CN109103252B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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CN109103252B
CN109103252B CN201710468976.5A CN201710468976A CN109103252B CN 109103252 B CN109103252 B CN 109103252B CN 201710468976 A CN201710468976 A CN 201710468976A CN 109103252 B CN109103252 B CN 109103252B
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isolation layer
fin
target
forming
semiconductor substrate
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CN109103252A (en
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners

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Abstract

A semiconductor device and a method of forming the same, wherein the method comprises: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a fin part; forming a target isolation layer covering partial side walls of the fin part on the surface of the semiconductor substrate, wherein the target isolation layer comprises a first target region and a second target region, the first target region is located on the surface of the semiconductor substrate and is adjacent to the fin part, the second target region is located on the surface of the semiconductor substrate and is adjacent to the first target region, a recess is formed in the first target region, and the fin part is exposed out of the side walls of the recess; and after the target isolation layer is formed, a grid electrode structure is formed, the grid electrode structure stretches across the fin part, part of the top surface of the covering fin part and part of the side wall surface, and the grid electrode structure is positioned on the surface of the target isolation layer and in the recess. The method improves the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
MOS transistors are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; the semiconductor device comprises a grid structure positioned on the surface of a semiconductor substrate, a source region positioned in the semiconductor substrate on one side of the grid structure and a drain region positioned in the semiconductor substrate on the other side of the grid structure. The operating principle of the MOS transistor is as follows: a voltage is applied to the gate structure, and a switching signal is generated by adjusting the current of a channel at the bottom of the gate structure.
With the development of semiconductor technology, the conventional planar MOS transistor has a weak ability to control channel current, resulting in a serious leakage current. Fin field effect transistors (Fin FETs) are emerging multi-gate devices, which generally include a Fin protruding from the surface of a semiconductor substrate, a gate structure covering a portion of the top surface and sidewall surfaces of the Fin, a source region in the Fin on one side of the gate structure, and a drain region in the Fin on the other side of the gate structure.
However, the performance of the semiconductor device formed by the conventional finfet needs to be improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a fin part; forming a target isolation layer covering partial side walls of the fin part on the surface of the semiconductor substrate, wherein the target isolation layer comprises a first target region and a second target region, the first target region is located on the surface of the semiconductor substrate and is adjacent to the fin part, the second target region is located on the surface of the semiconductor substrate and is adjacent to the first target region, a recess is formed in the first target region, and the fin part is exposed out of the side walls of the recess; and after the target isolation layer is formed, a grid electrode structure is formed, the grid electrode structure stretches across the fin part, part of the top surface of the covering fin part and part of the side wall surface, and the grid electrode structure is positioned on the surface of the target isolation layer and in the recess.
Optionally, the method for forming the target isolation layer includes: forming an initial isolation layer on the surface of the semiconductor substrate, wherein the initial isolation layer covers the side wall of the fin part and exposes the top surface of the fin part; etching the initial isolation layer by adopting a Certas etching process to form an intermediate isolation layer on the initial isolation layer, wherein the top surface of the intermediate isolation layer is lower than that of the fin part, and the intermediate isolation layer comprises a first intermediate region which is positioned on the surface of the semiconductor substrate and is adjacent to the fin part and a second intermediate region which is positioned on the surface of the semiconductor substrate and is adjacent to the first intermediate region; and etching the intermediate isolation layer by adopting a SiCoNi etching process, wherein the etching rate of the SiCoNi etching process to the first intermediate region is greater than that to the second intermediate region, so that the intermediate isolation layer forms the target isolation layer, the first intermediate region forms a first target region of the target isolation layer, and the second intermediate region forms a second target region of the target isolation layer.
Optionally, the material of the initial isolation layer, the intermediate isolation layer and the target isolation layer is silicon oxide.
Optionally, the Certas etching process includes remote dry etching and first in-situ annealing performed after the remote dry etching; the parameters of the remote dry etching comprise: the gas used comprises NH3And NF3，NH3The flow rate of (1) is 200sccm to 500sccm, NF3The gas flow of the gas is 20sccm to 200sccm, the pressure of the chamber is 0.1torr to 760torr, and the temperature is-40 ℃ to 25 ℃; the parameters of the first in-situ anneal include: the temperature is 60-100 ℃, and the pressure of the chamber is 0.1-760 torr.
Optionally, the SiCoNi etching process includes remote plasma etching and second in-situ annealing performed after the remote plasma etching; the parameters of the remote plasma etching comprise: the gas used comprises NH3And NF3，NH3The flow rate of (1) is 200sccm to 500sccm, NF3The gas flow of the gas is 20 sccm-200 sccm, the source radio frequency power is 50 watts-2000 watts, the bias voltage is 30 volts-500 volts, the pressure of the chamber is 0.1 torr-760 torr, and the temperature is-40 ℃ to 25 ℃; the parameters of the second in-situ anneal include: the temperature is 60-100 ℃, and the pressure of the chamber is 0.1-760 torr.
Optionally, a first distance is provided between the top surface of the second intermediate region and the top surface of the fin portion, and a second distance is provided between the top surface of the second target region and the top surface of the fin portion; the first distance is 5% -20% of the height of the fin portion, and the second distance is 30% -60% of the first distance.
Optionally, before the initial isolation layer is formed, a mask layer is arranged on the top surface of the fin portion; after the initial isolation layer is formed, the initial isolation layer covers the side wall of the fin portion and the side wall of the mask layer and exposes the top surface of the mask layer; the method for forming the semiconductor device further comprises the following steps: after the initial isolation layer is formed and before the Certas etching process is carried out, the mask layer is removed, and the top surface of the fin portion is exposed.
Optionally, the method further includes: oxidizing sidewalls of the fin portion prior to forming the initial isolation layer.
Optionally, the process of oxidizing the sidewalls of the fin portion includes an in-situ steam generation method.
Optionally, the method further includes: and before the initial isolation layer is formed, rounding the top angle of the fin part.
Optionally, the rounding treatment includes an annealing process.
Optionally, the parameters of the annealing process include: the gas used comprises H2And Ar, wherein the annealing temperature is 100-400 ℃.
Optionally, the depth of the recess is 1nm to 5 nm.
Optionally, the bottom width of the fin portion is greater than the top width of the fin portion.
Optionally, the method further includes: before forming a gate structure, forming a dummy gate structure, wherein the dummy gate structure crosses the fin part, part of the top surface and part of the side wall surface of the fin part, and is positioned on the surface of the target isolation layer and in the recess, and comprises a dummy gate electrode layer which crosses the fin part; forming source and drain doped regions in the fin parts on two sides of the pseudo gate structure; forming an interlayer dielectric layer on the surface of the target isolation layer after forming the source-drain doped region, wherein the interlayer dielectric layer covers the side wall of the pseudo gate structure, the fin part and the source-drain doped region and exposes the top surface of the pseudo gate structure; after the interlayer dielectric layer is formed, removing the pseudo gate electrode layer to form a gate opening; forming the gate structure in the gate opening.
The present invention also provides a semiconductor device comprising: a semiconductor substrate; a fin portion on the semiconductor substrate; the target isolation layer is positioned on the surface of the semiconductor substrate and covers partial side walls of the fin portion, the target isolation layer comprises a first target area positioned on the surface of the semiconductor substrate and adjacent to the fin portion and a second target area positioned on the surface of the semiconductor substrate and adjacent to the first target area, a recess is formed in the first target area, and the fin portion is exposed out of the side walls of the recess; the grid structure stretches across the fin part, part of the top surface of the covering fin part and part of the side wall surface, and is positioned on the surface of the target isolation layer and in the recess.
Optionally, the material of the target isolation layer comprises silicon oxide.
Optionally, the depth of the recess is 1nm to 5 nm.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor device provided by the technical scheme of the invention, the target isolation layer is formed, the first target area of the target isolation layer is provided with a recess, and the side wall of the recess is exposed out of the fin part. After the gate structure is formed, part of the gate structure is positioned in the recess, so that the gate structure is directly contacted with the region close to the surface of the target isolation layer in the crossed fin part, therefore, the control capability of the gate structure on the region close to the surface of the target isolation layer in the crossed fin part is enhanced, and the performance of the semiconductor device is improved.
In the semiconductor device provided by the technical scheme of the invention, the gate structure is directly contacted with the region close to the surface of the target isolation layer in the crossed fin part, so that the control capability of the gate structure on the region close to the surface of the target isolation layer in the crossed fin part is enhanced, and the performance of the semiconductor device is improved.
Drawings
Fig. 1to 3 are schematic structural views of a semiconductor device formation process;
fig. 4 to 13 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor devices formed by the prior art is poor.
Fig. 1to 3 are schematic structural views of a semiconductor device formation process.
Referring to fig. 1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 having a fin 110 thereon; an initial isolation layer 120 covering sidewalls of the fins 110 and exposing a top surface of the fins 110 is formed on the surface of the semiconductor substrate 100, and the top surface of the initial isolation layer 120 is flush with the top surface of the fins 110.
Referring to fig. 2, the initial isolation layer 120 (refer to fig. 1) is etched back, so that the initial isolation layer 120 forms a target isolation layer 121 covering a portion of the sidewalls of the fin 110.
Referring to fig. 3, after the target isolation layer 121 is formed, a gate structure 130 is formed, the gate structure 130 crosses the fin 110, covers a portion of the top surface and a portion of the sidewall surface of the fin 110, and the gate structure 130 is located on the surface of the target isolation layer 121.
However, the performance of the semiconductor device formed by the method is poor, and researches show that the reason is that:
during the etching back of the initial isolation layer 120, the portion of the initial isolation layer 120 contacting the fin 110 is blocked by the fin 110, so that the etching direction is limited. In the process of etching back the initial isolation layer 120, the region of the initial isolation layer 120 away from the fin 110 is not blocked by the fin 110, so that the region of the initial isolation layer 120 away from the fin 110 is etched in more directions. After the target isolation layer 121 is formed, the surface of the target isolation layer 121 close to the fin 110 is higher than the surface of the target isolation layer 121 far from the fin 110.
Second, to improve the controllability of the gate structure 130 over the fin 110, the gate structure 130 needs to have a larger height across the sidewalls of the fin 110. Accordingly, the target isolation layer 121 exposes the sidewalls of the fins 110 with a greater height. Then a greater depth of the initial isolation layer 120 needs to be etched back, and the time for etching back the initial isolation layer 120 is longer, accordingly, the thickness of the target isolation layer 121 in the region close to the fin 110 is much greater than the thickness of the target isolation layer 121 in the region far from the fin 110.
In summary, in the region of the fin 110 spanned by the gate structure 130 close to the target isolation layer 121, there is more material of the target isolation layer 121 between the gate structure 130 and the fin 110, which results in a reduced controllability of the gate structure 130 over the region of the spanned fin 110 close to the target isolation layer 121, and thus results in a lower performance of the semiconductor device.
On the basis, the invention provides a method for forming a semiconductor device, which comprises the steps of forming a target isolation layer, wherein the target isolation layer comprises a first target area and a second target area, the first target area is positioned on the surface of a semiconductor substrate and is adjacent to a fin part, the second target area is positioned on the surface of the semiconductor substrate and is adjacent to the first target area, a recess is formed in the first target area, and the fin part is exposed out of the side wall of the recess; and forming a gate structure crossing the fin part, wherein the gate structure is positioned on the surface of the target isolation layer and in the recess. The method improves the performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 13 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 4, a semiconductor substrate 200 is provided, the semiconductor substrate 200 having a fin 210 thereon.
The semiconductor substrate 200 may be single crystal silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like; the semiconductor substrate 200 may be a bulk material or may be a composite structure, such as silicon-on-insulator; the semiconductor substrate 200 may also be other semiconductor materials, which are not illustrated here. In this embodiment, the material of the semiconductor substrate 200 is silicon.
The fin 210 is formed by patterning the semiconductor substrate 200. Alternatively, a fin material layer is formed on the semiconductor substrate 200, and the fin 210 is formed by patterning the fin material layer.
The number of the fins 210 is one or more.
The top surface of fin 210 has a mask layer 220.
In the present embodiment, the mask layer 220 has a stacked structure, and the mask layer 220 includes a first mask layer (not shown) on a top surface of the fin 210 and a second mask layer (not shown) on a top surface of the first mask layer. The material of the first mask layer comprises silicon oxide, and the material of the second mask layer comprises silicon nitride.
The first mask layer may reduce stress of the second mask layer on the top surface of fin 210.
In other embodiments, the mask layer is a single-layer structure, and the material of the mask layer includes silicon nitride or silicon oxynitride.
In one embodiment, the method of forming the fin 210 and the mask layer 220 includes: forming a fin material layer on the semiconductor substrate 200; forming a mask material layer on the surface of the fin material layer; the masking material layer and the fin material layer are patterned to form a masking layer 220 and a fin 210. The fin 210 corresponds to the fin material layer, and the mask layer 220 corresponds to the mask material layer.
The width of the bottom of fin 210 is greater than the width of the top of fin 210 due to the etching process. The bottom width and the top width of the fin 210 both refer to the dimension in the direction parallel to the surface of the semiconductor substrate 200 and perpendicular to the extension direction of the fin 210.
Next, a target isolation layer covering a partial sidewall of the fin 210 is formed on the surface of the semiconductor substrate 200, where the target isolation layer includes a first target region located on the surface of the semiconductor substrate 200 and adjacent to the fin 210, and a second target region located on the surface of the semiconductor substrate 200 and adjacent to the first target region, where the first target region has a recess therein, and the sidewall of the recess exposes the fin 210.
The method for forming the target isolation layer comprises the following steps: forming an initial isolation layer on the surface of the semiconductor substrate 200, wherein the initial isolation layer covers the sidewall of the fin portion 210 and exposes the top surface of the fin portion 210; etching the initial isolation layer by adopting a Certas etching process to form an intermediate isolation layer on the initial isolation layer, wherein the top surface of the intermediate isolation layer is lower than that of the fin portion 210, and the intermediate isolation layer comprises a first intermediate region which is positioned on the surface of the semiconductor substrate 200 and is adjacent to the fin portion 210 and a second intermediate region which is positioned on the surface of the semiconductor substrate 200 and is adjacent to the first intermediate region; and etching the intermediate isolation layer by adopting a SiCoNi etching process, wherein the etching rate of the SiCoNi etching process to the first intermediate region is greater than that to the second intermediate region, so that the intermediate isolation layer forms the target isolation layer, the first intermediate region forms a first target region of the target isolation layer, and the second intermediate region forms a second target region of the target isolation layer.
In this embodiment, the method further includes: before forming the initial isolation layer, oxidizing the sidewalls of the fin 210; before forming the initial isolation layer, the top corners of the fin 210 are rounded.
Referring to fig. 5, sidewalls of the fin 210 are oxidized; the top corners of the fins 210 are rounded.
The process of oxidizing the sidewalls of the fin 210 is a wet oxidation process or a dry oxidation process.
After the sidewalls of fin 210 are oxidized, an oxide layer 230 is formed on the sidewall surface of fin 210.
The effect of oxidizing the fin 210 includes: the etching damage on the sidewall surface of fin 210 during the formation of fin 210 is repaired.
In this embodiment, the process of oxidizing the sidewalls of the fin 210 is an in-situ steam generation method, which has the following advantages: the oxide layer 230 formed after oxidizing the sidewalls of the fin portion 210 is dense, and the sidewalls of the fin portion 210 are better repaired.
The smoothing treatment functions include: the top angle of the fin portion 210 becomes more smooth, the subsequent gate structure crosses the fin portion 210, and after voltage is applied to the gate structure, the electric field intensity at the edge of the top surface of the fin portion 210 is prevented from being too large, the phenomenon of point discharge at the edge of the top surface of the fin portion 210 is prevented from occurring, and then the gate dielectric layer is prevented from being broken down.
The rounding treatment includes an annealing process.
The parameters of the annealing process comprise: the gas used comprises H2And Ar, wherein the annealing temperature is 100-400 ℃.
After the sidewalls of the fin portions 210 are oxidized, rounding the top corners of the fin portions 210; alternatively, after rounding the top corners of the fin 210, the sidewalls of the fin 210 are oxidized.
A method of forming the target isolation layer is described below with reference to fig. 6 to 8.
An initial isolation layer 240 is formed on the surface of the semiconductor substrate 200, wherein the initial isolation layer 240 covers the sidewalls of the fin 210 and exposes the top surface of the fin 210.
Referring to fig. 6, an initial isolation layer 240 is formed on the surface of the semiconductor substrate 200, wherein the initial isolation layer 240 covers sidewalls of the fin 210 and sidewalls of the mask layer 220 and exposes a top surface of the mask layer 220.
The material of the initial isolation layer 240 includes silicon oxide.
The method of forming the initial isolation layer 240 includes: forming an initial isolation film (not shown) on the semiconductor substrate 200; the initial isolation film is planarized until the top surface of the mask layer 220 is exposed, forming an initial isolation layer 240.
Referring to fig. 7, after the initial isolation layer 240 is formed, the mask layer 220 (see fig. 6) is removed to expose the top surface of the fin 210.
The process of removing the mask layer 220 is an etching process.
In other embodiments, an initial isolation film is formed on a semiconductor substrate; and flattening the initial isolation film and the mask layer until the top surface of the fin part is exposed to form an initial isolation layer, wherein the initial isolation layer covers the side wall of the fin part and exposes the top surface of the fin part.
Referring to fig. 8, the initial isolation layer 240 (see fig. 7) is etched by a Certas etching process, such that the initial isolation layer 240 forms an intermediate isolation layer 241, a top surface of the intermediate isolation layer 241 is lower than a top surface of the fin 210, and the intermediate isolation layer 241 includes a first intermediate region located on the surface of the semiconductor substrate 200 and adjacent to the fin 210, and a second intermediate region located on the surface of the semiconductor substrate 200 and adjacent to the first intermediate region.
The direction from the first intermediate region to the second intermediate region is perpendicular to the extending direction of the fin 210 and parallel to the surface of the semiconductor substrate 200.
After the mask layer 220 is removed, a Certas etching process is performed.
In one embodiment, the Certas etching process comprises remote dry etching and a first in-situ anneal performed after the remote dry etching. The parameters of the remote dry etching comprise: the gas used comprises NH3And NF3，NH3The flow rate of the gas is 200sccm to 500sccm,NF3the gas flow of the gas is 20sccm to 200sccm, the pressure of the chamber is 0.1torr to 760torr, such as 10torr, 100torr or 400torr, and the temperature is-40 ℃ to 25 ℃, such as 20 ℃; the parameters of the first in-situ anneal include: the temperature is 60 ℃ to 100 ℃, such as 80 ℃, and the pressure of the chamber is 0.1torr to 760torr, such as 10torr, 100torr, or 400 torr.
Specifically, during the remote dry etching, NH is added3And NF3The precursor gas formed reacts with the initial barrier layer 240 surface material to form hexafluorosilicone ((NH)4)SiF6) And deposited on the surface of the initial isolation layer 240; in the first in-situ annealing process, under the action of the temperature of 60-100 ℃, hexafluoro-silicon ammonia ((NH) on the surface of the initial isolation layer 2404)SiF6) Decomposing into gaseous by-products including silicon tetrafluoride (SiF)4) Ammonia (NH)3) And Hydrogen Fluoride (HF); the gaseous by-products are then pumped away.
It should be noted that the remote dry etching and the first in-situ annealing are performed in the same etching machine. In the remote dry etching, source radio frequency power and bias voltage, NH, are not applied3And NF3Since the precursor gas is not converted into plasma, hexafluoro-silicon-ammonia ((NH)) on the surface of the initial isolation layer 2404)SiF6) The hexa-fluorosilicone ((NH) without being impacted by plasma to affect different areas of the surface of the initial isolation layer 2404)SiF6) And (4) thickness. Therefore, hexafluorosilicone ammonia ((NH) is present in different areas of the surface of the initial isolation layer 2404)SiF6) The thickness distribution is relatively uniform.
For convenience of explanation, a region of the initial isolation layer 240 corresponding to the second intermediate region is referred to as an initial intermediate region. Notably hexafluorosilamine ((NH) of the initial intermediate zone surface4)SiF6) The thickness distribution is relatively uniform. Therefore, after the first in-situ annealing, the surface flatness of the second intermediate region is better.
In a practical process, the Certas etching process comprises a plurality of cycles of a first sub-etching process, wherein the first sub-etching process comprises one time of remote dry etching, one time of first in-situ annealing correspondingly and one time of steps of extracting gaseous byproducts correspondingly.
It should be noted that, in the course of the Certas etching process, the etching direction of the portion of the initial isolation layer 240 in contact with the fin 210 is limited due to the blocking of the fin 210, and the second middle region of the initial isolation layer 240 is not blocked by the fin 110, so that the second middle region of the initial isolation layer 240 is etched in more directions. Therefore, after the formation of the intermediate isolation layer 241, the surface of the first intermediate region close to the fin portion 210 is slightly higher than the surface of the second intermediate region.
Since the distance from the surface of the second intermediate region to the top surface of the fin 210 is smaller than the distance from the surface of the subsequent second target region to the top surface of the fin 210, the depth of the initial isolation layer 240 etched by the Certas etching process is smaller, and accordingly, the height difference between the surface of the first intermediate region close to the fin 210 and the surface of the second intermediate region is smaller.
The top surface of the second intermediate region has a first distance to the top surface of fin 210.
In one embodiment, the first distance is 5% to 20%, such as 5%, 10%, or 20%, of the height of fin 210. The height of the fin 210 refers to a dimension of the fin 210 in a direction normal to the surface of the semiconductor substrate 200.
Referring to fig. 9, the intermediate isolation layer 241 (refer to fig. 8) is etched using a SiCoNi etching process, which has an etching rate for the first intermediate region greater than that for the second intermediate region, such that the intermediate isolation layer 241 forms the target isolation layer 242, and the first intermediate region forms the first target region of the target isolation layer 242, and the second intermediate region forms the second target region of the target isolation layer 242.
The material of the target isolation layer 242 includes silicon oxide.
The target isolation layer 242 includes a first target region located on the surface of the semiconductor substrate 200 and adjacent to the fin 210, and a second target region located on the surface of the semiconductor substrate 200 and adjacent to the first target region, the first target region has a recess 243 therein, and a sidewall of the recess 243 exposes the fin 210.
The direction from the first target region to the second target region is perpendicular to the extending direction of the fin 210 and parallel to the surface of the semiconductor substrate 200.
In the width direction of the fin 210, the size of the first target region is 10% to 40% of the size of the second target region.
In one embodiment, the SiCoNi etching process comprises remote plasma etching and a second in-situ annealing after the remote plasma etching; the parameters of the remote plasma etching comprise: the gas used comprises NH3And NF3，NH3The flow rate of (1) is 200sccm to 500sccm, NF3The gas flow of the gas is 20sccm to 200sccm, the source radio frequency power is 50 watts to 2000 watts, such as 50 watts, 300 watts, 500 watts, 800 watts, 1500 watts or 2000 watts, the bias voltage is 30 volts to 500 volts, such as 30 volts, 50 volts, 100 volts, 200 volts or 500 volts, the chamber pressure is 0.1torr to 760torr, such as 10torr, 100torr or 400torr, and the temperature is-40 ℃ to 25 ℃, such as 20 ℃; the parameters of the second in-situ anneal include: the temperature is 60 ℃ to 100 ℃, such as 80 ℃, and the pressure of the chamber is 0.1torr to 760torr, such as 10torr, 100torr, or 400 torr.
Specifically, during the remote plasma etching, NH is added3And NF3The precursor gas thus formed is converted into ammonia fluoride (NH) by plasma4F) Plasma and ammonia difluoride (NH)4F2) Plasma, the formed plasma reacts with the surface material of the middle isolation layer 241 to form hexa-fluoro-silicon-ammonia ((NH)4)SiF6) And deposited on the surface of the intermediate isolation layer 241; in the second in-situ annealing process, under the action of the temperature of 60-100 ℃, hexafluoro-silicon ammonia ((NH) on the surface of the middle isolation layer 2414)SiF6) Decomposing into gaseous by-products including silicon tetrafluoride (SiF)4) Ammonia (NH)3) And Hydrogen Fluoride (HF); the gaseous by-products are then pumped away.
It should be noted that the remote plasma etching and the second in-situ annealing are performed in the same etching machine. Applying source RF power and bias voltage, NH, during the remote plasma etch3And NF3The precursor gas thus constituted is converted into plasma, and hexafluoro-silicon-ammonia ((NH) on the surface of the intermediate isolation layer 241 is formed4)SiF6) The plasma will impact the hexa-fluorosilicone ammonia ((NH) in different areas on the surface of the middle isolation layer 2414)SiF6) And (4) thickness.
Specifically, in the remote plasma etching, hexa-fluoro-silicon ammonia ((NH) on the surface of the isolation layer 241 in the plasma collision process4)SiF6) The first intermediate region is blocked by the fin 210, thereby making hexafluoro-silicon ammonia ((NH) on the surface of the first intermediate region4)SiF6) The degree of collision by the plasma is less than that of the hexafluoro-silicon ammonia ((NH) on the surface of the second intermediate region4)SiF6) The degree of collision by the plasma. Accordingly, hexa-fluorosilicone ammonia ((NH) deposited on the surface of the second intermediate zone4)SiF6) Is less than the hexa-fluorosilicon ammonia ((NH) deposited on the surface of the first intermediate zone4)SiF6) Is measured. Accordingly, the surface of the first intermediate region is etched to a greater extent than the surface of the second intermediate region.
In a practical process, the SiCoNi etching process includes a plurality of cycles of a second sub-etching process, the second sub-etching process including a single remote plasma etch, a corresponding single second in-situ anneal, and a corresponding single step of extracting gaseous byproducts.
The top surface of the second target region has a second distance to the top surface of fin 210.
In one embodiment, the first distance is 5% to 20% of the height of the fin 210, and the second distance is 30% to 60% of the first distance. The meaning of the first distance and the second distance selecting this range includes: the distance between the surface of the first middle region of the middle isolation layer 241 close to the fin 210 and the surface of the second middle region is ensured to be small, so that the depth of the recess 243 is not too small, and the flatness of the top surface of the second target region of the target isolation layer 242 is good.
The depth of the recess 243 is 1nm to 5 nm. If the depth of the depression 243 is selected from this range, the meaning includes: the capability of filling the recess 243 with the subsequent gate structure is better, and the occurrence of voids is avoided; and the gate structure has better control over the bottom region of the fin 210 that it crosses.
After the target isolation layer 242 is formed, a gate structure is formed, wherein the gate structure crosses the fin 210, covers a portion of the top surface and a portion of the sidewall surface of the fin 210, and is located on the surface of the target isolation layer 242 and in the recess 243.
In this embodiment, the method further includes: before forming a gate structure, forming a dummy gate structure, wherein the dummy gate structure crosses the fin portion 210, part of the top surface and part of the sidewall surface of the covering fin portion 210, and is located on the surface of the target isolation layer 242 and in the recess 243, and the dummy gate structure comprises a dummy gate electrode layer, and the dummy gate electrode layer crosses the fin portion 210; forming source and drain doped regions in the fin portions 210 at two sides of the dummy gate structure; after forming the source-drain doped regions, forming an interlayer dielectric layer on the surface of the target isolation layer 242, wherein the interlayer dielectric layer covers the sidewalls of the dummy gate structure, the fin portion 210 and the source-drain doped regions and exposes the top surface of the dummy gate structure; after the interlayer dielectric layer is formed, removing the pseudo gate electrode layer to form a gate opening; and forming a gate structure in the gate opening.
Referring to fig. 10, a dummy gate structure 250 is formed, wherein the dummy gate structure 250 crosses the fin 210, covers a portion of the top surface and a portion of the sidewall surface of the fin 210, and the dummy gate structure 250 is located on the surface of the target isolation layer 242 and in the recess 243 (refer to fig. 9).
The dummy gate structure 250 includes a dummy gate dielectric layer 251 and a dummy gate electrode layer 252 on the surface of the dummy gate electrode layer 251. The dummy gate electrode layer 251 spans the fin 210, covering a portion of the top surface and a portion of the sidewall surface of the fin 210.
In this embodiment, the dummy gate dielectric layer 251 is made of silicon oxide, and the dummy electrode layer 252 is made of polysilicon.
In this embodiment, the dummy gate dielectric layer 251 is formed by oxidizing the surface of the fin portion 210, and accordingly, the dummy gate dielectric layer 251 is only located on a portion of the sidewall surface and a portion of the top surface of the fin portion 210. Correspondingly, the dummy gate electrode layer 252 is located on the surface of the dummy gate dielectric layer 251, and the dummy gate electrode layer 252 further extends to a portion of the surface of the target isolation layer 242 and the recess 243.
In addition, because the dummy gate dielectric layer 251 is formed by adopting an oxidation process, the density of the dummy gate dielectric layer 251 is higher, and the breakdown resistance of the semiconductor device is improved.
Specifically, in this embodiment, the in-situ steam generation method (ISSG) is used to form the dummy gate dielectric layer 251, which has the following advantages: the interface between the dummy gate dielectric layer 251 and the fin portion 210 is good, so that the carrier mobility in the fin portion 210 and the reliability of a semiconductor device are improved; the quality of the dummy gate dielectric layer 251 is good, and the breakdown resistance of the dummy gate dielectric layer 251 is good.
In other embodiments, the dummy gate dielectric layer is formed by deposition, the dummy gate dielectric layer crosses the fin portion, the dummy gate dielectric layer is located on a portion of the surface of the target isolation layer and the inner wall of the recess, and covers a portion of the top surface and a portion of the surface of the side wall of the fin portion, and correspondingly, the dummy gate electrode layer is located on the surface of the dummy gate electrode layer.
In the process of forming the dummy gate structure 250, a dummy gate mask layer 260 on the top surface of the dummy gate structure 250 is also formed. The dummy gate mask layer 260 is made of silicon nitride.
Referring to fig. 11, a source-drain doped region (not shown) is formed in the fin portion 210 at two sides of the dummy gate structure 250; after the source-drain doped region is formed, an interlayer dielectric layer 270 is formed on the surface of the target isolation layer 242, and the interlayer dielectric layer 270 covers the sidewall of the dummy gate structure 250, the fin portion 210 and the source-drain doped region and exposes the top surface of the dummy gate structure 250.
Specifically, the step of forming the interlayer dielectric layer 270 includes: forming an interlayer dielectric film on the surface of the target isolation layer 242, wherein the interlayer dielectric film covers the dummy gate structure 250, the fin portion 210, the source-drain doped region and the dummy gate mask layer 260; and flattening the interlayer dielectric film and the dummy gate mask layer 260 until the top surface of the dummy gate structure 250 is exposed to form an interlayer dielectric layer 270.
The interlayer dielectric layer 270 is made of silicon oxide, silicon oxycarbide or silicon oxynitride.
Referring to fig. 12, after the interlayer dielectric layer 270 is formed, the dummy gate electrode layer 252 (see fig. 11) is removed to form a gate opening 271.
In this embodiment, the dummy gate structure 250 is located at an edge region of the semiconductor substrate 200, and the edge region of the semiconductor substrate 200 is used for forming a peripheral logic circuit. Accordingly, the dummy gate electrode layer 252 is removed and the dummy gate dielectric layer 251 remains to form a gate opening 271.
In other embodiments, the dummy gate structure is located in a core region of the semiconductor substrate, the edge region of the semiconductor substrate 200 is located at a periphery of the core region of the semiconductor substrate, and the core region of the semiconductor substrate is used for forming a core circuit. And correspondingly, removing the dummy gate electrode layer and the dummy gate dielectric layer to form a gate opening.
Referring to fig. 13, a gate structure 280 is formed in the gate opening 271 (refer to fig. 12).
The gate structure 280 spans the fin 210, covers a portion of the top surface and a portion of the sidewall surface of the fin 210, and the gate structure 280 is located on the surface of the target isolation layer 242 and in the recess 243.
The gate structure 280 includes a gate dielectric layer 281 on the sides and bottom of the gate opening 271 and a gate electrode layer 282 over the gate dielectric layer 281.
The gate dielectric layer 281 is made of a high-K (K is greater than 3.9) dielectric material, and the gate electrode layer 282 is made of a metal.
In this embodiment, the gate dielectric layer 281 is also located on the dummy gate dielectric layer 251. The total thickness of the gate dielectric layer 281 and the dummy gate dielectric layer 251 is greater than the thickness of the gate dielectric layer 281, thereby enhancing the breakdown resistance of the semiconductor device.
In other embodiments, the dummy gate electrode layer and the dummy gate dielectric layer are removed to form the gate opening, and accordingly, no dummy gate dielectric layer is arranged between the gate dielectric layer and the fin portion.
Accordingly, the present embodiment further provides a semiconductor device formed by the above method, with reference to fig. 13, including: a semiconductor substrate 200; fin 210 on semiconductor substrate 200; a target isolation layer 242 on the surface of the semiconductor substrate 200 and covering a portion of the sidewall of the fin portion 210, wherein the target isolation layer 242 includes a first target region on the surface of the semiconductor substrate 200 and adjacent to the fin portion 210, and a second target region on the surface of the semiconductor substrate 200 and adjacent to the first target region, the first target region has a recess 243 therein (refer to fig. 9), and the sidewall of the recess 243 exposes the fin portion 210; a gate structure 280, wherein the gate structure 280 spans the fin 210, covers a portion of the top surface and a portion of the sidewall surface of the fin 210, and the gate structure 280 is located on the surface of the target isolation layer 242 and in the recess 243 (refer to fig. 9).
The material of the target isolation layer 242 includes silicon oxide.
The depth of the recess 243 is 1nm to 5 nm.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a fin part;
forming a target isolation layer covering partial side walls of the fin part on the surface of the semiconductor substrate, wherein the target isolation layer comprises a first target region and a second target region, the first target region is located on the surface of the semiconductor substrate and is adjacent to the fin part, the second target region is located on the surface of the semiconductor substrate and is adjacent to the first target region, a recess is formed in the first target region, and the fin part is exposed out of the side walls of the recess;
after the target isolation layer is formed, a grid electrode structure is formed, the grid electrode structure stretches across the fin part, part of the top surface of the covering fin part and part of the side wall surface, and the grid electrode structure is located on the surface of the target isolation layer and in the recess;
the method for forming the target isolation layer comprises the following steps: forming an initial isolation layer on the surface of the semiconductor substrate, wherein the initial isolation layer covers the side wall of the fin part and exposes the top surface of the fin part; etching the initial isolation layer to form an intermediate isolation layer, wherein the top surface of the intermediate isolation layer is lower than that of the fin portion, and the intermediate isolation layer comprises a first intermediate region located on the surface of the semiconductor substrate and adjacent to the fin portion and a second intermediate region located on the surface of the semiconductor substrate and adjacent to the first intermediate region; and etching the intermediate isolation layer, wherein the etching rate of the etching process for etching the intermediate isolation layer to the first intermediate region is greater than the etching rate to the second intermediate region, so that the intermediate isolation layer forms the target isolation layer, the first intermediate region forms a first target region of the target isolation layer, and the second intermediate region forms a second target region of the target isolation layer.
2. The method of claim 1, wherein the initial isolation layer is etched using a Certas etching process; and etching the intermediate isolation layer by adopting a SiCoNi etching process.
3. The method of forming a semiconductor device according to claim 2, wherein a material of the initial isolation layer, the intermediate isolation layer, and the target isolation layer is silicon oxide.
4. The method of claim 3, wherein the Certas etching process comprises a remote dry etching and a first in-situ anneal performed after the remote dry etching; the parameters of the remote dry etching comprise: the gas used comprises NH3And NF3，NH3The flow rate of (1) is 200sccm to 500sccm, NF3The gas flow of the gas is 20sccm to 200sccm, the pressure of the chamber is 0.1torr to 760torr, and the temperature is-40 ℃ to 25 ℃; the parameters of the first in-situ anneal include: the temperature is 60-100 ℃, and the pressure of the chamber is 0.1-760 torr.
5. The method of claim 3, wherein the SiCoNi etch process comprises a remote plasma etch and a second in-situ anneal after the remote plasma etch; the parameters of the remote plasma etching comprise: the gas used comprises NH3And NF3，NH3The flow rate of (1) is 200sccm &500sccm，NF3The gas flow of the gas is 20 sccm-200 sccm, the source radio frequency power is 50 watts-2000 watts, the bias voltage is 30 volts-500 volts, the pressure of the chamber is 0.1 torr-760 torr, and the temperature is-40 ℃ to 25 ℃; the parameters of the second in-situ anneal include: the temperature is 60-100 ℃, and the pressure of the chamber is 0.1-760 torr.
6. The method of claim 2, wherein a top surface of the second intermediate region has a first distance to a top surface of the fin, and a top surface of the second target region has a second distance to the top surface of the fin; the first distance is 5% -20% of the height of the fin portion, and the second distance is 30% -60% of the first distance.
7. The method of claim 2, wherein a mask layer is formed on a top surface of the fin before the initial isolation layer is formed; after the initial isolation layer is formed, the initial isolation layer covers the side wall of the fin portion and the side wall of the mask layer and exposes the top surface of the mask layer; the method for forming the semiconductor device further comprises the following steps: after the initial isolation layer is formed and before the Certas etching process is carried out, the mask layer is removed, and the top surface of the fin portion is exposed.
8. The method for forming a semiconductor device according to claim 7, further comprising: oxidizing sidewalls of the fin portion prior to forming the initial isolation layer.
9. The method of claim 8, wherein the oxidizing the sidewalls of the fin comprises in-situ steam generation.
10. The method for forming a semiconductor device according to claim 7, further comprising: and before the initial isolation layer is formed, rounding the top angle of the fin part.
11. The method of claim 10, wherein the rounding comprises an annealing process.
12. The method of claim 11, wherein the parameters of the annealing process comprise: the gas used comprises H2And Ar, wherein the annealing temperature is 100-400 ℃.
13. The method for forming a semiconductor device according to claim 1, wherein a depth of the recess is 1nm to 5 nm.
14. The method of claim 1, wherein a bottom width of the fin is greater than a top width of the fin.
15. The method for forming a semiconductor device according to claim 1, further comprising: before forming a gate structure, forming a dummy gate structure, wherein the dummy gate structure crosses the fin part, part of the top surface and part of the side wall surface of the fin part, and is positioned on the surface of the target isolation layer and in the recess, and comprises a dummy gate electrode layer which crosses the fin part; forming source and drain doped regions in the fin parts on two sides of the pseudo gate structure; forming an interlayer dielectric layer on the surface of the target isolation layer after forming the source-drain doped region, wherein the interlayer dielectric layer covers the side wall of the pseudo gate structure, the fin part and the source-drain doped region and exposes the top surface of the pseudo gate structure; after the interlayer dielectric layer is formed, removing the pseudo gate electrode layer to form a gate opening; forming the gate structure in the gate opening.
16. A semiconductor device formed by the method for forming a semiconductor device according to any one of claims 1to 15, comprising:
a semiconductor substrate;
a fin portion on the semiconductor substrate;
the target isolation layer is positioned on the surface of the semiconductor substrate and covers partial side walls of the fin portion, the target isolation layer comprises a first target area positioned on the surface of the semiconductor substrate and adjacent to the fin portion and a second target area positioned on the surface of the semiconductor substrate and adjacent to the first target area, a recess is formed in the first target area, and the fin portion is exposed out of the side walls of the recess;
the grid structure stretches across the fin part, part of the top surface of the covering fin part and part of the side wall surface, and is positioned on the surface of the target isolation layer and in the recess.
17. The semiconductor device of claim 16, wherein a material of the target isolation layer comprises silicon oxide.
18. The semiconductor device according to claim 16, wherein a depth of the recess is 1nm to 5 nm.
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