CN109103149A - 一种改进型的双基岛封装结构 - Google Patents
一种改进型的双基岛封装结构 Download PDFInfo
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- CN109103149A CN109103149A CN201710468331.1A CN201710468331A CN109103149A CN 109103149 A CN109103149 A CN 109103149A CN 201710468331 A CN201710468331 A CN 201710468331A CN 109103149 A CN109103149 A CN 109103149A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- Microelectronics & Electronic Packaging (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明提供了一种改进型的双基岛封装结构,包括塑封体、外引脚、一个通过散热材质外露的基岛,一个不外露的基岛,两个芯片。本发明解决了传统双基岛封装结构存在的散热问题,同时解决了单基岛封装结构性能不佳和集成度低的问题。本发明使制造成本得到降低,且能满足电子行业小型材经,微型化的发展需求。
Description
技术领域
本发明涉及集成电路领域,尤其涉及集成电路芯片封装技术领域。
背景技术
现有的集成电路芯片封装技术多采用在一个塑封体上封装一颗芯片,一个塑封体里有一个基岛,芯片放在基岛上。当两个芯片需要组合使用时,现有的技术多将两个芯片封装在两个塑封体里,通过外围连线连接,这样可以大大保证芯片的可靠性,但存在性能不佳的问题,由于采用两个塑封体,成本也很高。
目前,出现了一种双基岛的封装结构,在一个塑封体里同时存在两个基岛,将两个芯片分别放置两个基岛里,由于将两个相关联的芯片安装在一个塑封体内部的两个基岛里,其性能稳定性得到大大增强,成本也大大降低。但是将两个芯片放在一个塑封体里,芯片自身工作散发的热能不能很好的排出,这会大大影响芯片的性能,甚至导致芯片损坏。
发明内容
本发明提供了一种改进型的双基岛封装结构,将两个基岛中的一个设计成通过散热材质使基岛外露,外露基岛上可以放置功耗比较大的芯片;另一个基岛仍然全部包裹在塑封体里。
本发明解决了传统双基岛封装结构的散热问题,同时解决了单基岛性能不佳和集成度低的问题,本发明使制造成本得到降低,且能满足电子行业小型材经,微型化的发展需求。
附图说明
图1为本发明改进型的双基岛封装结构。
具体实施方式
图1是本发明改进型的双基岛封装结构,它包括塑封体1、外引脚4、芯片3、芯片6、基岛2、基岛5,芯片6放置在基岛5上,芯片3放置在基岛2上,封装时将芯片上的PAD通过连线连接到外引脚上。
本发明的独特之处在于将基岛2和基岛5中的一个基岛外露,将它通过散热材质从封装体的体部引出,基岛外露,其封装的热容积比较大,具有良好的散热特性。与外露基岛相接触的散热材质,可以在装配过程中通过回流焊安装到PCB上。这样可使电路板铺铜的接地区域充当散热片。
基岛2和基岛5中的另一个基岛不外露,全部包裹在塑封体里,此基岛不外露可以很好的满足封装所要求的安全爬电距离和电气间隙,使芯片可靠性大大提高。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (3)
1.一种改进型的双基岛封装结构,其特征在于,包含:塑封体、外引脚、两个芯片、两个基岛。
2.一种改进型的双基岛封装结构,其特征在于,所述两个芯片分别放置在两个不同的基岛里。
3.一种改进型的双基岛封装结构,其特征在于,所述的两个基岛一个全部包裹在塑封体里,一个通过散热材质外露在塑封体外。
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CN201710468331.1A CN109103149A (zh) | 2017-06-20 | 2017-06-20 | 一种改进型的双基岛封装结构 |
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- 2017-06-20 CN CN201710468331.1A patent/CN109103149A/zh active Pending
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Application publication date: 20181228 |