CN109087912A - Multichip packaging structure and preparation method thereof with chamber - Google Patents
Multichip packaging structure and preparation method thereof with chamber Download PDFInfo
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- CN109087912A CN109087912A CN201810911145.5A CN201810911145A CN109087912A CN 109087912 A CN109087912 A CN 109087912A CN 201810911145 A CN201810911145 A CN 201810911145A CN 109087912 A CN109087912 A CN 109087912A
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- 238000005516 engineering process Methods 0.000 abstract description 6
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Abstract
Present invention discloses a kind of multichip packaging structure and preparation method thereof with chamber, encapsulating structure include: package substrate, and the side of package substrate has several external pins, and package substrate has chamber；Functional chip is set in chamber, and functional chip has several first electrodes；Filter chip is set to the top of package substrate, and filter chip has the second upper surface and the second lower surface being oppositely arranged, and the second lower surface is arranged face-to-face with upper surface of base plate, and filter chip has several second electrodes；Cofferdam cooperates with the second lower surface and upper surface of base plate and encloses to set to form cavity；Several interconnection structures, for several first electrodes, several second electrodes and several external pins to be connected.The present invention utilizes encapsulation technology that in same package substrate, the highly integrated of multi-chip is may be implemented in two different chip packages, improves the utilization rate of package substrate, and then realize the miniaturization of encapsulating structure.
Description
Technical field
The present invention relates to field of semiconductor package more particularly to a kind of multichip packaging structures and its production with chamber
Method.
Background technique
To cater to the increasingly light and short development trend of electronic product, filter and radio-frequency transmissions component/receiving unit are needed
It is highly integrateable in the encapsulating structure of limited areal, forms system in package (SystemInPackage, SIP) structure, with
Reduce the size of hardware system.
For the filter and RF front-end module encapsulation integration technology in system-in-package structure, there are still suitable in the industry
More technical problem urgent need to resolve, for example, connection structure, multiple chips between the protection structure of filter, multiple chips
Layout etc..
Summary of the invention
The purpose of the present invention is to provide a kind of multichip packaging structure and preparation method thereof with chamber.
One of for achieving the above object, an embodiment of the present invention provides a kind of multi-chip package knot with chamber
Structure, comprising:
Package substrate has the upper surface of base plate and base lower surface being oppositely arranged, and the side of the package substrate has
Several external pins, and the package substrate has chamber；
Functional chip is set in the chamber, and the functional chip has the first upper surface and first being oppositely arranged
Lower surface, and the functional chip has several first electrodes；
Filter chip, is set to the top of the package substrate, and the filter chip has second be oppositely arranged
Upper surface and the second lower surface, second lower surface is arranged face-to-face with the upper surface of base plate, and the filter chip
With several second electrodes；
Cofferdam cooperates with second lower surface and the upper surface of base plate and encloses to set to form cavity；
Several interconnection structures, for several first electrodes, several second electrodes and several external pins to be connected.
As the further improvement of an embodiment of the present invention, there are several outsides to draw for the side of the base lower surface
Foot, the package substrate have several through-holes, and the second electrode is located at second lower surface, and the interconnection structure passes through institute
It states through-hole and the second electrode, the first electrode and the external pin is connected.
As the further improvement of an embodiment of the present invention, the first electrode is located at first lower surface, described
Interconnection structure includes metal layer, the metal layer fill the through-hole interior zone and extend toward the base lower surface direction and
The first electrode is connected.
As the further improvement of an embodiment of the present invention, the multichip packaging structure further includes being set to the base
Second insulation of the first insulating layer, cladding first insulating layer and the metal layer between plate lower surface and the metal layer
The metal layer is connected by the hole in the second insulating layer and extends toward the lower surface direction of the second insulating layer for layer
Lower rewiring layer and the cladding second insulating layer and the lower third insulating layer for rerouting layer, the external pin connect
Connect the lower rewiring layer, and external pin described in the third insulating layer exposing.
As the further improvement of an embodiment of the present invention, the cofferdam includes first enclosing on the inside of the through-hole
Weir and the second cofferdam on the outside of the through-hole.
As the further improvement of an embodiment of the present invention, several through-holes, which enclose, sets the Internal periphery to be formed connection described first
Cofferdam, several through-holes, which enclose, sets the outer profile to be formed connection second cofferdam, and first cofferdam and second cofferdam are mutual
Connection.
As the further improvement of an embodiment of the present invention, direction of second cofferdam towards separate first cofferdam
The lateral border for extending up to second cofferdam is flushed with the lateral border of the package substrate.
As the further improvement of an embodiment of the present invention, the multichip packaging structure further includes being located at the encapsulation
The plastic packaging layer of side of the substrate far from the base lower surface, the plastic packaging layer coat simultaneously second cofferdam be exposed to it is outer
Surface area, the filter chip and the functional chip, and the plastic packaging layer fills the functional chip and the chamber
Gap between room.
One of for achieving the above object, an embodiment of the present invention provides a kind of multi-chip package knot with chamber
The production method of structure, comprising steps of
S1: providing package substrate, has the upper surface of base plate and base lower surface being oppositely arranged；
S2: in forming chamber on the package substrate；
S3: cofferdam is formed far from the region of the chamber in the upper surface of base plate；
S4: providing functional chip and filter chip, and the functional chip has the first upper surface being oppositely arranged and the
A lower surface, the filter chip has the second upper surface and the second lower surface being oppositely arranged, and the functional chip has
There are several first electrodes, the filter chip has several second electrodes；
S5: the functional chip and the filter chip are loaded to the package substrate, the functional chip is located at
In the chamber, the second lower surface and the upper surface of base plate of the filter chip are arranged face-to-face, and the cofferdam with
Second lower surface and the upper surface of base plate cooperate and enclose and set to form cavity；
S6: several interconnection structures that several first electrodes and several second electrodes are connected are formed；
S7: external pin is formed at the interconnection structure.
As the further improvement of an embodiment of the present invention, step S2, S3 is specifically included:
In formation chamber and several through-holes on the package substrate；
Photaesthesia insulating film is laid in the upper surface of base plate；
Exposure and imaging forms cofferdam, and the cofferdam includes the first cofferdam being located on the inside of the through-hole and is located at described logical
The second cofferdam on the outside of hole, and the cofferdam exposes the chamber and the through-hole；
Step S6, S7 is specifically included:
Plastic packaging layer is formed far from the side of the base lower surface in the package substrate, the plastic packaging layer coats institute simultaneously
It states the second cofferdam and is exposed to outer surface area, the filter chip and the functional chip, and the plastic packaging layer is filled
Gap between the functional chip and the chamber, the second electrode are directed at the through-hole；
The first insulating layer is formed in the base lower surface；
Inside hole inside through-hole, on the first insulating layer and lower section of the first insulating layer forms metal layer, the gold
Belong to layer and the first electrode and the second electrode is connected；
Second insulating layer is formed in the lower section of first insulating layer and the metal layer；
It is formed in the lower section of the second insulating layer and the metal layer is connected by the hole in the second insulating layer
Lower rewiring layer；
It is formed and coats the second insulating layer and the lower third insulating layer for rerouting layer, the third insulating layer exposing
The lower rewiring layer out；
Ball grid array is formed in being exposed to outer lower rewiring layer.
Compared with prior art, the beneficial effects of the present invention are: an embodiment of the present invention is formed by the way that cofferdam is arranged
Cavity, it is possible to prevente effectively from external substance enters cavity in encapsulating structure manufacturing process or in encapsulating structure use process
Normal use that is internal and influencing filter chip, so that the overall performance of multichip packaging structure is improved, in addition, the present invention one
Embodiment utilizes encapsulation technology that in same package substrate, the height collection of multi-chip is may be implemented in two different chip packages
At improving the utilization rate of package substrate, and then realize the miniaturization of multichip packaging structure.
Detailed description of the invention
Fig. 1 is an exemplary RF front-end module of the invention；
Fig. 2 is another exemplary RF front-end module of the present invention；
Fig. 3 is the cross-sectional view of the multichip packaging structure of an embodiment of the present invention；
Fig. 4 is the schematic diagram in (respective filter chip area) cofferdam on the package substrate of an embodiment of the present invention；
The step of Fig. 5 is the production method of the multichip packaging structure of an embodiment of the present invention figure；
Fig. 6 a to Fig. 6 z is the flow chart of the production method of the multichip packaging structure of an embodiment of the present invention.
Specific embodiment
Below with reference to specific embodiment shown in the drawings, the present invention will be described in detail.But these embodiments are simultaneously
The present invention is not limited, structure that those skilled in the art are made according to these embodiments, method or functionally
Transformation is included within the scope of protection of the present invention.
In each diagram of the application, for the ease of illustration, structure or partial certain sizes can be relative to other knots
Structure or part are exaggerated, and therefore, are only used for the basic structure of the theme of diagram the application.
In addition, the term of the representation space relative position used herein such as "upper", " top ", "lower", " lower section " is
A unit as shown in the drawings or feature are described for the purpose convenient for explanation relative to another unit or feature
Relationship.The term of relative space position can be intended to include equipment in use or work other than orientation as shown in the figure not
Same orientation.For example, being described as being located at other units or feature " below " or " under " if the equipment in figure overturn
Unit will be located at other units or feature " top ".Therefore, exemplary term " lower section " can include above and below both
Orientation.Equipment can otherwise be directed (be rotated by 90 ° or other directions), and be interpreted accordingly it is used herein with it is empty
Between relevant description language.
Join Fig. 1 and Fig. 2, an embodiment of the present invention provides a kind of general RF front-end module, and RF front-end module can
For in the mobile devices such as mobile phone, computer either other electronic equipments.
In conjunction with Fig. 1, in one example, RF front-end module includes (the Power Amplifier of power amplifier module 200
Module, PAM), power amplifier module 200 includes the first amplifier unit 201 being successively electrically connected, the first RF switch list
Member 202 and the first RF filter cell 203, the first amplifier unit 201 are multi-mode-wide bandwidth Power Amplifier Unit.
In practical operation, the first amplifier unit 201 is used to receive the modulated signal of other component output, puts through overpower
Greatly after the modulation, amplification of device module 200 and filtering operation, exported by filter cell 203.
In conjunction with Fig. 2, in another example, RF front-end module includes receiving 300 (Receive of diversity module
Diversity Module, RDM), receiving diversity module 300 includes the low noise amplification multiplexer 301 being successively electrically connected
(LNA Multiplexer Module, LMM), the 2nd RF filter cell 302 and RF duplexer unit 303, wherein low noise
It includes the second amplifier unit 3011 and the 2nd RF switch unit 3012 being electrically connected, the second amplification that sound, which amplifies multiplexer 301,
Device unit 3011 is multi-mode-wide bandwidth low-noise amplifier unit, and the both ends of the 2nd RF switch unit 3012 are separately connected
Second amplifier unit 3011 and the 2nd RF filter cell 302.
In practical operation, signal divides by notch diplexer 304 to be believed here with high frequency for high-frequency signal and low frequency signal
For number, high-frequency signal enters RF duplexer unit 303, then successively passes through the 2nd RF filter cell 302 and low noise
It is exported after amplifying the filtering, modulation, amplifying operation of multiplexer 301 by the second amplifier unit 3011.
It should be understood that the electrical property between each units such as above-mentioned RF switch unit, filter cell, amplifier unit connects
Connecing can be realized by packaging technology, i.e., RF switch chip, amplifier chip, filter chip etc. are packaged together and realize
Various functions.
Present embodiment is said by taking RF switch chip, amplifier chip, the encapsulating structure of filter chip, technique as an example
It is bright.
Join Fig. 3, is the cross-sectional view of the multichip packaging structure 100 with chamber of an embodiment of the present invention.
Multichip packaging structure 100 includes package substrate 10, functional chip 20, filter chip 30, cofferdam 40 and several
Interconnection structure 50.
Package substrate 10 has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged, the side tool of package substrate 10
There are several external pins 121, and package substrate 10 has chamber 101.
Here, package substrate 10 is the loading plate for carrying chip, and package substrate 10 can be printing made of organic resin
Circuit board is also possible to glass substrate or ceramic substrate etc..
Chamber 101 can be the through hole through package substrate 10, and but not limited to this.
External pin 121 can be ball grid array (Ball Grid Array, BGA), pad etc., multi-chip package knot
Structure 100 can be electrically connected by external pin 121 with realizations such as other chips or substrates, and here, external pin 121 is with ball bar
For array 121, external pin 121 protrudes out the lower surface of multichip packaging structure 100.
In addition, but not limited to this, outside here by taking several external pins 121 are located at the side of base lower surface 12 as an example
Portion's pin 121 may be alternatively located at other regions.
Functional chip 20 is set in chamber 101, and functional chip 20 has the first upper surface 21 and first being oppositely arranged
Lower surface 22, and functional chip 20 has several first electrodes 221.
Here, by taking first electrode 221 is located at the first lower surface 22 as an example, but not limited to this.
First electrode 221 protrudes out the first lower surface 22 towards the direction far from the first upper surface 21, and but not limited to this.
Functional chip 20 is amplifier chip or RF switch chip, and but not limited to this.
Filter chip 30 is set to the top of package substrate 10, and filter chip 30 has table on second be oppositely arranged
Face 31 and the second lower surface 32, the second lower surface 32 are arranged face-to-face with upper surface of base plate 11, and if filter chip 30 have
Dry second electrode 321.
Here, by taking second electrode 321 is located at the second lower surface 32 as an example, but not limited to this.
Second electrode 321 protrudes out the second lower surface 32 towards the direction far from the second upper surface 31, and but not limited to this.
Filter chip 30 can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW) or volume
Acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, the active region on 30 surface of filter chip
Domain (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs are filtering
The lower section of device chip 30 forms a cavity to protect the active region.
Several interconnection structures 50 lead to several first electrodes 221, several second electrodes 321 and several external pins for being connected
121。
Here, " several interconnection structures 50 lead to several first electrodes 221, several second electrodes 321 and several outer for being connected
Portion's pin 121 " refers to be electrically connected between first electrode 221 and second electrode 321, first electrode 221 and external pin 121 it
Between be electrically connected, and be electrically connected between second electrode 321 and external pin 121, i.e. realization filter chip 30 and function core
The interconnection of piece 20 and the interconnection of filter chip 30, functional chip 20 and other external structures.
Cofferdam 40 and the second lower surface 32 and upper surface of base plate 11 cooperate and enclose to set to form cavity S, the corresponding filtering of cavity S
The active region on 30 surface of device chip.
Present embodiment by setting cofferdam 40 formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or
It is that external substance enters the normal use for inside cavity S and influencing filter chip 30 in encapsulating structure use process, thus
Improve the overall performance of multichip packaging structure 100.
In addition, present embodiment utilizes encapsulation technology by two different chips (filter chip 30 and functional chip 20)
It is packaged in same package substrate 10, the highly integrated of multi-chip may be implemented, improves the utilization rate of package substrate 10, and then realize
The miniaturization of multichip packaging structure 100.
It should be noted that the multichip packaging structure 100 of present embodiment is with a filter chip 30 and a function
Energy chip 20 is loaded into for package substrate 10, it is possible to understand that, in practice, referring to Figure 1 and Figure 2, it may include more
A filter chip 30 and multiple functional chips 20, for example, around filter chip 30 (including all around three-dimensional side up and down
To) multiple functional chips 20 etc. can be electrically connected with.
In addition, the filter chip 30 of present embodiment and functional chip 20 mutually stagger distribution.
Specifically, functional chip 20 is located in the chamber 101 of package substrate 10, and the first upper surface 21 of functional chip 20
It is flushed with upper surface of base plate 11, and the first lower surface 22 flushes 22 with base lower surface, i.e., chamber 101 is through hole, function at this time
Energy chip 20 is entirely embedded in chamber 101, and the thickness of functional chip 20 is equal with the thickness of package substrate 10, but not with this
It is limited.
Filter chip 30 is located at the top of package substrate 10, and filter chip 30 is arranged far from chamber 101, filter
There is upper and lower drop between chip 30 and functional chip 20.
At this point, the embedded setting of functional chip 20, so that multichip packaging structure 100 is more frivolous, moreover, functional chip 20
The first upper surface 21 top have idle space, can in the top of the first upper surface 21 be arranged an at least passive device, quilt
Dynamic element is, for example, resistance, capacitor, inductance, Tao Zhen, crystal oscillator, transformer etc., to improve the sky that leaves unused above the first upper surface 21
Between utilization rate, and can further improve the integrated level of multichip packaging structure 100.
In the present embodiment, package substrate 10 has several through-holes 13, and cofferdam 40 includes positioned at the of the inside of through-hole 13
One cofferdam 41 and the second cofferdam 42 on the outside of through-hole 13.
Here, it since cofferdam 40 has certain height, when the lower surface area when cofferdam 40 is too small, may can not prop up
The cofferdam 40 of the height is supportted, collapsing phenomenon occurs so as to cause cofferdam 40, the cofferdam 40 of present embodiment includes being located at several lead to
The first cofferdam 41 and the second cofferdam 42 on the outside of several through-holes 13, cofferdam 40 of 13 inside of hole have sufficiently large following table
Face improves the stability in entire cofferdam 40；In addition, 40 upper surface of cofferdam can be with the 30 lower surface area cavity S of filter chip
Overseas 30 lower surface whole region of filter chip combines, and further increases the forming stability of cavity S.
In conjunction with Fig. 4, several through-holes 13 are in array distribution in upper surface of base plate 11, and have interval between adjacent through-holes 13,
There is a space, the first cofferdam 41 is located in the space, i.e. the first cofferdam 41 is located at several through-holes 13 between two column through-holes 13
Inside, the second cofferdam 42 are located at outside the space, i.e. the second cofferdam 42 is located at the outside of several through-holes 13.
That is, several through-holes 13, which enclose, sets the first cofferdam 41 of the Internal periphery to be formed connection, several through-holes 13, which enclose, to be set to be formed
Outer profile connect the second cofferdam 42.
It should be noted that can be independent from each other between the first cofferdam 41 and the second cofferdam 42, such as the first cofferdam
41 be the first cyclic structure, and the first cyclic structure connects the inside of several through-holes 13, and the second cofferdam 42 is the second cyclic structure, the
Bicyclic structures connect the outside of several through-holes 13.
Certainly, be also possible between the first cofferdam 41 and the second cofferdam 42 it is interconnected, at this point, the first cofferdam 41 and
Interconnection is realized by third cofferdam 43 between two cofferdam 42, third cofferdam 43 is positioned at adjacent through-hole 13 between or other areas
Domain, that is to say, that cofferdam 40 at this time is covered with cavity S periphery, and cofferdam 40 is covered with 13 periphery of through-hole.
In the present embodiment, the upper surface in the second lower surface 32 the first cofferdam 41 of covering of filter chip 30, and the
Two lower surfaces 32 are Chong Die with the upper surface portion in the second cofferdam 42, and upper surface of base plate 11 covers the lower surface and the in the first cofferdam 41
The lower surface in two cofferdam 42.
Second cofferdam 42 extends up to the lateral border and package substrate in the second cofferdam 42 towards the direction far from the first cofferdam 41
10 lateral border flushes.
It should be noted that " lateral border of package substrate 10 " can refer to the left side lateral margin of package substrate 10 in conjunction with Fig. 3
And package substrate 10 leans on the lateral margin (i.e. the left side lateral margin of chamber 101) of 101 side of abluminal compartment, alternatively, " package substrate 10 it is outer
Lateral margin " can refer to lateral margin (i.e. 101 right side of Fig. 3 middle chamber of 10 rightmost side of left side lateral margin and package substrate of package substrate 10
The right side lateral margin of the package substrate 10 of side), at this point, other than the region of chamber 101, cavity S and through-hole 13 covering, table on substrate
Other regions in face 11 are laid with cofferdam 40.
Certainly, since package substrate 10 is quadrilateral structure, lateral border further include package substrate 10 front side lateral margin and after
Side lateral margin, the second cofferdam 42 can also extend to front side lateral margin and rear side lateral margin together, and but not limited to this, and package substrate 10 can also
To be the structure of other shapes.
Cofferdam 40 is made of the insulating materials of photaesthesia, and but not limited to this.
In the present embodiment, multichip packaging structure 100 further include coat simultaneously the second cofferdam 42 be exposed to it is outer upper
The plastic packaging layer 60 of surface region, filter chip 30 and functional chip 20, plastic packaging layer 60 fill functional chip 20 and chamber 101 it
Between gap, and plastic packaging layer 60 is located at side of the package substrate 10 far from base lower surface 12.
That is, plastic packaging layer 60 is located at the top in the second cofferdam 42 at this time, plastic packaging layer 60 coat filter chip 30 and
All open areas around functional chip 20.
Plastic packaging layer 60 can be EMC (Epoxy Molding Compound) plastic packaging layer, enclose since present embodiment utilizes
Weir 40 can stop external substance to enter cavity S, without considering whether plastic packaging layer 60 can influence in cavity S because of problem of materials
Protection zone, therefore, the range of choice of 60 material of plastic packaging layer expands significantly, and then can evade the choosing of specific capsulation material
It selects, substantially widen plastic packaging making technology window and effectively reduce cost.
In the present embodiment, the side of base lower surface 12 have several external pins 121, package substrate 10 it is several
Through-hole 13 passes through for several interconnection structures 50.
It should be noted that " several through-holes 13 of package substrate 10 pass through for several interconnection structures 50 " refers to interconnection structure
50 at least partly structure passes through corresponding through-hole 13, to realize second electrode 321 and first electrode 221, external pin 121
Interconnection.
Here, several 13 respective filter chip 30 of through-hole settings, the second electrode 321 of filter chip 30 are located at second
Lower surface 32, the corresponding through-hole 13 of second electrode 321 are arranged, and second electrode 321, first is connected by through-hole 13 in interconnection structure 50
Electrode 221 and external pin 121.
Specifically, first electrode 221 is located at the first lower surface 22, interconnection structure 50 includes metal layer 51, and metal layer 51 fills
It fills out 13 interior zone of through-hole and extends toward 12 direction of base lower surface and first electrode 221 is connected.
That is, the upper surface of metal layer 51 connects second electrode 321, then metal layer 51 fills up through-hole 13 and direction
12 direction of base lower surface extends, and since base lower surface 12 exposes first electrode 221 at this time, metal layer 51 may extend to chamber
101 region of room and first electrode 221 is connected.
Here, the upper surface of metal layer 51 and the lower surface of second electrode 321 are mutually matched and are electrically connected.
That is, the profile of 13 upper opening of outer profile with through-hole of second electrode 321 is mutually matched at this time, metal layer
51 connection second electrodes 321 are simultaneously filled up after through-hole 13, and 40 essence of cofferdam is to surround the setting of metal layer 51.
Here, directly realize that second electrode 321 and the electrical property of external pin 121, first electrode 221 connect by metal layer 51
It connects, it is advantageous that: the structure of interconnection structure 50 is simple, and the difficulty of packaging technology can be effectively reduced, improve efficiency.
Multichip packaging structure 100 further includes the first insulating layer being set between base lower surface 12 and metal layer 51
70, it coats the second insulating layer 71 of the first insulating layer 70 and metal layer 51, metal is connected by the hole in second insulating layer 71
Layer 51 and the lower rewiring layer 52 extended toward the lower surface direction of second insulating layer 71 and cladding second insulating layer 71 and lower heavy
The third insulating layer 72 of wiring layer 52, the connection of external pin 121 is lower to reroute layer 52, and the exposure external pin of third insulating layer 72
121。
Here, metal layer 51 and lower rewiring layer 52 are layers of copper.
That is, present embodiment realizes the 221, second electricity of first electrode using succinct rewiring (RDL) scheme
Electric connection between pole 321 and external pin 121, process stabilizing and high reliablity.
The metal line materials of rewiring are copper (i.e. metal layer 51 and lower rewiring layer 52 are layers of copper), reroute copper and core
Enhancing rewiring copper can be set between plate electrode (including first electrode 221 and second electrode 321) and chip electrode is mutually attached
The metal or alloy film puted forth effort, the metal or alloy material can be nickel, titanium, nickel chromium triangle, titanium tungsten etc..
The first insulating layer 70, second insulating layer 71 are folded between package substrate 10, metal layer 51 and lower rewiring layer 52
And third insulating layer 72, to realize the electrical isolation between all parts.
It should be understood that the metal layer in rewiring scheme is not with above-mentioned two layers (metal layer 51 and lower rewiring layer 52)
Be limited, can according to the actual situation depending on.
An embodiment of the present invention also provides a kind of production method of multichip packaging structure 100, in conjunction with aforementioned multi-chip
The explanation and Fig. 5, Fig. 6 a to Fig. 6 z of encapsulating structure 100, production method comprising steps of
S1: ginseng Fig. 6 a provides package substrate 10, has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged；
S2: ginseng Fig. 6 b, in formation chamber 101 on package substrate 10；
S3: ginseng Fig. 6 c and Fig. 6 d, cofferdam 40 is formed far from the region of chamber S in upper surface of base plate 11；
Step S2, S3 is specific as follows:
Join Fig. 6 b, in formation chamber 101 and several through-holes 13 on package substrate 10；
Join Fig. 6 c, lays photaesthesia insulating film 80 in upper surface of base plate 11；
Join Fig. 6 d, exposure and imaging forms cofferdam 40, and cofferdam 40 includes positioned at the first cofferdam 41 and position of 13 inside of through-hole
In second cofferdam 42 in 13 outside of through-hole, and cofferdam 40 exposes chamber 101 and through-hole 13.
It should be noted that cofferdam 40 may include the third cofferdam 43 for connecting the first cofferdam 41 and the second cofferdam 42,
That is removing the other surfaces region outside the region for corresponding to cavity S, through-hole 13 and chamber 101 in upper surface of base plate 11 at this time
It is respectively formed cofferdam 40.
In addition, formed since independent package substrate 10 can be divided by the large substrates of wafer scale, it, can when forming cofferdam 40
With the multiple cofferdam 40 of straight forming on large substrates, the segmentation of large substrates is then carried out again and obtains the list with single cofferdam 40
A package substrate 10, in this way, being greatly improved packaging efficiency, certainly, cofferdam 40 is also plastic on filter chip 30.
In addition, being further comprised the steps of: after step S3
Join Fig. 6 e, an interim jointing plate 90 is provided；
Join Fig. 6 f, base lower surface 12 is bonded with interim jointing plate 90.
S4: ginseng Fig. 6 g and Fig. 6 h provide functional chip 20 and filter chip 30, and functional chip 20, which has, to be oppositely arranged
First upper surface 21 and the first lower surface 22, filter chip 30 have the second upper surface 31 and the second lower surface being oppositely arranged
32, and functional chip 20 has several first electrodes 221, first electrode 221 is located at the first lower surface 22, and filter core 30 has
Several second electrodes 321, second electrode 321 are located at the second lower surface 32；
S5: ginseng Fig. 6 i loads functional chip 20 and filter chip 30 to package substrate 10, functional chip 20 is located at chamber
In room 101, the second lower surface 32 of filter chip 30 is arranged face-to-face with upper surface of base plate 11, and cofferdam 40 and the second following table
Face 32 and upper surface of base plate 11 cooperate and enclose and set to form cavity S；
S6: ginseng Fig. 6 j to Fig. 6 w forms several mutual connections that several first electrodes 221 and several second electrodes 321 are connected
Structure 50；
S7: ginseng Fig. 6 x to Fig. 6 z forms external pin 121 at interconnection structure 50.
Step S6, S7 is specific as follows:
Join Fig. 6 j, forms plastic packaging layer 60 far from the side of base lower surface 12 in package substrate 10, plastic packaging layer 60 wraps simultaneously
It covers the second cofferdam 42 and is exposed to outer surface area, filter chip 30 and functional chip 20, and plastic packaging layer 60 fills function
Gap between chip 20 and chamber 101, second electrode 321 are directed at through-hole 13；
Join Fig. 6 k, removes interim jointing plate 90；
Join Fig. 6 l, forms the first insulating layer 70 in base lower surface 12；
Join Fig. 6 m to Fig. 6 q, inside the hole inside through-hole 13, on the first insulating layer 70 and under the first insulating layer 70
It is rectangular at metal layer 51, the first electrode 221 and the second electrode 321 is connected in metal layer 51；
It is specific as follows:
Join Fig. 6 m, forms several first holes 701 in 70 exposure and imaging of the first insulating layer, the first hole 701 exposes
Through-hole 13, second electrode 321 and first electrode 221；
Join Fig. 6 n, forms the first photoresist layer 81 in the lower section of the first insulating layer 70；
Join Fig. 6 o, forms several first apertures 811, the first aperture 811 exposure in 81 exposure and imaging of the first photoresist layer
First hole 701 and the first insulating layer 70 out；
Join Fig. 6 p, inside through-hole 13, the inside of the first hole 701 and is exposed on the first outer insulating layer 70 and forms metal
Layer 51；
Join Fig. 6 q, removes the first photoresist layer 81.
Join Fig. 6 r, forms second insulating layer 71 in the lower section of the first insulating layer 70 and metal layer 51；
Join Fig. 6 s to Fig. 6 w, is formed in the lower section of second insulating layer 71 by described in the hole conducting in second insulating layer 71
The lower rewiring layer 52 of metal layer 51；
It is specific as follows:
Join Fig. 6 s, forms several second holes 711 in 71 exposure and imaging of second insulating layer, the second hole 711 exposes
Metal layer 51；
Join Fig. 6 t, forms the second photoresist layer 82 in the lower section of second insulating layer 71；
Join Fig. 6 u, forms several second apertures 821, the second aperture 821 exposure in 82 exposure and imaging of the second photoresist layer
Second hole 711 and second insulating layer 71 out；
Ginseng Fig. 6 v in 711 inside of the second hole and is exposed to the lower rewiring layer 52 of formation in outer second insulating layer 71；
Join Fig. 6 w, removes the second photoresist layer 82.
Join Fig. 6 x and Fig. 6 y, forms cladding second insulating layer 71 and the lower third insulating layer 72 for rerouting layer 52, third is exhausted
Edge layer 72 exposes lower rewiring layer 52；
It is specific as follows:
Join Fig. 6 x, forms third insulating layer 72 in second insulating layer 71 and the lower lower section for rerouting layer 52；
Join Fig. 6 y, forms several third holes 721 in 72 exposure and imaging of third insulating layer, third hole 721 exposes
Lower rewiring layer 52.
Join Fig. 6 z, forms ball grid array 121 in being exposed to outer lower rewiring layer 52, i.e., in several third holes 721
Form ball grid array 121.
Other explanations of the production method of the multichip packaging structure 100 of present embodiment can be sealed with reference to above-mentioned multi-chip
The explanation of assembling structure 100, details are not described herein.
Cofferdam 40 of the invention is located at the inside and outside of through-hole 13, and the lateral border in the second cofferdam 42 and package substrate 10
Lateral border flush, in other embodiments, cofferdam 40 may be alternatively located at the inside of through-hole 13, alternatively, the second cofferdam 42 is outer
Lateral margin is flushed with the lateral border of filter chip 30, or, the lateral border in the second cofferdam 42 is located at the outer of filter chip 30
Between the lateral border of lateral margin and package substrate 10 etc..
To sum up, present embodiment forms cavity S by setting cofferdam 40, it is possible to prevente effectively from encapsulating structure manufacturing process
In or external substance enters the normal use for inside cavity S and influencing filter chip 30 in encapsulating structure use process,
To improve the overall performance of multichip packaging structure 100.
In addition, present embodiment utilizes encapsulation technology by two different chips (filter chip 30 and functional chip 20)
It is packaged in same package substrate 10, the highly integrated of multi-chip may be implemented, improves the utilization rate of package substrate 10, and then realize
The miniaturization of multichip packaging structure 100.
It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one
A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say
As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book
With the other embodiments of understanding.
The series of detailed descriptions listed above only for feasible embodiment of the invention specifically
Protection scope bright, that they are not intended to limit the invention, it is all without departing from equivalent implementations made by technical spirit of the present invention
Or change should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of multichip packaging structure with chamber characterized by comprising
Package substrate, has the upper surface of base plate and base lower surface being oppositely arranged, and the side of the package substrate has several
External pin, and the package substrate has chamber；
Functional chip is set in the chamber, and the functional chip has the first upper surface being oppositely arranged and the first following table
Face, and the functional chip has several first electrodes；
Filter chip, is set to the top of the package substrate, and the filter chip has table on second be oppositely arranged
Face and the second lower surface, second lower surface is arranged face-to-face with the upper surface of base plate, and the filter chip has
Several second electrodes；
Cofferdam cooperates with second lower surface and the upper surface of base plate and encloses to set to form cavity；
Several interconnection structures, for several first electrodes, several second electrodes and several external pins to be connected.
2. multichip packaging structure according to claim 1, which is characterized in that if the side of the base lower surface has
Dry external pin, the package substrate have several through-holes, and the second electrode is located at second lower surface, the mutual connection
The second electrode, the first electrode and the external pin is connected by the through-hole in structure.
3. multichip packaging structure according to claim 2, which is characterized in that the first electrode is located under described first
Surface, the interconnection structure include metal layer, and the metal layer fills the through-hole interior zone and the past base lower surface
Direction extends and the first electrode is connected.
4. multichip packaging structure according to claim 3, which is characterized in that the multichip packaging structure further includes setting
The first insulating layer, cladding first insulating layer and the metal layer being placed between the base lower surface and the metal layer
Second insulating layer, the metal layer and the following table toward the second insulating layer is connected by the hole in the second insulating layer
The lower rewiring layer and the cladding second insulating layer and the lower third insulating layer for rerouting layer that face direction extends, it is described
External pin connects the lower rewiring layer, and external pin described in the third insulating layer exposing.
5. multichip packaging structure according to claim 1, which is characterized in that the cofferdam includes being located in the through-hole
First cofferdam of side and the second cofferdam on the outside of the through-hole.
6. multichip packaging structure according to claim 5, which is characterized in that several through-holes, which enclose, sets the Internal periphery to be formed company
Connect first cofferdam, several through-holes, which enclose, to be set the outer profile to be formed and connect second cofferdam, first cofferdam and described the
Two cofferdam are interconnected.
7. multichip packaging structure according to claim 5, which is characterized in that second cofferdam is towards far from described first
The lateral border that the direction in cofferdam extends up to second cofferdam is flushed with the lateral border of the package substrate.
8. multichip packaging structure according to claim 1, which is characterized in that the multichip packaging structure further includes position
Plastic packaging layer in side of the package substrate far from the base lower surface, the plastic packaging layer coat second cofferdam simultaneously
It is exposed to outer surface area, the filter chip and the functional chip, and the plastic packaging layer fills the function core
Gap between piece and the chamber.
9. a kind of production method of the multichip packaging structure with chamber, which is characterized in that comprising steps of
S1: providing package substrate, has the upper surface of base plate and base lower surface being oppositely arranged；
S2: in forming chamber on the package substrate；
S3: cofferdam is formed far from the region of the chamber in the upper surface of base plate；
S4: providing functional chip and filter chip, and the functional chip has under the first upper surface and first being oppositely arranged
Surface, the filter chip have the second upper surface and the second lower surface that are oppositely arranged, and if the functional chip have
Dry first electrode, the filter chip have several second electrodes；
S5: the functional chip and the filter chip are loaded to the package substrate, the functional chip is located at described
In chamber, the second lower surface and the upper surface of base plate of the filter chip are arranged face-to-face, and the cofferdam with it is described
Second lower surface and the upper surface of base plate cooperate and enclose and set to form cavity；
S6: several interconnection structures that several first electrodes and several second electrodes are connected are formed；
S7: external pin is formed at the interconnection structure.
10. the production method of multichip packaging structure according to claim 9, which is characterized in that step S2, S3 is specifically wrapped
It includes:
In formation chamber and several through-holes on the package substrate；
Photaesthesia insulating film is laid in the upper surface of base plate；
Exposure and imaging forms cofferdam, and the cofferdam includes being located at the first cofferdam on the inside of the through-hole and being located at outside the through-hole
Second cofferdam of side, and the cofferdam exposes the chamber and the through-hole；
Step S6, S7 is specifically included:
Plastic packaging layer is formed far from the side of the base lower surface in the package substrate, the plastic packaging layer coats described the simultaneously
Two cofferdam are exposed to outer surface area, the filter chip and the functional chip, and described in plastic packaging layer filling
Gap between functional chip and the chamber, the second electrode are directed at the through-hole；
The first insulating layer is formed in the base lower surface；
Inside hole inside through-hole, on the first insulating layer and lower section of the first insulating layer forms metal layer, the metal layer
The first electrode and the second electrode is connected；
Second insulating layer is formed in the lower section of first insulating layer and the metal layer；
It is formed in the lower section of the second insulating layer and the lower heavy of the metal layer is connected by the hole in the second insulating layer
Wiring layer；
The third insulating layer for coating the second insulating layer and the lower rewiring layer is formed, the third insulating layer exposing goes out institute
State lower rewiring layer；
Ball grid array is formed in being exposed to outer lower rewiring layer.
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| CN201810911145.5A CN109087912A (en) | 2018-08-10 | 2018-08-10 | Multichip packaging structure and preparation method thereof with chamber |
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| JP2005311230A (en) * | 2004-04-26 | 2005-11-04 | Murata Mfg Co Ltd | Circuit module and circuit device using the same |
| US20110128713A1 (en) * | 2009-11-30 | 2011-06-02 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
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Effective date of registration: 20200616 Address after: 313200 No. 926 Changhong East Street, Fuxi Street, Deqing County, Huzhou City, Zhejiang Province (Mogan Mountain National High-tech Zone) Applicant after: Zhejiang Rongcheng Semiconductor Co., Ltd Address before: 215123 Jiangsu city Suzhou Industrial Park 99 Jinji Hu Road 99 Suzhou Nancheng NW-05 building 301 Applicant before: Fu Wei |