CN109075139B - 集成电路封装以及其制造方法 - Google Patents
集成电路封装以及其制造方法 Download PDFInfo
- Publication number
- CN109075139B CN109075139B CN201780029132.9A CN201780029132A CN109075139B CN 109075139 B CN109075139 B CN 109075139B CN 201780029132 A CN201780029132 A CN 201780029132A CN 109075139 B CN109075139 B CN 109075139B
- Authority
- CN
- China
- Prior art keywords
- package
- die
- integrated circuit
- opening
- die member
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000005520 cutting process Methods 0.000 claims abstract description 57
- 238000000034 method Methods 0.000 claims description 37
- 238000002485 combustion reaction Methods 0.000 claims description 13
- 230000000977 initiatory effect Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
- B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
- B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
- B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
- B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48105—Connecting bonding areas at different heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48105—Connecting bonding areas at different heights
- H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/48177—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
一种通过以下步骤来制作集成电路封装的方法:a)提供连接到模具中的相应电接触构件(8a、8b)的多个管芯构件(4a、4b);b)提供与第一管芯构件(4a)的第一上表面(6a)的至少部分接触的模具插入件;c)将多个管芯构件(4a、4b)和相应电接触构件(8a、8b)包封到封装收集主体(3)中;以及d)沿着第一切割线(S1)将封装收集主体(3)切成至少两个单独的集成电路封装(3a、3b),所述第一切割线延伸穿过封装收集主体(3)并且分开多个管芯构件(4a、4b)。如在步骤b)中提供的模具插入件延伸跨过第一切割线(S1)的部分。
Description
技术领域
本发明涉及一种制造集成电路封装的方法,具体地,涉及一种制造方形扁平无引脚(QFN)集成电路封装、连接盘网格阵列(LGA)集成电路封装或者球栅阵列(BGA)集成电路封装的方法。在另一方面,本发明涉及一种集成电路封装。
背景技术
国际申请WO 03/028086公开了一种用于利用密封剂来包封芯片的方法,其中该芯片的表面的一部分必须保持没有密封剂。该方法包括以下步骤:将芯片固定在引脚框架、衬底、膜或可以具有适当导体结构的其他载体上,以及将载体和芯片放在两部分或多部分模具的一部分中。该方法的另一步骤随后包括将材料置于模具的一部分或芯片表面的一部分上,使得在模具闭合之后,该材料被夹紧在芯片的所述部分与模具之间。该方法还包括以下步骤:引入密封剂并且创造密封剂在模具中至少部分地固化的条件。在实施方式中,材料可以作为预先模制件引入在顶部模具部分与底部模具部分之间的腔体中,直到在操作期间该模制件压靠待包封的芯片的至少一部分的程度,以便芯片的表面的期望部分保持暴露。
美国专利公布US2004/159961公开了一种半导体芯片,该半导体芯片置于载体上,该载体具有用于半导体芯片的保护覆盖物,以便用作指纹传感器。保护覆盖物的顶侧具有覆盖半导体芯片、载体和接合线的部分的第一部分。第二部分旨在保持没有注封/包封化合物,以允许接近传感器区域。第二部分由边缘界定,并且优选地具有允许容易将指尖置于半导体芯片的敏感区域上的形状。
美国专利公布US2009/079091涉及一种使用具有接近开口的插入器阵列的集成电路封装系统,其中制造对称布置的IC。通过从中心切穿接近开口而将基础封装从基础封装基板片和插入器阵列单切出来。
发明内容
本发明试图提供一种制造诸如方形扁平无引脚(QFN)集成电路封装、连接盘网格阵列(LGA)集成电路封装或者球栅阵列(BGA)集成电路封装等集成电路(IC)封装的改进方法,从而允许有效地分批分离阵列布置中的多个电路封装,并且提供对每个封装的封装内部构件的改进的暴露和接近。
根据本发明,提供一种前文中定义的类型的方法,其包括以下步骤:a)提供连接到模具中的相应电接触构件的多个管芯构件(die member),以及b)提供与第一管芯构件的第一上表面的至少部分接触的模具插入件。该方法随后继续行进到步骤c)将多个芯片构件和相应电接触构件包封在封装收集主体中,以及d)沿着第一切割线将封装收集主体切成至少两个单独的集成电路封装,该第一切割线延伸穿过封装收集主体并且将多个管芯构件分开,其中在步骤b)中提供的模具插入件延伸跨过或跨越第一切割线的部分。
根据本发明,如在该方法中使用的模具插入件允许在包封多个管芯构件和连接到此的相应电触点构件时在封装收集主体中形成开口或凹部,其中开口或凹部至少部分地暴露第一管芯构件。包封的过程可以被设想为包覆模制过程,其中模具插入件限定被模制到封装收集主体中的凹部的形状和位置。模具插入件可以由膜叠加或覆盖,以便在需要时允许由膜辅助的模制。由于模具插入件跨越第一切割线,因此沿着第一切割线将封装收集主体切成至少两个单独的集成电路封装也将开口或凹部切成或剖成两个单独的管芯开口或凹部部分,使得每个分开的集成电路封装具有这样的管芯开口。每个管芯开口可以被视作沿着暴露管芯构件的相关联集成封装的边缘的切口。
更具体地,在沿着第一切割线完成切割后,所形成的每个管芯开口包括沿着切割表面的侧部开口,该侧部开口变成诸如QFN、LGA或BGA封装等相应分开的集成电路封装的侧表面的部分。分开的集成电路主体中的侧部开口可以被视作封装收集主体中的开口或凹部在沿着第一切割线切开之前的横截面。
根据上述内容,本发明的方法提供一种制造集成电路封装的有效方式,该集成电路封装包括管芯开口或边缘切口,该边缘切口包括从中暴露管芯构件的至少两个开口或表面。这提供很多优点,诸如,允许集成电路封装具有传感器和/或致动器,这些传感器和/或致动器从集成电路封装的不同侧部进行使用和/或部署。本发明的方法可以用于制造QFN、LGA和BGA封装。
附图说明
下文将基于多个示例性实施方式参考附图来更详细地论述本发明,在附图中:
图1示出根据本发明的集成电路封装的阵列的实施方式的三维视图;以及
图2示出根据本发明的单个集成电路封装的实施方式的三维视图。
具体实施方式
集成电路封装或简称IC封装正在用于越来越多的应用中,其中IC封装不仅需要提供一般的电处理电路,而且甚至可以包括例如用于监测诸如温度和/或压力的物理性质的一个或多个传感器。在其他应用中,IC封装甚至可以包括有源元件,诸如点火器或致动器构件。
鉴于越来越多的应用需要具有感测或致动能力的IC封装,因此需要一种IC封装和制造方法,使得提供对包封在IC封装中的管芯(die)构件的改进的接近和暴露。具体地,管芯构件可以包括传感器和/或致动器,其中对传感器和/或致动器的改进的接近和暴露会增加IC封装的多样性。
根据本发明,公开了一种集成电路封装和有效制造方法,从而至少部分地满足上述需要。
图1示出根据本发明的集成电路封装的阵列的实施方式的三维视图;以及图2示出根据本发明的单个分开的IC封装的实施方式的三维视图。
本发明的制造如图2所示的IC封装的方法例如开始于步骤a)提供连接到模具中的相应电接触构件8a、8b的多个管芯构件4a、4b。在实施方式中,每个管芯构件4a、4b可以利用对应的接合线7连接到一个或多个相应的电接触构件8a、8b。在另一实施方式中,每个管芯构件4a、4b可以直接安装或连接到一个或多个相应的电接触构件8a、8b。在其他实施方式中,每个管芯构件4a、4b可以通过引脚框架和/或插入器连接到一个或多个相应的电接触构件8a、8b,如用于例如LGA/BGA封装。
为了允许在最终产品(即,待制造的IC封装)中至少部分地暴露管芯构件4a、4b,该方法包括步骤b)提供与第一管芯构件4a的第一上表面6a的至少部分接触的模具插入件。模具插入件可以被膜叠加或覆盖,从而在需要时允许由膜辅助的模制,因此在实施方式中,步骤b)可以包括提供与第一管芯构件4a的第一上表面6a的至少部分接触的覆膜模具插入件。布置具有或没有膜的模具插入件(未示出),以防止在其他制造步骤期间封装材料至少部分地覆盖第一上表面6a。
一旦多个管芯构件4a、4b和相应的电接触构件8a、8b在模具中并且提供模具插入件,如上文概述,该方法随后包括步骤c)将多个管芯构件4a、4b和相应的电接触构件8a、8b包封到封装收集主体3中。封装收集主体3可以被构建为阵列布置或一批多个IC封装,但要分成多个单独的IC封装。在包封期间,模具插入件防止任何封装材料到达并至少部分地覆盖第一管芯构件4a的第一上表面6a,因为其在最终产品中应保持暴露。在实施方式中,包封步骤可以被视作使用例如热塑性或热固性聚合物材料的包覆模制过程。
在包封步骤之后,获得固体或固化的封装收集主体3,其中多个管芯构件4a、4b和相应的电接触构件8a、8b至少部分地嵌入该封装收集主体中并且其中开口16、凹部16或凹部状特征16由模具插入件设在封装收集主体3中。开口16从封装收集主体3的上表面10延伸到第一管芯构件4a的第一上表面6a的至少一部分。应注意,如图1所示,可以使用相应多个模具插入件来设置多个开口16,该多个模具插入件可以是如先前所述的覆膜模具插入件。
根据本发明,随后通过方法步骤d)沿着第一切割线S1将封装收集主体3切成至少两个单独的集成电路封装3a、3b来获得具有对封装内部构件的改进的暴露和接近的IC封装,该第一切割线延伸穿过封装收集主体3并且分开多个管芯构件4a、4b,其中如在步骤b)中提供的模具插入件延伸跨过或跨越第一切割线S1的一部分,即,在包封步骤c)期间。
通过上述切割步骤d),改进对例如第一管芯构件4a的暴露,因为由模具插入件在封装收集主体3中形成的开口16或凹部状特征16随后被切成或剖成两个管芯开口18a、18b,每个管芯开口可以呈现为沿着相应分开的IC封装3a、3b的边缘布置的切口。
如图2所示,一旦封装收集主体3被切割并分成两个集成电路封装3a、3b,便获得第一管芯开口18a,从而至少部分地暴露第一管芯构件4a。具体地,第一管芯开口18a包括开口16的部分(例如,一半),而且还包括从第一集成电路封装3a的(四个侧表面12a中的)第一侧表面12a延伸到第一管芯构件4a的第一上表面6a的第一侧部开口17a,以及其中第一侧部开口17a沿着第一切割线布置S1。也就是,通过切割封装收集主体3,形成第一切割表面14作为封装3a的(四个)侧表面12a中的一者,其中第一侧部开口17a位于第一切割表面14内。在包封步骤完成后,第一侧部开口17a还可以被视作如由模具插入件形成的开口或凹部16的横截面。
如图1的示例性实施方式所示,开口16由边界壁19界定,该边界壁基本上垂直于封装收集主体3的(主)上表面10延伸(并且分别基本上垂直于管芯构件4a的上表面6a和管芯构件4b的上表面6b)。在替代实施方式中,边界壁19可以是倾斜壁或弯曲壁。类似地,边界壁19也界定相应分开的封装3a、3b中的第一管芯开口18a和第二管芯开口18b。
通过上述方法步骤a)到d),提供一种制造第一集成电路封装3a的有效方式,该第一集成电路封装包括用于暴露第一管芯构件4a的第一管芯开口18a,其中第一管芯开口18a由第一集成表面封装3a的两个外表面或侧面中的两个开口限定。例如,第一集成电路封装3a包括第一上表面10a中的第一上部开口,因为在包封期间模具穿过封装收集主体3的上表面10突出到封装收集主体3中,并且通过沿着第一切割线S1进行切割在侧表面12a的一者中获得第一侧部开口17a。
如上文公开的第一管芯开口18a容易作为管芯开口进行推广,该管芯开口包括诸如上部开口和侧部开口17a的多个开口,借此暴露管芯构件并且如有需要可以接近管芯构件。管芯开口18a允许来自相对于设置有该管芯开口的IC封装的不同方向的感测或致动能力,以便增加IC封装的通用性。例如,如果对IC封装存在高度限制,那么在IC封装中具有侧部开口17a可以允许朝向侧面的感测和致动能力(例如,通过流体接近所暴露的管芯构件4a、4b并与其流体接触)。如果对IC封装存在宽度限制,那么上部开口允许相同IC封装的感测和致动能力。
利用上述方法,现在有可能有效地制造多个集成电路封装3a、3b,其中每个IC封装3a、3b提供对包封于其中的管芯构件4a、4b的改进的接近和暴露。
在实施方式中,用于提供连接到相应电接触构件8a、8b的多个管芯构件4a、4b的方法步骤a)还可以包括提供沿着第一切割线S1相对于第一管芯构件4a成镜像的第二管芯构件4b。通过这个实施方式,当沿着第一切割线S1切穿封装收集主体3时,获得两个单独的IC封装3a、3b,其中第一管芯构件4a和第二管芯构件4b是分开的。所获得的两个IC封装3a、3b两者都包括如上文概述的管芯开口,即,分别是第一管芯开口18a和第二管芯开口18b。
如在步骤d)中执行的沿着第一切割线S1进行切割还可以包括切穿相应的电接触构件8a、8b。这样一来会提供分别与第一IC封装3a的第一侧表面12a和第二IC封装3b的第二侧表面12b齐平的相应电接触构件8a、8b。例如,在图1中,示出了跨越第二切割线S3的其他电接触构件9。在沿着第二切割线S3完成切割步骤后,其他电接触构件9将至少部分地跟随第二切割线S3与分开的第二IC封装3b的四个第二侧表面12b中的一者齐平。
如在步骤b)中提供的模具插入件延伸跨过或跨越第一切割线S1的部分,其中至少两个分开的IC封装3a、3b两者可以得益于通过相应第一管芯开口18a和第二管芯开口18b的改进的暴露和接近,每个管芯开口18a、18b包括开口或凹部16的一部分以及通过在切割步骤期间切穿封装收集主体3和开口或凹部16而形成的第一侧部开口17a和第二侧部开口(未示出)。
在有利实施方式中,该方法还可以包括将模具插入件对称地布置在第一切割线S1上。也就是,在包封多个管芯构件4a、4b和相应的电接触构件8a、8b之后,开口16对称地跨越第一切割线S1,其中每个分开的IC封装3a、3b包括相同形状和尺寸的相应第一管芯开口18a和第二管芯开口18b。至于模具插入件的形状,该方法还可以包括为模具插入件选择圆形、椭圆形、正方形、矩形或多边形形状。模具插入件的形状可以基于应用进行选择,并且可以取决于需要对管芯构件进行哪种尺寸和形状的暴露和接近。
为了在选择相应电接触构件8a、8b的特定包封布局时提供足够的自由,提供这样的实施方式,其中相应的电接触构件8a、8b相对于第一切割线S1成镜像。利用这个实施方式,模具插入件可以用来获得开口或凹部16,该开口或凹部从封装收集主体3的上表面10延伸到第一管芯构件4a的第一上表面6a的至少部分,并且延伸到第二管芯构件4b的第二上表面6b的至少部分。两个分开的IC封装3a、3b便具有相对于彼此的相应电接触构件8a、8b的镜像布局,但每个IC封装3a、3b包括相应的管芯开口18a、18b,每个管芯开口具有上部开口和侧部开口,从而改进对管芯的暴露。
在替代实施方式中,相应电接触构件8a、8b并不相对于第一切割线S1成镜像。在这个实施方式中,模具插入件以及其放置与上述实施方式相同,但相应电接触构件8a、8b的放置和布局无需相对于第一切割线S1成镜像或对齐,从而允许第一IC封装3a和第二IC封装3b不是彼此的镜像版本,因此为第一IC封装3a和第二IC封装3b的电接触构件布局提供进一步的灵活性。
因此,鉴于上述内容,本发明的方法允许制造具有不同电接触构件布局的多个电路封装(例如,QFN、LGA、BGA封装),以满足各种规格但使得能够将单个模具插入件用于在封装收集主体3中提供开口或凹部16,从而至少部分地暴露两个或更多管芯构件4a、4b。
可想到电接触构件8a、8b的其他替代布局和放置。例如,在又一实施方式中,至少两个单独的集成电路封装3a、3b是方形扁平无引脚(QFN)封装。这个实施方式通过切割步骤d)有效地获得,该切割步骤还可以包括切穿相应电接触构件8a、8b,以便所述构件8a、8b变得与分开的IC封装3a、3b的侧表面齐平。在这个实施方式中,相应电接触构件8a、8b随后可以被视作相应引脚框架构件8a、8b。在其他实施方式中,至少两个单独的集成电路封装3a、3b是连接盘网格阵列(LGA)封装或球栅阵列(BGA)封装。
参考图1,在实施方式中,该方法步骤还包括将多个管芯构件4a、4b和相应电接触构件8a、8b布置在阵列中,即,在封装收集主体3中允许多个管芯构件4a、4b和相应电接触构件8a、8b的基于行和列的布置。基于行和列的阵列布置允许第一切割线S1平直,从而简化切穿封装收集主体3。在另一实施方式中,可选地由膜覆盖的一个或多个模具插入件可以放置在阵列布置中,以在包封多个管芯构件4a、4b和相应电接触构件8a、8b之后获得多个开口或凹部16的阵列布置。在实施方式中,多个模具插入件16对称地跨越第一切割线S1。例如,图1示出有利实施方式,其中多个开口16以列向方式布置,以便沿着第一切割线S1的切割会将每个开口或凹部16剖成两个部分,每个部分是至少部分地暴露相应管芯构件4a、4b的管芯开口18、18b。
鉴于如图1所示的上述阵列布置,可以限定垂直于第一切割线S1的一条或多条其他切割线S2、S4,以用于进一步分开封装收集主体3内的至少两个IC封装3a、3b。具体地,方法步骤d)切割封装收集主体3还可以包括沿着一条或多条其他切割线S2、S4切割封装收集主体3,这些其他切割线垂直于第一切割线S1延伸穿过封装收集主体3。通过这个实施方式,例如,随后从封装收集主体3中进一步分开至少两个IC封装3a、3b。在另一实施方式中,沿着一条或多条其他切割线S2、S4切割也可以包括切穿电接触构件8a、8b,这有利于获得QFN电路封装。
根据本发明,该方法允许在IC封装中提供改进的感测和/或致动能力。例如,在实施方式中,第一管芯构件4a可以包括压力和/或温度传感器,以便向集成电路封装提供感测能力。在另一实施方式中,还可以提供致动能力,因为第一管芯构件4a可以包括有源元件,诸如燃烧开始元件或传感器元件。燃烧开始元件可以被配置成用于提供热量(例如,热点)。为此,可以提供这样的实施方式,其中燃烧开始元件是例如灼热丝。在示例性实施方式中,这样的燃烧开始元件可以有助于点燃提供在由开口16形成的空间中的燃烧材料,其中第一管芯构件4a包括例如灼热丝等作为燃烧开始元件。可以由开口16的适当形状增强对燃烧开始元件的适当点火。
基于可从本发明的方法中获得的上述IC封装,在另一方面,本发明涉及以示例性方式在图2中示出的集成电路封装1。集成电路封装1包括连接到至少部分地包封在封装3a中的一个或多个电接触构件8a的管芯构件4a。一个或多个电接触构件8a可以在封装3a的(一个或多个)侧表面12a处暴露。在实施方式中,一个或多个电接触构件8a可以与侧表面12a齐平,诸如用于QFN封装的类型的一个或多个电接触构件。在另一实施方式中,一个或多个电接触构件8a可以具体化为用于LGA封装的类型的扁平或垫状接触构件。在又一实施方式中,一个或多个电接触构件8a可以具体化为用于BGA封装的类型的球状接触构件。
根据本发明,在IC封装1中提供管芯开口18a,从而暴露管芯构件4a的至少部分,其中封装3a的一个侧表面12是第一切割表面14。管芯开口18a包括从封装3a的上(主)表面10a延伸到管芯构件4a的上表面6a的上部开口16,以及从第一切割表面14延伸到管芯构件4a的上表面6a的侧部开口17a。
在另一实施方式中,由于如上所述在封装收集主体3中形成上部开口16,因此上部开口16具有从上(主)表面10a延伸到管芯构件4a的上表面6a的边界壁19,如图1和图2的示例性视图所示。
因此,本发明的集成电路封装1包括从多个侧面或表面,即,从封装3a的上部开口16和侧部开口17a至少部分地暴露管芯构件4a的管芯开口18a。为了进一步清楚起见,管芯开口18a可以被视作沿着封装3a的边缘布置的切口,借此IC封装1允许暴露和接近管芯构件4a,以从相对于封装3a的不同方向获得感测和/或致动能力。例如,如果在将IC封装1用于特定应用时存在高度限制,那么可以通过侧部开口17a来利用感测和/或致动能力。如果在使用IC封装1时存在宽度限制,那么可以从封装3a的上部开口16利用感测和/或致动能力。
在有利实施方式中,管芯构件4a包括燃烧开始元件,以便可能在内燃机应用中实现集成电路封装1的紧凑和通用布置。在示例性实施方式中,燃烧开始元件是加热元件,诸如灼热丝,其中加热元件可以帮助燃烧点火。这些实施方式清楚地表明,本发明的IC封装1可以用于更多种类的应用。
上文已经参考在附图示出并参考附图描述的许多示例性实施方式描述了本发明。对一些部分或元件的修改和替代实施是可能的,并且包括在如所附权利要求限定的保护范围内。
Claims (14)
1.一种制作集成电路封装的方法,包括以下步骤:
a)提供连接到模具中的相应电接触构件(8a、8b)的多个管芯构件(4a、4b);
b)提供与第一管芯构件(4a)的第一上表面(6a)的至少部分接触的模具插入件;
c)将所述多个管芯构件(4a、4b)和所述相应电接触构件(8a、8b)包封到封装收集主体(3)中;以及
d)沿着第一切割线(S1)将所述封装收集主体(3)切成至少两个单独的集成电路封装(3a、3b),所述第一切割线(S1)延伸穿过所述封装收集主体(3),并且分开所述多个管芯构件(4a、4b),其中如在步骤b)中提供的所述模具插入件延伸跨过所述第一切割线(S1)的部分,
由此形成第一管芯开口(18a),所述第一管芯开口(18a)包括:
上部开口(16)的一部分,从所述至少两个集成电路封装(3a、3b)中的第一集成电路封装(3a)的第一上表面(10a)延伸到所述第一管芯构件(4a)的第一上表面(6a),以及
第一侧部开口(17a),从所述第一集成电路封装(3a)的第一侧表面(12a)延伸到所述第一管芯构件(4a)的所述第一上表面(6a),其中所述第一侧部开口(17a)沿着所述第一切割线(S1)布置。
2.根据权利要求1所述的方法,还包括:提供第二管芯构件(4b),所述第二管芯构件(4b)沿着所述第一切割线(S1)相对于所述第一管芯构件(4a)成镜像。
3.根据权利要求1所述的方法,其中所述至少两个单独的集成电路封装(3a、3b)是方形扁平无引脚(QFN)封装、连接盘网格阵列(LGA)封装或者球栅阵列(BGA)封装。
4.根据权利要求1所述的方法,还包括:将所述多个管芯构件(4a、4b)和所述相应电接触构件(8a、8b)布置成阵列。
5.根据权利要求1所述的方法,其中所述第一管芯构件(4a)包括有源元件。
6.根据权利要求1所述的方法,其中所述第一管芯构件(4a)包括燃烧开始元件或传感器元件。
7.根据权利要求1所述的方法,其中所述相应电接触构件(8a、8b)并不相对于所述第一切割线(S1)成镜像。
8.根据权利要求1所述的方法,其中所述相应电接触构件(8a、8b)相对于所述第一切割线(S1)成镜像。
9.根据权利要求1所述的方法,还包括将所述模具插入件对称地布置在所述第一切割线(S1)上。
10.根据权利要求1所述的方法,还包括为所述模具插入件选择圆形、椭圆形或多边形形状。
11.根据权利要求10所述的方法,其中所述多边形形状为正方形或矩形形状。
12.一种集成电路封装,包括管芯构件(4a),所述管芯构件(4a)连接到包封在封装(3a)中的一个或多个电接触构件(8a),以及其中提供管芯开口(18a),以暴露所述管芯构件(4a)的至少部分,其中所述封装(3a)的一个侧表面(12a)是直的第一切割表面(14),
其中所述管芯开口(18a)包括从所述封装(3a)的上表面(10a)延伸到所述管芯构件(4a)的上表面(6a)的上部开口(16),以及侧部开口(17a),所述侧部开口(17a)位于所述直的第一切割表面(14)中,并从所述直的第一切割表面(14)延伸到所述管芯构件(4a)的所述上表面(6a),其中,所述侧部开口(17a)形成为所述上部开口(16)的剖面。
13.根据权利要求12所述的集成电路封装,其中所述上部开口(16)具有从所述封装(3a)的所述上表面(10a)延伸到所述管芯构件(4a)的所述上表面(6a)的边界壁(19)。
14.根据权利要求12所述的集成电路封装,其中所述管芯构件(4a)包括燃烧开始元件。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP16170345.9 | 2016-05-19 | ||
EP16170345 | 2016-05-19 | ||
PCT/NL2017/050315 WO2017200384A1 (en) | 2016-05-19 | 2017-05-18 | Integrated circuit package and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109075139A CN109075139A (zh) | 2018-12-21 |
CN109075139B true CN109075139B (zh) | 2022-12-27 |
Family
ID=56026698
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201780029132.9A Active CN109075139B (zh) | 2016-05-19 | 2017-05-18 | 集成电路封装以及其制造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US10593567B2 (zh) |
EP (1) | EP3459109B1 (zh) |
CN (1) | CN109075139B (zh) |
AU (1) | AU2017266836B2 (zh) |
WO (1) | WO2017200384A1 (zh) |
ZA (1) | ZA201807263B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11233002B2 (en) | 2019-10-10 | 2022-01-25 | Marvell Asia Pte, Ltd. | High density low power interconnect using 3D die stacking |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5886398A (en) * | 1997-09-26 | 1999-03-23 | Lsi Logic Corporation | Molded laminate package with integral mold gate |
US6420201B1 (en) * | 2001-01-03 | 2002-07-16 | Amkor Technology, Inc. | Method for forming a bond wire pressure sensor die package |
DE10109327A1 (de) | 2001-02-27 | 2002-09-12 | Infineon Technologies Ag | Halbleiterchip und Herstellungsverfahren für ein Gehäuse |
NL1019042C2 (nl) | 2001-09-26 | 2003-03-27 | Europ Semiconductor Assembly E | Werkwijze voor het inkapselen van een chip en/of ander voorwerp. |
US8124451B2 (en) | 2007-09-21 | 2012-02-28 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer |
JP2009099680A (ja) * | 2007-10-15 | 2009-05-07 | Panasonic Corp | 光学デバイスおよびその製造方法 |
JP5743922B2 (ja) | 2012-02-21 | 2015-07-01 | 日立オートモティブシステムズ株式会社 | 熱式空気流量測定装置 |
US20130299955A1 (en) * | 2012-05-08 | 2013-11-14 | Nxp B.V. | Film based ic packaging method and a packaged ic device |
US9448130B2 (en) * | 2013-08-31 | 2016-09-20 | Infineon Technologies Ag | Sensor arrangement |
DE102014202821B4 (de) * | 2014-02-17 | 2023-03-30 | Robert Bosch Gmbh | Gehäuse für ein mikromechanisches Sensorelement |
US9236331B2 (en) * | 2014-02-25 | 2016-01-12 | Freescale Semiconductor, Inc. | Multiple die lead frame |
US9297713B2 (en) * | 2014-03-19 | 2016-03-29 | Freescale Semiconductor,Inc. | Pressure sensor device with through silicon via |
US9346667B2 (en) * | 2014-05-27 | 2016-05-24 | Infineon Technologies Ag | Lead frame based MEMS sensor structure |
US20160068387A1 (en) * | 2014-09-09 | 2016-03-10 | Texas Instruments Incorporated | Semiconductor cavity package using photosensitive resin |
US10717645B2 (en) * | 2014-12-17 | 2020-07-21 | Robert Bosch Gmbh | Exposed-die mold package for a sensor and method for encapsulating a sensor that interacts with the environment |
US9896330B2 (en) * | 2016-01-13 | 2018-02-20 | Texas Instruments Incorporated | Structure and method for packaging stress-sensitive micro-electro-mechanical system stacked onto electronic circuit chip |
US20170278825A1 (en) * | 2016-03-24 | 2017-09-28 | Freescale Semiconductor, Inc. | Apparatus and Methods for Multi-Die Packaging |
CN107290096A (zh) * | 2016-04-11 | 2017-10-24 | 飞思卡尔半导体公司 | 具有膜片的压力感测集成电路器件 |
-
2017
- 2017-05-18 US US16/301,448 patent/US10593567B2/en active Active
- 2017-05-18 CN CN201780029132.9A patent/CN109075139B/zh active Active
- 2017-05-18 AU AU2017266836A patent/AU2017266836B2/en active Active
- 2017-05-18 EP EP17728946.9A patent/EP3459109B1/en active Active
- 2017-05-18 WO PCT/NL2017/050315 patent/WO2017200384A1/en unknown
-
2018
- 2018-10-30 ZA ZA2018/07263A patent/ZA201807263B/en unknown
Also Published As
Publication number | Publication date |
---|---|
AU2017266836A1 (en) | 2018-11-22 |
CN109075139A (zh) | 2018-12-21 |
US20190295860A1 (en) | 2019-09-26 |
WO2017200384A1 (en) | 2017-11-23 |
AU2017266836B2 (en) | 2022-06-09 |
ZA201807263B (en) | 2021-04-28 |
EP3459109A1 (en) | 2019-03-27 |
US10593567B2 (en) | 2020-03-17 |
EP3459109B1 (en) | 2021-11-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0813236B1 (en) | Method for encapsulating an integrated semi-conductor circuit | |
US6611047B2 (en) | Semiconductor package with singulation crease | |
KR101297015B1 (ko) | 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지 | |
US7838973B2 (en) | Semiconductor device | |
US7030505B2 (en) | Resin-sealed-type semiconductor device, and production process for producing such semiconductor device | |
US9184118B2 (en) | Micro lead frame structure having reinforcing portions and method | |
US20180122731A1 (en) | Plated ditch pre-mold lead frame, semiconductor package, and method of making same | |
US7719845B1 (en) | Chamfered memory card module and method of making same | |
US9768091B2 (en) | Method of forming an electronic package and structure | |
KR20080076063A (ko) | 반도체 패키지용 리드프레임 | |
KR0141952B1 (ko) | 반도체 패키지 및 그 제조방법 | |
US9134193B2 (en) | Stacked die sensor package | |
US9673122B2 (en) | Micro lead frame structure having reinforcing portions and method | |
CN109075139B (zh) | 集成电路封装以及其制造方法 | |
CN105097749A (zh) | 组合的qfn和qfp半导体封装 | |
US8415793B2 (en) | Wafer and substructure for use in manufacturing electronic component packages | |
KR20040108582A (ko) | 반도체 장치 및 그 제조 방법 | |
US20170221802A1 (en) | Semiconductor Device Packaging Assembly, Lead Frame Strip and Unit Lead Frame with Molding Compound Channels | |
US8853840B2 (en) | Semiconductor package with inner and outer leads | |
CN102891090A (zh) | 半导体器件及其封装方法 | |
JP3380464B2 (ja) | リードフレームおよびそれを用いた半導体装置ならびに半導体装置の製造方法 | |
CN106158810B (zh) | 用于ic封装的具有偏转的连接杆的引线框架 | |
US6616436B1 (en) | Apparatus for manufacturing semiconductor packages | |
US20060278964A1 (en) | Plastic integrated circuit package, leadframe and method for use in making the package | |
US20090166820A1 (en) | Tsop leadframe strip of multiply encapsulated packages |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |