CN109066923A - Logic control circuit, battery protection chip and circuit for the charging of 0V battery - Google Patents
Logic control circuit, battery protection chip and circuit for the charging of 0V battery Download PDFInfo
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- CN109066923A CN109066923A CN201811178661.8A CN201811178661A CN109066923A CN 109066923 A CN109066923 A CN 109066923A CN 201811178661 A CN201811178661 A CN 201811178661A CN 109066923 A CN109066923 A CN 109066923A
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- 230000004224 protection Effects 0.000 title claims abstract description 22
- 230000001681 protective effect Effects 0.000 claims abstract description 58
- 238000001514 detection method Methods 0.000 claims abstract description 45
- 238000013519 translation Methods 0.000 claims abstract description 31
- 230000005611 electricity Effects 0.000 claims description 17
- 239000013078 crystal Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 4
- 229910052744 lithium Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910001416 lithium ion Inorganic materials 0.000 description 2
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H02J7/0086—
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/0031—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using battery or load disconnect circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/00302—Overcharge protection
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- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The present embodiments relate to a kind of logic control circuit, battery protection chip and circuit for the charging of 0V battery, which includes: pressure-resistant protective module, the locking of charge control current potential and current potential translation module；The current potential of charge and discharge electro-detection signal input part CS is increased to required current potential by pressure-resistant protective module, the locking of charge control current potential and current potential translation module are supplied to by pressure-resistant protective module output end CS1；The current potential of the gate control terminal OC of charge control in battery protecting circuit transistor is fixed on the current potential of power supply positive input terminal VDD after 0V battery accesses charger by the charge control current potential locking module in the locking of charge control current potential and current potential translation module；The input signal that high/low level is VDD/0V is transformed into the output signal that high/low level is VDD/CS1 by current potential translation module, to control the turn-on and turn-off of charge control transistor.
Description
Technical field
The present invention relates to battery boosting technology field more particularly to it is a kind of for 0V battery charging logic control circuit,
Battery protection chip and circuit.
Background technique
How to realize that 0V charge function has become one of the key of current design in application fields such as li-ion cell protections.0V fills
Electricity, which refers to, recharges the battery of self discharge to 0V in the case where lithium battery license.In the industry for the skill of 0V charging
Art has carried out a large amount of research, and the implementation method proposed at present includes the following two kinds: first is that utilizing depletion device and thick grid oxygen
Device is realized, second is that realized using thick grid oxygen device.
Fig. 1 is the circuit diagram that 0V charging is realized using depletion device and thick grid oxygen device.
N1 is depletion device in figure, and wherein VDD is power supply positive input terminal, and CS is charging and discharging currents test side, and COUT is
Charge inside controls signal, and OC is the grid control terminal of charge control transistor (FET), each metal oxide half in circuit
Conductor field-effect (MOS) pipe is thick grid oxygen device.Battery to 0V and when not accessing charger, there is VDD=due to self-discharge
0V, COUT=0V, CS=0V, P1 ends at this time, since N1 is that depletion device and grid source are connected, therefore N1 is connected and is in linear
Area, no current exists in the branch, and the grid potential of P2 and N2 are equal to CS current potential, and CS current potential and VDD current potential be identical at this time
For 0 current potential, therefore N2 and P2 are turned off, and equally, P3, N3, P4, N4 are similarly in off state, and output end OC is zero potential.Access
After charger, due to the effect of charger, CS current potential becomes negative potential, and size is related with charger starting voltage, charger
Starting voltage is bigger, and the current potential of CS is more negative, when the starting voltage of charger is greater than some value (V0CH), the current potential of CS is also as low as energy
Enough so that P2 is begun to turn on, N2, which is in, at this time ends, current potential of the grid potential equal to VDD of P3 and N3, N3 conducting, P3 cut-off,
The grid potential of P4 and N4 is equal to the current potential of CS, P4 conducting, N4 cut-off, and output end OC current potential is equal to VDD current potential.I.e. due to
After the lithium battery of self-discharge to 0V access charger, charge control is fixed on the terminal electricity of VDD with the gate voltage of FET
Pressure, and charge control is CS with the source of FET, is opened charge control with FET using the pressure difference between OC and CS, formation is filled
Electrical circuit starts to charge to 0V battery；Here it is 0V charging realization principles.In short, realizing that 0V charge function is exactly 0V
Battery can guarantee that charge control is fixed on VDD terminal voltage with the gate voltage of FET after accessing charger, utilize charger
Charger is controlled with the gate pole of FET with pressure difference between source electrode and is connected with FET by control, realizes charging.
The shortcomings that this implementation is: N1 is depletion type NMOS device, and the grid source of P2, N3, P4 device needs are resistance to
High pressure but its cut-in voltage again cannot be too big, because if that requires charger starting voltage V if cut-in voltage is too big0CH
It is very big, it is not inconsistent with practical application；Many techniques cannot meet the two conditions simultaneously, then the applicability of this circuit is just paid no attention to
Think.
Fig. 2 is the circuit diagram that 0V charging is realized using thick grid oxygen device.Likewise, battery is due to self-discharge
To 0V, when not accessing charger, there are VDD=0, COUT=0, CS=0, P5 is in off state at this time, and N5, which is similarly in, to be cut
Only state；After accessing charger, due to the effect of charger, CS current potential becomes negative potential, size and charger starting electricity
It is pressed with pass, charger starting voltage is bigger, and the current potential of CS is more negative after access charger, when the starting voltage of charger is greater than some
It is worth (V0CH) when, the current potential of CS is also as low as that can make the grid source pressure difference of N5 be greater than the cut-in voltage of device, and N5 conducting, P5 is still at this time
So in cut-off；The grid potential of P6 and N6 is equal to the current potential of CS, N6 cut-off, and P6 is on, and output end OC current potential is equal to VDD
After accessing charger, charge control is fixed on VDD terminal voltage with the gate voltage of FET, and charges for current potential, i.e. 0V battery
Control is CS with the source current potential of FET, using pressure difference between OC and CS by the conducting of the FET of charge control, is realized to 0V electricity
It charges in pond.
Implementation its shortcoming is that: the grid source of N5 and P6 needs high pressure resistant but cut-in voltage cannot be too high；If same
Too greatly, that requires charger starting voltage V to cut-in voltage0CHIt is very big, it is not inconsistent with practical application.
Although both current 0V charge it can be found that second of solution is avoided using depletion device
Implementation has some limitations, and special technique is needed to support that 0V charge function just may be implemented.
Therefore, a kind of better circuit of versatility is urgently developed in the industry, is not needed depletion device, is not needed the resistance to height in grid source
Pressure and cut-in voltage again cannot be too high device, and without to the limitation on making technology.
Summary of the invention
The object of the present invention is to provide a kind of logic control circuit, battery protection chip and electricity for the charging of 0V battery
Road, solves the problems, such as device pressure resistance by increasing pressure-resistant protective module, translates mould by the locking of charge control current potential and current potential
Block realizes that the current potential of the gate control terminal OC of the charge control transistor in battery protecting circuit is fixed on power supply positive input
The current potential of terminal VDD, and the input signal that high/low level is VDD/0V is transformed into the output that high/low level is VDD/CS1 and is believed
Number, to realize the turn-on and turn-off logic of control charge control transistor.
To achieve the above object, in a first aspect, the present invention provides a kind of logic control electricity for the charging of 0V battery
Road, comprising:
Pressure-resistant protective module, the locking of charge control current potential and current potential translation module；
The input terminal of the pressure resistance protective module is charge and discharge electro-detection signal input part CS, output end CS1, resistance R6 string
It is connected between the charge and discharge electro-detection signal input part CS and pressure-resistant protective module output end CS1；When charge and discharge power detection signal is defeated
The voltage for entering to hold CS is timing, the voltage of pressure-resistant protective module output end CS1 and the voltage of charge and discharge electro-detection signal input part CS
It is identical；When the voltage of charge and discharge electro-detection signal input part CS is negative, the voltage of pressure-resistant protective module output end CS1 is relative to filling
The voltage of discharge examination signal input part CS has the positive differential pressure of δ V；The electricity of the size of δ V and pressure-resistant protective module output end CS1
Pressing element has functional relation；
The charge control current potential locking and current potential translation module include: charge control current potential locking module and current potential translation
Module；The input terminal of the charge control current potential locking and current potential translation module is charge and discharge electro-detection signal input part CS, pressure resistance
The reversed phase signal COUTB of protective module output end CS1 and battery protecting circuit charge inside control signal, output end are battery guarantor
The gate control terminal OC of charge control transistor in protection circuit；
Wherein, the charge control current potential locking module includes the first PMOS transistor P8, the second PMOS transistor P9, the
One NMOS transistor N7 and resistance R4；Wherein, the grid of the first PMOS transistor P8 and the first NMOS transistor N7 is and power supply
Negative input terminal VSS connection, resistance R4 are connected in series between the first PMOS transistor P8 and the drain electrode of the first NMOS transistor；
The source electrode of first NMOS transistor is connected with pressure resistance protective module output end CS1；First PMOS transistor P8 and the 2nd PMOS is brilliant
The source electrode of body pipe P9 is connect with power supply positive input terminal VDD, the drain electrode and the second PMOS transistor of the first PMOS transistor P8
The grid of P9 is connected；The drain electrode of second PMOS transistor P9 connects with gate control terminal OC；In power supply negative input terminal VSS
Voltage and pressure-resistant protective module output end CS1 voltage between pressure difference when being greater than given threshold, the gate control terminal
The voltage of OC is equal to the voltage of power supply positive input terminal VDD；
The current potential translation module includes third PMOS transistor P10 and resistance R5；Wherein, third PMOS transistor P10
Grid meet the signal COUTB, source electrode is connect with power supply positive input terminal VDD, the drain electrode of third PMOS transistor P10 and institute
Gate control terminal OC is stated to connect, resistance R5 be serially connected in charge and discharge electro-detection signal input part CS and the gate control terminal OC it
Between, the current potential of gate control terminal OC is promoted, the input signal that high/low level is VDD/0V is transformed into high/low electricity
The output signal for VDD/CS1 is equalled, to control the turn-on and turn-off of the charge control transistor.
Preferably, the pressure-resistant protective module specifically includes: the second NMOS transistor N8, third NMOS transistor N9, the
Four PMOS transistor P11, the 5th PMOS transistor P12, the 6th PMOS transistor P13, triode T1 and the resistance R6；
6th PMOS transistor P13, the second NMOS transistor N8 and triode T1 are connected in series in power supply positive input terminal
Between VDD and power supply negative input terminal VSS；Wherein, the grid of the 6th PMOS transistor P13 connects current source bias signal, by electricity
Current offset module in pond protection circuit provides, to determine the size of current of the 6th place PMOS transistor P13 branch, the
The source electrode of six PMOS transistor P13 is connect with power supply positive input terminal VDD, and drain electrode connects grid and the leakage of the second NMOS transistor N8
Pole, the emitter of triode T1 are connect with the source electrode of the second NMOS transistor N8, and base stage and collector connect power supply negative input terminal
VSS；
Third NMOS transistor N9, the 4th PMOS transistor P11 and the 5th PMOS transistor P12 are being connected in series in power supply just
Between input terminal VDD and pressure-resistant protective module output end CS1；Wherein, the grid of third NMOS transistor N9 and the 6th PMOS
The drain electrode of transistor P13 connects, and the source electrode of the 4th PMOS transistor P11 meets the source electrode of third NMOS transistor N9, the 4th PMOS
The grid of transistor P11 and drain electrode connect the source electrode of the 5th PMOS transistor P12, the grid of the 5th PMOS transistor P12 and drain electrode
It is connected with pressure-resistant protective module output end CS1.
It is further preferred that the triode T1 is that PNP pipe or NPN are managed；
When for PNP pipe, emitter is connect with the source electrode of the second NMOS transistor N8, base stage and collector connect power supply bear it is defeated
Enter terminal VSS；
When for NPN pipe, base stage connects the source electrode of the second NMOS transistor N8 with collector, and emitter connects power supply negative input
Terminal VSS.
It is further preferred that in the pressure-resistant protective module, when charge and discharge electro-detection signal input part CS is positive potential,
Third NMOS transistor N9, the 4th PMOS transistor P11, the 5th PMOS transistor P12 are in off state, nothing in resistance R6
Electric current flows through, and the current potential of pressure-resistant protective module output end CS1 is identical with the current potential of charge and discharge electro-detection signal input part CS；Work as charge and discharge
The current potential of power detection signal input terminal CS be negative and absolute value be greater than third NMOS transistor N9, the 4th PMOS transistor P11 and
When the sum of the threshold value absolute value of the 5th PMOS transistor P12, third NMOS transistor N9, the 4th PMOS transistor P11, the 5th
PMOS transistor P12 is in the conductive state, has electric current to flow through in resistance R6, generates pressure resistance protective module output end CS1 and charge and discharge
Positive differential pressure δ V between power detection signal input terminal CS.
Preferably, in the locking of charge control current potential and current potential translation module, when 0V battery does not access charger, power supply
The current potential of positive input terminal VDD is 0V, the current potential of charge and discharge electro-detection signal input part CS and pressure-resistant protective module output end CS1 are
0V, charging control signal the current potential of reversed phase signal COUTB be 0V, the first PMOS transistor P8, the second PMOS transistor P9, the
Three PMOS transistor P10, the first NMOS transistor N7 are in off state, the gate control terminal of charge control transistor
OC is 0V, and pressure difference is 0V between gate control terminal OC and charge and discharge electro-detection signal input part CS.
Preferably, in the locking of charge control current potential and current potential translation module, when 0V battery accesses charger and charger
Starting voltage be greater than charging nominal voltage VOCHWhen, between power supply negative input terminal VSS and pressure-resistant protective module output end CS1
Pressure difference be greater than the first NMOS transistor N7 cut-in voltage, the first NMOS transistor N7 conducting, the first PMOS transistor P8 is still
In off state, current potential of the grid potential equal to pressure-resistant protective module output end CS1 of the second PMOS transistor P9, second
PMOS transistor P9 is begun to turn on, and for third PMOS transistor P10 still in off state, the second PMOS transistor P9 is in linear
Area, the current potential of gate control terminal OC are equal to the current potential of power supply positive input terminal VDD, i.e. the grid control of charge control transistor
The voltage of terminal OC processed is fixed on the voltage of power supply positive input terminal VDD, at this time the source voltage terminal of charge control transistor
Equal to the voltage of charge and discharge electro-detection signal input part CS.
Preferably, in the locking of charge control current potential and current potential translation module, when charging proceeds to power supply positive input terminal
When the voltage of VDD gradually rises the first PMOS transistor P8 of satisfaction, third PMOS transistor P10 conducting, the second PMOS transistor
The grid potential of P9 gradually rises to the current potential of power supply positive input terminal VDD, the second PMOS transistor P9 cut-off, at this time grid control
The level of terminal OC processed is determined by the signal COUTB.
Second aspect, the embodiment of the invention provides a kind of battery protection chips, including use described in above-mentioned first aspect
In the logic control circuit of 0V battery charging.
The third aspect, the embodiment of the invention provides a kind of battery protecting circuits, including electricity described in above-mentioned second aspect
Protect chip in pond.
Preferably, the grid of the grid of the charge control transistor and logic control circuit in the battery protection chip
Pole control terminal OC is connected.
Logic control circuit provided in an embodiment of the present invention for the charging of 0V battery, by increase pressure-resistant protective module come
It solves the problems, such as device pressure resistance, is realized after 0V battery accesses charger by the locking of charge control current potential and current potential translation module
The current potential of the gate control terminal OC of charge control transistor in battery protecting circuit is fixed on power supply positive input terminal VDD
Current potential, and the input signal that high/low level is VDD/0V is transformed into the output signal that high/low level is VDD/CS1, with reality
Now control the turn-on and turn-off logic of charge control transistor.
Detailed description of the invention
Fig. 1 is that the circuit using depletion device and thick grid oxygen device realization 0V charging that the prior art provides is illustrated
Figure；
Fig. 2 is the circuit diagram that 0V charging is realized using thick grid oxygen device that the prior art provides；
Fig. 3 is the schematic diagram of battery protecting circuit provided in an embodiment of the present invention；
Fig. 4 is the internal logic schematic diagram of battery protection chip provided in an embodiment of the present invention；
Fig. 5 is the block diagram of the logic control circuit provided in an embodiment of the present invention for the charging of 0V battery；
Fig. 6 is the logical circuitry of pressure-resistant protective module provided in an embodiment of the present invention；
The position Fig. 7 is the logical circuitry of electric control current potential provided in an embodiment of the present invention locking and current potential translation module.
Specific embodiment
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
In order to better understand the present invention for 0V battery charging logic control circuit, be applied to first environment into
Row explanation.
Logic control circuit for the charging of 0V battery of the invention is applied to the battery of battery protecting circuit shown in Fig. 3
It protects in chip, VDD is power supply positive input terminal in figure；VSS is power supply negative input terminal；OD is overdischarge abbreviation,
That is whether the gate control terminal of control of discharge transistor FET1, control lithium battery allow to discharge；OC is overcharge contracting
It writes, i.e. the gate control terminal of charge control transistor FET2, whether control lithium battery allows to charge；CS is current
Sense abbreviation, i.e. charge and discharge power detection signal are charged and discharged size of current for detecting, the terminal we be defined as charge and discharge
Detect signal input part CS.
In battery protection chip, internal logic is as shown in Figure 4.Logic control for the charging of 0V battery of the invention
Circuit is in control logic driving circuit.For 0V battery charging logic control circuit block diagram can with as shown in figure 5,
Including pressure-resistant protective module, the locking of charge control current potential and current potential translation module.Wherein, COUTB is inside battery protecting circuit
The reversed phase signal of charging control signal, charging control signal are that result is exported by overcharge detection comparator after logical operation
Obtained signal.
After being applied to environment and understanding, the logic control circuit for the charging of 0V battery of the invention is carried out below
It is described in detail.
It is known that the current potential of CS will appear the very big negative voltage of absolute value in li-ion cell protection system, then CS is just
Cannot directly it be connected with low-voltage device, two mentioned in the prior art kind solution is solved by technique level,
The part being connected with the end CS selects high pressure resistant device to solve.
In the present invention, device pressure resistance is solved the problems, such as by pressure-resistant protective module.
As shown in fig. 6, the input terminal of pressure-resistant protective module is charge and discharge electro-detection signal input part CS, output end CS1, electricity
Resistance R6 is serially connected between the charge and discharge electro-detection signal input part CS and pressure-resistant protective module output end CS1.
Pressure-resistant protective module specifically includes: the second NMOS transistor N8, third NMOS transistor N9, the 4th PMOS transistor
P11, the 5th PMOS transistor P12, the 6th PMOS transistor P13, triode T1 and the resistance R6；
6th PMOS transistor P13, the second NMOS transistor N8 and triode T1 are connected in series in power supply positive input terminal
Between VDD and power supply negative input terminal VSS；Wherein, the grid of the 6th PMOS transistor P13 connects current source bias signal, by electricity
Current offset module in pond protection circuit provides, to determine the size of current of the 6th place PMOS transistor P13 branch, the
The source electrode of six PMOS transistor P13 is connect with power supply positive input terminal VDD, and drain electrode connects grid and the leakage of the second NMOS transistor N8
Pole, triode T1 can manage for PNP pipe or NPN.
When for PNP pipe, emitter is connect with the source electrode of the second NMOS transistor N8, base stage and collector connect power supply bear it is defeated
Enter terminal VSS；When for NPN pipe, base stage connects the source electrode of the second NMOS transistor N8 with collector, emitter connect power supply bear it is defeated
Enter terminal VSS.
Third NMOS transistor N9, the 4th PMOS transistor P11 and the 5th PMOS transistor P12 are being connected in series in power supply just
Between input terminal VDD and pressure-resistant protective module output end CS1；Wherein, the grid of third NMOS transistor N9 and the 6th PMOS
The drain electrode of transistor P13 connects, and the source electrode of the 4th PMOS transistor P11 meets the source electrode of third NMOS transistor N9, the 4th PMOS
The grid of transistor P11 and drain electrode connect the source electrode of the 5th PMOS transistor P12, the grid of the 5th PMOS transistor P12 and drain electrode
It is connected with pressure-resistant protective module output end CS1.
When charge and discharge electro-detection signal input part CS is positive potential, third NMOS transistor N9, the 4th PMOS transistor
P11, the 5th PMOS transistor P12 are in off state, and no current flows through in resistance R6, pressure-resistant protective module output end CS1
Current potential it is identical with the current potential of charge and discharge electro-detection signal input part CS；Be negative when the current potential of charge and discharge electro-detection signal input part CS and
Absolute value is larger, meets the threshold for being greater than third NMOS transistor N9, the 4th PMOS transistor P11 and the 5th PMOS transistor P12
When being worth the sum of absolute value, third NMOS transistor N9, the 4th PMOS transistor P11, the 5th PMOS transistor P12 are on shape
State has electric current to flow through in resistance R6, generates between pressure resistance protective module output end CS1 and charge and discharge electro-detection signal input part CS
Positive differential pressure δ V.
Therefore, when the voltage of charge and discharge electro-detection signal input part CS is timing, the voltage of pressure-resistant protective module output end CS1
It is identical as the voltage of charge and discharge electro-detection signal input part CS；When the voltage of charge and discharge electro-detection signal input part CS is negative, pressure resistance
The voltage of protective module output end CS1 has the positive differential pressure of δ V relative to the voltage of charge and discharge electro-detection signal input part CS；CS's
It is worth more negative, δ V is bigger, the specific size of δ V can be designed according to practical application condition, meets resistance to pressure request with this.δV
Size and the voltage of pressure-resistant protective module output end CS1 there is functional relation, i.e. CS current potential is more negative, and CS1 current potential is also more negative, but
The absolute value of δ V increases；In the case where device parameters select suitable situation, though in the case where CS current potential is very negative it is also possible that
For the level of CS1 in suitable range, low-voltage device is can be used to realize in the device being connected in this way with the end CS1, to drop
The low requirement to technique, enhances the applicability of circuit.
The logic circuit structure of the locking of charge control current potential and current potential translation module is as shown in fig. 7, charge control current potential is locked
Fixed and current potential translation module includes: charge control current potential locking module 10 and current potential translation module 11；
The input terminal of the locking of charge control current potential and current potential translation module is charge and discharge electro-detection signal input part CS, pressure resistance is protected
The reversed phase signal COUTB of module output end CS1 and battery protecting circuit charge inside control signal are protected, output end is battery protection
The gate control terminal OC of charge control transistor in circuit；
Wherein, charge control current potential locking module 10 includes the first PMOS transistor P8, the second PMOS transistor P9, first
NMOS transistor N7 and resistance R4；Wherein, the grid of the first PMOS transistor P8 and the first NMOS transistor N7 are negative with power supply
Input terminal VSS connection, resistance R4 are connected in series between the first PMOS transistor P8 and the drain electrode of the first NMOS transistor；The
The source electrode of one NMOS transistor is connected with pressure resistance protective module output end CS1；First PMOS transistor P8 and the 2nd PMOS crystal
The source electrode of pipe P9 is connect with power supply positive input terminal VDD, the drain electrode of the first PMOS transistor P8 and the second PMOS transistor P9
Grid be connected；The drain electrode of second PMOS transistor P9 connects with gate control terminal OC；Power supply negative input terminal VSS's
When pressure difference between voltage and the voltage of pressure-resistant protective module output end CS1 is greater than given threshold, the gate control terminal OC
Voltage be equal to power supply positive input terminal VDD voltage；
Current potential translation module 11 includes third PMOS transistor P10 and resistance R5；Wherein, third PMOS transistor P10
Grid meets the signal COUTB, and source electrode is connect with power supply positive input terminal VDD, the drain electrode of third PMOS transistor P10 with it is described
Gate control terminal OC connects, resistance R5 be serially connected in charge and discharge electro-detection signal input part CS and the gate control terminal OC it
Between, the current potential of gate control terminal OC is promoted, the input signal that high/low level is VDD/0V is transformed into high/low electricity
The output signal for VDD/CS1 is equalled, to control the turn-on and turn-off of the charge control transistor.
In the locking of charge control current potential and current potential translation module, when 0V battery does not access charger, power supply positive input
The current potential of terminal VDD is 0V, the current potential of charge and discharge electro-detection signal input part CS and pressure-resistant protective module output end CS1 are 0V, fill
The current potential of the reversed phase signal COUTB of electric control signal is 0V, the first PMOS transistor P8, the second PMOS transistor P9, third
PMOS transistor P10, the first NMOS transistor N7 are in off state, the gate control terminal OC of charge control transistor
For 0V, pressure difference is 0V between gate control terminal OC and charge and discharge electro-detection signal input part CS.
After accessing charger, CS current potential becomes negative potential, and size is related with charger starting voltage, charger starting electricity
Pressure is bigger, and CS current potential is more negative after accessing charger.The signal of CS exports the signal of CS1, the letter of CS1 after pressure-resistant protective module
Number it is similarly negative voltage.
When the starting voltage that 0V battery accesses charger and charger is greater than charging nominal voltage VOCHWhen, power supply negative input
Cut-in voltage of the pressure difference greater than the first NMOS transistor N7 between terminal VSS and pressure-resistant protective module output end CS1, first
NMOS transistor N7 conducting, the first PMOS transistor P8 is still in off state, the grid potential etc. of the second PMOS transistor P9
In the current potential of CS1, the second PMOS transistor P9 is begun to turn on, and third PMOS transistor P10 is still in off state, the 2nd PMOS
Transistor P9 is in linear zone, and the current potential of gate control terminal OC is equal to the current potential of power supply positive input terminal VDD, i.e. charge control
The voltage of power supply positive input terminal VDD is fixed on the voltage of the gate control terminal OC of transistor, charge control is used at this time
The source voltage terminal of transistor is equal to the voltage of charge and discharge electro-detection signal input part CS.
With the progress of charging process, when the voltage that charging proceeds to power supply positive input terminal VDD gradually rises satisfaction the
When one PMOS transistor P8, third PMOS transistor P10 are connected, the grid potential of the second PMOS transistor P9 is gradually risen to electricity
The current potential of source positive input terminal VDD, the second PMOS transistor P9 cut-off, the level of gate control terminal OC is by the signal at this time
COUTB is determined.Enter normal logic control state.
The locking of charge control current potential and current potential translation module in the present invention, can guarantee after accessing charger in 0V battery
Charge control is fixed on VDD terminal voltage with the gate voltage of FET, is pressed using charge control between the gate pole of FET and source electrode
Charge control is connected difference with FET, realizes charging.
Compared with the prior art, the logic control circuit for the charging of 0V battery of the invention has the advantages that
(1) logic control circuit for the charging of 0V battery of the invention is not necessarily to depletion device compared with available circuit.
(2) logic control circuit for the charging of 0V battery of the invention is high pressure resistant without grid source compared with available circuit
And the device that cut-in voltage is moderate, it can be realized by thin grid oxygen device.
(3) logic control circuit for the charging of 0V battery of the invention solves compared with available circuit due to CS electricity
Press through negative bring a series of problems.
(4) requirement drop of the logic control circuit for the charging of 0V battery of the invention compared with available circuit, to technique
Low, the scope of application of circuit is wider.
Logic control circuit provided in an embodiment of the present invention for the charging of 0V battery, by increase pressure-resistant protective module come
It solves the problems, such as device pressure resistance, the charging in battery protecting circuit is realized by the locking of charge control current potential and current potential translation module
The current potential of the gate control terminal OC of control transistor is fixed on the current potential of power supply positive input terminal VDD, and by high/low level
It is transformed into the output signal that high/low level is VDD/CS1 for the input signal of VDD/0V, controls charge control crystal to realize
The turn-on and turn-off logic of pipe.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of logic control circuit for the charging of 0V battery, which is characterized in that the logic control circuit includes: pressure-resistant guarantor
Protect module, the locking of charge control current potential and current potential translation module；
The input terminal of the pressure resistance protective module is charge and discharge electro-detection signal input part CS, and output end CS1, resistance R6 are serially connected with
Between the charge and discharge electro-detection signal input part CS and pressure-resistant protective module output end CS1；When charge and discharge electro-detection signal input part
The voltage of CS is timing, and the voltage of pressure-resistant protective module output end CS1 is identical as the voltage of charge and discharge electro-detection signal input part CS；
When the voltage of charge and discharge electro-detection signal input part CS is negative, the voltage of pressure-resistant protective module output end CS1 is relative to charge and discharge
The voltage for detecting signal input part CS has the positive differential pressure of δ V；The voltage of the size of δ V and pressure-resistant protective module output end CS1 have
There is functional relation；
The charge control current potential locking and current potential translation module include: charge control current potential locking module and current potential translation mould
Block；The charge control current potential locks and the input terminal of current potential translation module is charge and discharge electro-detection signal input part CS, pressure resistance is protected
The reversed phase signal COUTB of module output end CS1 and battery protecting circuit charge inside control signal are protected, output end is battery protection
The gate control terminal OC of charge control transistor in circuit；
Wherein, the charge control current potential locking module includes the first PMOS transistor P8, the second PMOS transistor P9, first
NMOS transistor N7 and resistance R4；Wherein, the grid of the first PMOS transistor P8 and the first NMOS transistor N7 are negative with power supply
Input terminal VSS connection, resistance R4 are connected in series between the first PMOS transistor P8 and the drain electrode of the first NMOS transistor；The
The source electrode of one NMOS transistor is connected with pressure resistance protective module output end CS1；First PMOS transistor P8 and the 2nd PMOS crystal
The source electrode of pipe P9 is connect with power supply positive input terminal VDD, the drain electrode of the first PMOS transistor P8 and the second PMOS transistor P9
Grid be connected；The drain electrode of second PMOS transistor P9 connects with gate control terminal OC；Power supply negative input terminal VSS's
When pressure difference between voltage and the voltage of pressure-resistant protective module output end CS1 is greater than given threshold, the gate control terminal OC
Voltage be equal to power supply positive input terminal VDD voltage；
The current potential translation module includes third PMOS transistor P10 and resistance R5；Wherein, the grid of third PMOS transistor P10
Pole meets the signal COUTB, and source electrode is connect with power supply positive input terminal VDD, the drain electrode of third PMOS transistor P10 and the grid
Pole control terminal OC connects, and resistance R5 is serially connected between charge and discharge electro-detection signal input part CS and the gate control terminal OC,
The current potential of gate control terminal OC is promoted, the input signal that high/low level is VDD/0V, which is transformed into high/low level, is
The output signal of VDD/CS1, to control the turn-on and turn-off of the charge control transistor.
2. logic control circuit according to claim 1, which is characterized in that the pressure resistance protective module specifically includes: the
Bi-NMOS transistor N8, third NMOS transistor N9, the 4th PMOS transistor P11, the 5th PMOS transistor P12, the 6th PMOS
Transistor P13, triode T1 and the resistance R6；
6th PMOS transistor P13, the second NMOS transistor N8 and triode T1 be connected in series in power supply positive input terminal VDD with
Between power supply negative input terminal VSS；Wherein, the grid of the 6th PMOS transistor P13 connects current source bias signal, by battery protection
Current offset module in circuit provides, to the size of current of branch where determining the 6th PMOS transistor P13, the 6th PMOS
The source electrode of transistor P13 is connect with power supply positive input terminal VDD, is drained and is connect grid and the drain electrode of the second NMOS transistor N8, and three
The emitter of pole pipe T1 is connect with the source electrode of the second NMOS transistor N8, and base stage and collector meet power supply negative input terminal VSS；
Third NMOS transistor N9, the 4th PMOS transistor P11 and the 5th PMOS transistor P12 are connected in series in power supply positive input
Between terminal VDD and pressure-resistant protective module output end CS1；Wherein, the grid of third NMOS transistor N9 and the 6th PMOS crystal
The drain electrode of pipe P13 connects, and the source electrode of the 4th PMOS transistor P11 connects the source electrode of third NMOS transistor N9, the 4th PMOS crystal
The grid of pipe P11 and drain electrode connect the source electrode of the 5th PMOS transistor P12, the grid of the 5th PMOS transistor P12 and drain electrode with it is resistance to
Protective module output end CS1 is pressed to be connected.
3. logic control circuit according to claim 2, which is characterized in that the triode T1 is that PNP pipe or NPN are managed；
When for PNP pipe, emitter is connect with the source electrode of the second NMOS transistor N8, and base stage and collector connect power supply negative input end
Sub- VSS；
When for NPN pipe, base stage connects the source electrode of the second NMOS transistor N8 with collector, and emitter connects power supply negative input terminal
VSS。
4. logic control circuit according to claim 2, which is characterized in that in the pressure-resistant protective module, work as charge and discharge
When power detection signal input terminal CS is positive potential, third NMOS transistor N9, the 4th PMOS transistor P11, the 5th PMOS crystal
Pipe P12 is in off state, and no current flows through in resistance R6, the current potential of pressure-resistant protective module output end CS1 and charge and discharge electric-examination
The current potential for surveying signal input part CS is identical；When the current potential of charge and discharge electro-detection signal input part CS be negative and absolute value be greater than third
When the sum of NMOS transistor N9, the 4th PMOS transistor P11 and threshold value absolute value of the 5th PMOS transistor P12, the 3rd NMOS
Transistor N9, the 4th PMOS transistor P11, the 5th PMOS transistor P12 are in the conductive state, have electric current to flow through in resistance R6,
Generate the positive differential pressure δ V between pressure resistance protective module output end CS1 and charge and discharge electro-detection signal input part CS.
5. logic control circuit according to claim 1, which is characterized in that in the locking of charge control current potential and current potential translation
In module, when 0V battery does not access charger, the current potential of power supply positive input terminal VDD is 0V, charge and discharge power detection signal inputs
It holds CS and the current potential of pressure-resistant protective module output end CS1 is 0V, the current potential of the reversed phase signal COUTB of charging control signal is 0V,
First PMOS transistor P8, the second PMOS transistor P9, third PMOS transistor P10, the first NMOS transistor N7, which are in, to be cut
Only state, the gate control terminal OC of charge control transistor are 0V, and gate control terminal OC and charge and discharge power detection signal are defeated
Entering to hold pressure difference between CS is 0V.
6. logic control circuit according to claim 1, which is characterized in that in the locking of charge control current potential and current potential translation
In module, when the starting voltage that 0V battery accesses charger and charger is greater than charging nominal voltage VOCHWhen, power supply negative input end
Pressure difference between sub- VSS and pressure-resistant protective module output end CS1 is greater than the cut-in voltage of the first NMOS transistor N7, the first NMOS
Transistor N7 conducting, the first PMOS transistor P8 are equal to resistance to still in off state, the grid potential of the second PMOS transistor P9
The current potential of protective module output end CS1 is pressed, the second PMOS transistor P9 begins to turn on, and third PMOS transistor P10 is still in cutting
Only state, the second PMOS transistor P9 are in linear zone, and the current potential of gate control terminal OC is equal to power supply positive input terminal VDD's
Current potential, i.e. charge control are fixed on the voltage of power supply positive input terminal VDD with the voltage of the gate control terminal OC of transistor,
The source voltage terminal of charge control transistor is equal to the voltage of charge and discharge electro-detection signal input part CS at this time.
7. logic control circuit according to claim 1, which is characterized in that in the locking of charge control current potential and current potential translation
In module, meet the first PMOS transistor P8, third when the voltage that charging proceeds to power supply positive input terminal VDD gradually rises
When PMOS transistor P10 is connected, the grid potential of the second PMOS transistor P9 is gradually risen to the electricity of power supply positive input terminal VDD
Position, the second PMOS transistor P9 cut-off, the level of gate control terminal OC is determined by the signal COUTB at this time.
8. a kind of battery protection chip, which is characterized in that the battery protection chip includes the claims 1-7 any described
For 0V battery charging logic control circuit.
9. a kind of battery protecting circuit, which is characterized in that the battery protecting circuit includes battery described in the claims 8
Protect chip and charge control transistor and control of discharge transistor.
10. battery protecting circuit according to claim 9, which is characterized in that the grid of the charge control transistor
It is connected with the gate control terminal OC of logic control circuit in the battery protection chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811178661.8A CN109066923A (en) | 2018-10-10 | 2018-10-10 | Logic control circuit, battery protection chip and circuit for the charging of 0V battery |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811178661.8A CN109066923A (en) | 2018-10-10 | 2018-10-10 | Logic control circuit, battery protection chip and circuit for the charging of 0V battery |
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| Publication Number | Publication Date |
|---|---|
| CN109066923A true CN109066923A (en) | 2018-12-21 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811178661.8A Withdrawn CN109066923A (en) | 2018-10-10 | 2018-10-10 | Logic control circuit, battery protection chip and circuit for the charging of 0V battery |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110048476A (en) * | 2019-04-02 | 2019-07-23 | 深圳市稳先微电子有限公司 | A kind of battery protection driving circuit and battery protection drive system |
| CN113258641A (en) * | 2021-05-26 | 2021-08-13 | 江苏长晶科技有限公司 | Battery 0V charge forbidding circuit for reducing high-voltage thick gate oxide MOS (metal oxide semiconductor) transistor |
| CN113381485A (en) * | 2020-12-09 | 2021-09-10 | 上海芯跳科技有限公司 | Charge-discharge control circuit with 0V battery charging function |
| TWI821240B (en) * | 2019-01-23 | 2023-11-11 | 南韓商Ｌｇ新能源股份有限公司 | Battery device and control method thereof |
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2018
- 2018-10-10 CN CN201811178661.8A patent/CN109066923A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI821240B (en) * | 2019-01-23 | 2023-11-11 | 南韓商Ｌｇ新能源股份有限公司 | Battery device and control method thereof |
| CN110048476A (en) * | 2019-04-02 | 2019-07-23 | 深圳市稳先微电子有限公司 | A kind of battery protection driving circuit and battery protection drive system |
| CN110048476B (en) * | 2019-04-02 | 2023-05-16 | 西安稳先半导体科技有限责任公司 | Battery protection driving circuit and battery protection driving system |
| CN113381485A (en) * | 2020-12-09 | 2021-09-10 | 上海芯跳科技有限公司 | Charge-discharge control circuit with 0V battery charging function |
| CN113258641A (en) * | 2021-05-26 | 2021-08-13 | 江苏长晶科技有限公司 | Battery 0V charge forbidding circuit for reducing high-voltage thick gate oxide MOS (metal oxide semiconductor) transistor |
| CN113258641B (en) * | 2021-05-26 | 2021-10-22 | 江苏长晶科技有限公司 | Battery 0V charge forbidding circuit for reducing high-voltage thick gate oxide MOS (metal oxide semiconductor) transistor |
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Address after: 611, North building, sensor network technology research center, Southeast University, 99 Linghu Avenue, Xinwu District, Wuxi City, Jiangsu Province, 214135 Applicant after: Dongke semiconductor Wuxi Co.,Ltd. Address before: 611, North building, sensor network technology research center, Southeast University, 99 Linghu Avenue, Xinwu District, Wuxi City, Jiangsu Province, 214135 Applicant before: ANHUI DONGKE SEMICONDUCTOR WUXI Co.,Ltd. |
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Effective date of registration: 20211013 Address after: 243071 101-401, building 38, digital Silicon Valley Industrial Park, 999 Yinhuang East Road, Ma'anshan economic and Technological Development Zone, Ma'anshan City, Anhui Province Applicant after: Dongke semiconductor (Anhui) Co.,Ltd. Address before: 611, North building, sensor network technology research center, Southeast University, 99 Linghu Avenue, Xinwu District, Wuxi City, Jiangsu Province, 214135 Applicant before: Dongke semiconductor Wuxi Co.,Ltd. |
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Application publication date: 20181221 |