CN113258641B

CN113258641B - Battery 0V charge forbidding circuit for reducing high-voltage thick gate oxide MOS (metal oxide semiconductor) transistor

Info

Publication number: CN113258641B
Application number: CN202110574779.8A
Authority: CN
Inventors: 杨国江; 王海波; 李宇
Original assignee: Jiangsu Changjing Technology Co ltd
Current assignee: Jiangsu Changjing Technology Co.,Ltd.
Priority date: 2021-05-26
Filing date: 2021-05-26
Publication date: 2021-10-22
Anticipated expiration: 2041-05-26
Also published as: CN113258641A

Abstract

The invention discloses a battery 0V charge prohibiting circuit for reducing high-voltage thick-gate oxide MOS (metal oxide semiconductor) tubes, which is characterized in that on the basis of a 0V charge prohibiting circuit comprising a voltage sampling circuit, a level shift circuit and an output control circuit in the prior art, a voltage clamping circuit comprising diodes and resistors is additionally arranged, the output control circuit is improved, and through the combined action of the voltage clamping circuit and the improved output control circuit, the 0V charge prohibiting circuit can normally work only by using a common high-voltage thick-gate oxide high-threshold MOS tube process, thereby skillfully solving the problem that the prior art has strict requirements on process parameters.

Description

Battery 0V charge forbidding circuit for reducing high-voltage thick gate oxide MOS (metal oxide semiconductor) transistor

Technical Field

The invention relates to charging protection of a lithium battery, in particular to a battery 0V charge forbidding circuit for reducing a high-voltage thick gate oxide MOS (metal oxide semiconductor) transistor.

Background

As lithium batteries are widely used in social life, lithium battery protection chips designed to prevent abnormal charging and discharging of lithium batteries are also very important. When the battery voltage is too low and is close to 0V due to over-discharge of the lithium batteries, some lithium batteries can be designed to be charged with 0V in order to avoid direct scrapping of the batteries after over-discharge, but the charging of the 0V lithium batteries may have certain risks, and the lithium battery system with higher safety requirements can adopt a more severe 0V charge prohibiting design.

Fig. 2 is a circuit of a lithium battery charging system in the prior art, a 0V charge-prohibiting circuit is a part of a chip of the battery protection circuit in fig. 2, CO is a charge control terminal, NM2 is a charge control MOS transistor controlled by the CO terminal, DO is a discharge control terminal, NM1 is a discharge control MOS transistor controlled by the DO terminal, VM is a low potential of the CO control terminal (i.e., the lowest voltage range of CO can reach VM) and is also a high voltage terminal of a sampling control terminal and a negative voltage, a VM terminal sampling signal determines whether a charging and discharging current of the system is normal, EB + is a positive terminal of a charger, and EB-is a negative terminal of the charger.

Fig. 1 is a 0V disable charging protection circuit of the prior art, which is composed of a voltage sampling circuit (Part 1), a level shifting circuit (Part 2) and an output control circuit (Part 3). The NMOS transistors N1, N2, N3 and N4 and the PMOS transistors P4 and P5 are low-threshold high-voltage thick-gate-oxide MOS transistors, and the PMOS transistors P1, P2 and P3 are low-threshold high-voltage thin-gate-oxide MOS transistors. The level shift circuit (Part 2) is used for converting the low-voltage level output by a low-voltage digital circuit in the front stage of the level shift circuit (Part 2) in the battery protection circuit into a high-voltage signal L2 to drive inverters P5 and N4 in the output control circuit (Part 3). The prior art battery protection circuit of fig. 2 includes, in addition to the 0V charge-inhibiting circuit, a discharge detection comparator series (including an over-discharge voltage detection comparator, a discharge overcurrent detection comparator, and a discharge load short circuit detection comparator), a charge detection comparator series (including an over-charge voltage detection comparator and a charge overcurrent detection comparator), a voltage reference circuit, a delay circuit, and a low voltage digital circuit. The charge detection comparator series samples VDD voltage and VM voltage and compares the VDD voltage and the VM voltage with reference voltage to judge whether the battery charging state is normal or not, an output signal of the comparator passes through a delay circuit and an internal low-voltage digital circuit, a front-stage low-voltage output signal of the low-voltage digital circuit is transmitted to a level shift circuit, a high-voltage output signal L2 after level shift passes through a phase inverter P5 and an N4 to control a CO end, finally an external power tube NM2 is controlled, when the charge detection comparator series detects that the charge is normal, the NM2 is controlled to be conducted to enable the system to be charged, and when the charge detection comparator series detects that the charge is abnormal, the NM2 is controlled to be cut off to disable the system to be charged. The discharging detection comparator series samples VDD voltage and VM voltage, compares the VDD voltage and the VM voltage with reference voltage to judge whether the discharging state of the battery is normal or not, an output signal of the comparator passes through a delay circuit and a digital circuit, controls an external power tube NM1 through a DO end, controls an NM1 to conduct a system to allow charging when the charging is detected to be normal, and controls an NM1 to cut off the system to prohibit charging when the charging is detected to be abnormal. The voltage difference between VDD and VSS is the battery voltage, and the gate-source voltage of PMOS transistor P1 is also equal to the battery voltage. When the battery voltage is low to be close to 0V, the grid-source voltage of P1 is lower than the threshold value thereof, P1 is cut off, and the system is in a 0V charge inhibition state. When the charger is externally connected (fig. 2), the voltage difference between VDD and VM is the output voltage of the charger, and the gate-source voltage of the NMOS transistor N1 is the voltage difference between VSS and VM. According to the working principle of the lithium battery charging chip, when no current flows out of the charging chip, the charging chip outputs high voltage, namely high voltage is generated between VDD and VM, the NMOS tube N1 is conducted, the grid L1 of the PMOS tube P4 is pulled down, the P4 is conducted, the L2 of the driving output tube is pulled up, and finally the CO end is pulled down to close the externally-connected NMOS tube NM2 to forbid charging of the battery. When the charger is just connected to the CO end and the CO end is an abnormal high potential, the NMOS tube NM2 outside the CO end in fig. 2 is turned on, the charging chip charges the lithium battery, at this time, since the lithium battery protection chip is in an overdischarge protection state and the external NMOS tube NM1 at the DO end is turned off, a current charges the battery through the body diode of NM1, the gate-source voltage of N1 is the body diode voltage of NM1, and the circuit requires that the gate of N1 can withstand a high voltage and the threshold value of the gate is close to the body diode voltage of the NMOS, namely about 0.65V. Therefore, the N1 tube can be conducted to pull up the CO finally, and the external NMOS tube NM2 is turned off, namely even if the initial state of the CO is high potential just after the charger is connected, the CO can be pulled down through the cooperation of N1, P4 and N4, and the charging prohibition function is ensured to be normal. When the battery voltage is higher than the 0V charge inhibition release voltage, P1 is turned on to pull L1 high, and the 0V charge inhibition control function is not operated.

In the prior art, a common design also adopts a combination of a high-voltage thick gate oxide PMOS transistor P5 and a high-voltage thick gate oxide NMOS transistor N4 in FIG. 1 to control the CO end of output, but the problem of high threshold of a high-voltage thick gate oxide MOS in a common process is difficult to solve, so that the circuit shown in FIG. 3 is derived, namely, another output control circuit structure of the existing 0V charging-allowed or 0V charging-forbidden circuit. However, the circuit abandons a high-voltage thick gate oxide NMOS pull-down tube, and only adopts the resistor R10 to pull down, so that two major disadvantages are caused, if the value of the selected resistor R10 is too small, the static power consumption of the system is large, and if the value of the selected resistor R10 is large, the CO end is pulled down too slowly when the protection needs to be started. The improvement sacrifices the system performance in order to solve the problem of high threshold of the high-voltage thick gate oxide MOS, and has certain limitation.

In order to enable a high-voltage end VM to bear the high voltage of a charger and the external abnormal conditions, the traditional circuit design needs to use more high-voltage thick gate oxide NMOS and PMOS tubes, a 0V charging forbidding circuit requires that a system can normally work when the voltage of a battery is close to 0V, and an uncertain state cannot exist, even if the charging state can be rapidly released in a short time at the moment of just accessing the charger, the charging can be certainly forbidden, the threshold value needs to be as low as about 0.65V when the grid electrode of the high-voltage thick gate oxide tube can resist the high voltage on the circuit, so that high requirements are provided for the process, and many processes are difficult to meet the requirements.

Disclosure of Invention

The invention aims to provide a solution to the problems that the traditional 0V charge inhibition control circuit has high requirements on process parameters, a grid of a high-voltage MOS (metal oxide semiconductor) tube needs to be resistant to high voltage, and the threshold value of the traditional 0V charge inhibition control circuit needs to be relatively low.

In order to achieve the purpose, the technical scheme of the invention is as follows: a battery 0V charge forbidding circuit for reducing high-voltage thick gate oxide MOS (metal oxide semiconductor) tubes is arranged in a battery charge protection circuit chip, wherein the battery charge protection circuit chip comprises a port VDD connected with the positive electrode of a lithium battery, a port VSS connected with the negative electrode of the lithium battery, a discharge control port DO connected with an externally-connected discharge NMOS tube, a charge control port CO connected with the externally-connected charge NMOS tube and a sampling control port for judging whether charge and discharge currents are normal or not, and the sampling control port is also a high-voltage end VM;

the 0V charge-prohibiting circuit provided with the high-voltage thick gate oxide MOS tube comprises a voltage sampling circuit, a level shift circuit and an output control circuit;

the voltage sampling circuit comprises a PMOS tube P1, an NMOS tube N1 and a resistor R1, wherein the source electrode of the PMOS tube P1 is connected with a port VDD of the lithium battery charging protection circuit chip, the grid electrode of the PMOS tube P1 is interconnected with the grid electrode of the NMOS tube N1 and is connected with a port VSS of the lithium battery charging protection circuit chip, the drain electrode of the PMOS tube P1 is connected with one end of the resistor R1 and serves as the output end of the voltage sampling circuit, the other end of the resistor R1 is connected with the drain electrode of the NMOS tube N1, and the source electrode of the NMOS tube N1 is connected with a high-voltage end VM of the lithium battery charging protection circuit chip; the NMOS transistor N1 is a high-voltage thick-gate oxide MOS transistor, and the PMOS transistor P1 is a high-voltage thin-gate oxide MOS transistor;

the level shift circuit comprises PMOS tubes P2 and P3, NMOS tubes N2 and N3, resistors R2 and R3 and an inverter inv 1; the source electrodes of the PMOS tube P2 and the PMOS tube P3 are connected with a port VDD of the lithium battery charging protection circuit chip, the grid electrode of the PMOS tube P2 is connected with the input end of the inverter inv1 and a low-voltage level signal output by a low-voltage digital circuit positioned at the front stage of the level shift circuit, the output end of the inverter inv1 is connected with the grid electrode of the PMOS tube P3, the drain electrode of the PMOS tube P2 is connected with one end of a resistor R2 and the grid electrode of an NMOS tube N3, the drain electrode of the PMOS tube P3 is connected with one end of the resistor R3 and the grid electrode of the NMOS tube N2 and serves as the output end of the level shift circuit, and the source electrode of the NMOS tube N2 and the source electrode of the NMOS tube N3 are connected with a high-voltage end VM of the lithium battery charging protection circuit chip; the NMOS transistor N2 and the NMOS transistor N3 are both low-threshold high-voltage thick-gate oxide MOS transistors, and the PMOS transistor P2 and the PMOS transistor P3 are both low-threshold high-voltage thin-gate oxide MOS transistors;

the output control circuit comprises PMOS tubes P4 and P5 and an NMOS tube N4, the sources of the PMOS tubes P4 and P5 are both connected with a port VDD of the lithium battery charging protection circuit chip, the grid of the PMOS tube P4 is connected with the output end of the voltage sampling circuit, the grid of the PMOS tube P5 is interconnected with the grid of the NMOS tube N4 and is connected with the drain of the PMOS tube P4 and the output end of the level shift circuit, the drain of the PMOS tube P5 is connected with the drain of the NMOS tube N4 and serves as the output end of the lithium battery 0V charge prohibiting protection circuit, the output end of the lithium battery 0V charge prohibiting protection circuit is connected with a charging control port CO of the lithium battery charging protection circuit chip, and the source of the NMOS tube N4 is connected with a high-voltage end VM of the lithium battery charging protection circuit chip; the NMOS transistor N4 and the PMOS transistors P4 and P5 are low-threshold high-voltage thick gate oxide MOS transistors;

the method is characterized in that: a voltage clamping circuit comprising a diode and a resistor is additionally arranged and an output control circuit is improved, wherein the voltage clamping circuit is used for clamping a high-voltage end VM to a voltage VM1, and VM1 is less than or equal to VM; the improved output control circuit is additionally provided with NMOS tubes N9, N10 and N12, a low-threshold high-voltage thin gate oxide PMOS tube P4 'is used for replacing a low-threshold high-voltage thick gate oxide PMOS tube P4, and the connection relation of the PMOS tube P4' is the same as that of a PMOS tube P4; the drain electrode of an NMOS tube N9 is connected with the output end of the level shift circuit, the grid electrode and the source electrode of an NMOS tube N9 are connected with each other and connected with the drain electrode of an NMOS tube N10, the grid electrode of the NMOS tube N10 is connected with the output end of an inverter inv1 in the level shift circuit, the source electrode of an NMOS tube N10 is connected with a clamping voltage VM1 output by the voltage clamping circuit, the NMOS tube N9 and the NMOS tube N12 are both high-voltage depletion type MOS tubes, and the NMOS tube N10 is a high-voltage thin-gate oxide MOS tube; under the combined action of the voltage clamping circuit and the improved output control circuit, the gate-source voltages of an NMOS tube N1 and a PMOS tube P1 in the voltage sampling circuit and the gate-source voltages of a PMOS tube P4 and an NMOS tube N10 in the output control circuit are clamped at low voltage, a low-threshold low-voltage thin gate oxide tube NMOS tube N1 ' is used for replacing a low-threshold high-voltage thick gate oxide NMOS tube N1, and compared with the connection relation of the NMOS tube N1, the connection relation of the NMOS tube N1 ' is the same as that of the NMOS tube N1 except that the source of the NMOS tube N1 ' is changed into a clamping voltage VM1 output by the voltage clamping circuit.

The voltage clamping circuit comprises a Zener diode D1 and a resistor R4, the cathode of the Zener diode D1 is connected with a VDD port, the anode of the Zener diode D1 is connected with one end of a resistor R4 and serves as the output end of a clamping voltage VM1, and the other end of the resistor R4 is the high-voltage end VM of a lithium battery charging protection circuit chip.

The voltage clamping circuit also comprises diodes D2 and D3 and a resistor R6 which are connected in series, wherein the anode of the diode D2 is connected with a VSS (voltage source), the cathode of the diode D2 is connected with the anode of the diode D3, the cathode of the diode D3 is connected with one end of the resistor R6 and serves as an output end of the clamping voltage VM1, and the other end of the resistor R6 serves as a high-voltage end VM of the lithium battery charging protection circuit chip.

The diodes D2 and D3 can be replaced by NPN triodes, PNP triodes, NMOS tubes or PMOS tubes in a diode connection mode, the number of the series diodes is determined according to the withstand voltage condition of the MOS tubes in the voltage sampling circuit to be protected, 2-10 diodes are selected, the number of the series diodes is increased, and then the clamping voltage VM1 is reduced.

The voltage clamp circuit may also include diodes D4 and D5, NMOS transistors N5, N6, N7 and N8, and a resistor R5; the drain of the NMOS transistor N5 and the drain of the NMOS transistor N6 are interconnected and connected with VDD, the source of the NMOS transistor N5 is shorted with the gate and is connected with the gate of the NMOS transistor N6 and the anode of the diode D4, the cathode of the diode D4 is connected with the anode of the diode D5, the cathode of the diode D5 is connected with VSS, the source of the NMOS transistor N6 is connected with the gate and the drain of the NMOS transistor N7, the source of the NMOS transistor N7 is connected with the gate and the drain of the NMOS transistor N8, the source of the NMOS transistor N8 is connected with one end of a resistor R5 and serves as an output end of a clamping voltage VM1, the other end of the resistor R5 serves as a high-voltage end VM, and the drain of the NMOS transistor N5 is used as a drain.

The diodes D4 and D5 can be replaced by NPN triodes, PNP triodes, NMOS tubes or PMOS tubes in a diode connection mode, the NMOS tubes N7 and N8 are replaced by NPN triodes, PNP triodes, NMOS tubes or PMOS tubes in a diode or diode connection mode, the number of the diodes D4 and D5 and the number of the NMOS tubes N7 and N8 in series are determined according to the withstand voltage condition of the MOS tubes in the voltage sampling circuit, 1-20 diodes are selected, the number of the diodes D4 and D5 in series is increased, the clamping voltage of the VM1 is increased, the number of the NMOS tubes N7 and N8 is increased, and the clamping voltage of the VM1 is reduced.

The drain is notwithstanding that N5 may be replaced by a resistor above 1M Ω or a current mirror drawn by a current bias.

High voltage dissipation in the output control circuit although N9 and N12 may be replaced with resistors above 1M Ω.

The source of the high voltage thin gate oxide NMOS transistor N10 may be connected to VSS instead of the clamp voltage VM 1.

The invention has the advantages and obvious effects that: the invention provides an improved output control circuit by adding a voltage clamping circuit and adding a part of MOS (metal oxide semiconductor) transistors, so that a 0V forbidden charging circuit can normally work only by using a common high-voltage thick-gate oxide high-threshold MOS transistor process. The difficult problem that the prior art has strict requirements on process parameters is ingeniously solved. The threshold value of the high-voltage thick gate oxygen tube required by the traditional framework is as low as about 0.65V, and the high-voltage thick gate oxygen tube adopting the new framework can work normally even if the threshold value is increased to 2-2.5V.

Drawings

Fig. 1 is a 0V inhibit charge circuit of the prior art using a low threshold high voltage thick gate oxide MOS process.

Fig. 2 is a prior art battery protection circuitry circuit.

Fig. 3 is another form of the output control circuit of fig. 1.

Fig. 4 is a 0V inhibit charge circuit of the present invention.

Fig. 5 is another implementation of the clamping circuit of fig. 4.

Fig. 6 is yet another implementation of the clamping circuit of fig. 4.

Detailed Description

Referring to fig. 4, the 0V charge-inhibiting circuit for a battery of the present invention, which reduces the number of high-voltage thick-gate oxide MOS transistors, is an improvement of the prior art fig. 1, and adds a voltage clamp circuit including a diode and a resistor, and improves an output control circuit. The voltage clamping circuit is used for clamping the high-voltage end VM to a voltage VM1, and VM1 is not less than VM; the improved output control circuit is additionally provided with NMOS tubes N9, N10 and N12, a low-threshold high-voltage thin gate oxygen PMOS tube P4 'can be used for replacing a low-threshold high-voltage thick gate oxygen PMOS tube P4 in the figure 1, and the connection relation of the PMOS tube P4' is the same as that of a PMOS tube P4 in the figure 1. The drain electrode of an NMOS tube N9 is connected with the output end of the level shift circuit, the grid electrode and the source electrode of an NMOS tube N9 are connected with each other and connected with the drain electrode of an NMOS tube N10, the grid electrode of the NMOS tube N10 is connected with the output end of an inverter inv1 in the level shift circuit, the source electrode of an NMOS tube N10 is connected with a clamping voltage VM1 output by the voltage clamping circuit, the NMOS tube N9 and the NMOS tube N12 are both high-voltage depletion type MOS tubes, and the NMOS tube N10 is a high-voltage thin-gate oxide MOS tube; under the combined action of the voltage clamping circuit and the improved output control circuit, the gate-source voltages of an NMOS tube N1 and a PMOS tube P1 in the voltage sampling circuit and a PMOS tube P4 and an NMOS tube N10 in the output control circuit are clamped at low voltage, so that a low-threshold low-voltage thin gate oxide tube NMOS tube N1 ' can be used for replacing a low-threshold high-voltage thick gate oxide NMOS tube N1 in a graph 1, and compared with the connection relation of the NMOS tube N1 in the graph 1, the connection relation of the NMOS tube N1 ' is the same as that of the NMOS tube N1 except that the source of the NMOS tube N1 ' is changed into a clamping voltage VM1 output by the voltage clamping circuit.

The voltage clamp circuit in fig. 4 adopts a form of clamping by connecting a zener diode D1 and a resistor R4 in series, wherein the cathode of the zener diode D1 is connected to the VDD, the anode of the zener diode D1 is connected to one end of the resistor R4 and serves as the output end of the clamp voltage VM1, that is, the voltage VM1 after clamping at the high-voltage end VM, and the other end of the resistor R4 is the high-voltage end VM of the lithium battery charging protection circuit chip. The source of the NMOS transistors N10 and N1' are connected to the clamp voltage VM 1. When the voltage difference between VM and VDD is smaller than the Zener tube breakdown voltage, the Zener tube is cut off, no current flows through the resistor R4, and the VM voltage is equal to the VM1 voltage. When a large negative voltage occurs to VM and the voltage difference between VM and VDD is larger than the breakdown voltage of the Zener diode, the Zener diode is reversely broken down, current flows through a resistor R4, so that the voltage difference between VM1 and VDD is kept at the breakdown voltage of the Zener diode, the gate-source withstand voltage and the source-drain withstand voltage of a low-voltage MOS transistor are generally higher than the breakdown voltage of the Zener diode, and therefore the high-voltage thick-gate oxygen NMOS transistor N1 and the PMOS transistor P4 in the traditional circuit can be replaced by a low-voltage NMOS transistor N1 'and a high-voltage thin-gate oxygen PMOS transistor P4' which have lower thresholds by means of clamping of VM 1.

The high-voltage thick gate oxide NMOS transistors N2, N3, N1' and the high-voltage thick gate oxide PMOS transistor P5 in the graph of FIG. 4 can work normally with the threshold value of 2V-2.5V. When the battery voltage is lower than 0V forbidden charging release voltage (generally set to be 1V-2V), the low-voltage tube N1 'with a lower threshold value can be conducted under the action of the charger voltage or the body diode voltage of NM1 after the charger is connected, so that L11 is pulled down, and then the high-voltage thick gate oxide PMOS tube P4' is conducted to pull up L21. At this time, if the gate-source voltage of N11 is higher than the threshold voltage, N11 turns on, pulling CO low by means of N11, and if N11 does not turn on, pulling CO low by means of high voltage consumption despite N12, ensuring that charging can be inhibited. When the battery voltage VDD is higher than the 0V charge-inhibition release voltage, P1 turns on L11 and is pulled high, the internal digital logic circuit controls the output L31 of the inverter inv1 to be at high level, since N10 is a high-voltage thin gate oxide transistor with a low threshold, it can be easily turned on, and the gate-source voltage of the high-voltage thick gate oxide transistor PMOS transistor P5 is the voltage difference between VDD and VM 1. Therefore, as long as the threshold voltage of P5 is higher than 0V forbidden charge release voltage plus 0.65V, P5 can be smoothly conducted when VDD is higher than 0V forbidden charge release voltage, and CO pulls up the battery for normal charging.

Fig. 5 is another implementation of the clamping circuit of fig. 4, which uses two diodes or a diode-connected transistor or MOS transistor in series with a resistor to clamp VM 1. When the VM voltage is two diode conduction drops below VSS, the diode conduction current flows through resistor R5, VM1 is clamped at two diode conduction drops below VSS, the diode is non-conducting when VM is above this voltage, and the VM1 voltage is equal to VM. The number of the diodes can be flexibly set to be 1 to 10 according to the withstand voltage range of the low-voltage tube of the corresponding process.

FIG. 6 is yet another implementation of the clamp circuit of FIG. 4, using diodes D4, D5 and diode-connected N7, N8 to provide voltage clamping despite providing a steady current, the voltage of VM1 being the same as VM when VM is above or just slightly below VSS, N6, N7, N8 are not conducting; when VM is lower than VSS more than N6, N7, N8 are turned on, current flows through resistor R5 so that VM1 is clamped at a voltage slightly lower than VSS, ensuring that the MOS transistor connected to VM1 is not broken down. D4, D5, N7 and N8 can be replaced by diodes or diode-connected triodes or MOS tubes, and the number of the series diodes or diode-connected triodes MOS tubes can be adjusted from 1 to 20 according to the withstand voltage condition of the corresponding process.

The three different embodiments of the voltage clamp circuits of fig. 4, 5, and 6 clamp VM1 at a lower voltage, so that the MOS transistor connected to VM1 can be used as a low voltage device. The structure of fig. 4 is the simplest but requires a process to support the zener device, and is only suitable for a single lithium battery protection system with a low VDD because VDD is clamped. The circuit structure of fig. 5 is relatively simple, because of clamping on VSS, the VDD voltage is not limited, the applicable VDD voltage range is wider, both single-section and multi-section lithium battery protection systems are applicable, the circuit structure of fig. 6 is more complex, although VDD is connected, the circuit structure is actually similar to the structure of fig. 5, the circuit structure is also clamping on VSS, the circuit structure is applicable to single-section and multi-section lithium battery protection systems, and the range of the clamped voltage VM1 is more flexible.

Claims

1. A battery 0V charge forbidding circuit for reducing high-voltage thick gate oxide MOS (metal oxide semiconductor) tubes is arranged in a battery charge protection circuit chip, wherein the battery charge protection circuit chip comprises a port VDD connected with the positive electrode of a lithium battery, a port VSS connected with the negative electrode of the lithium battery, a discharge control port DO connected with an externally-connected discharge NMOS tube, a charge control port CO connected with the externally-connected charge NMOS tube and a sampling control port for judging whether charge and discharge currents are normal or not, and the sampling control port is also a high-voltage end VM;

2. The circuit of claim 1 for reducing battery 0V inhibit charging of high voltage thick gate oxide MOS transistor, wherein: the voltage clamping circuit comprises a Zener diode D1 and a resistor R4, the cathode of the Zener diode D1 is connected with a VDD port, the anode of the Zener diode D1 is connected with one end of a resistor R4 and serves as the output end of a clamping voltage VM1, and the other end of the resistor R4 is the high-voltage end VM of a lithium battery charging protection circuit chip.

3. The circuit of claim 1 for reducing battery 0V inhibit charging of high voltage thick gate oxide MOS transistor, wherein: the voltage clamping circuit comprises diodes D2 and D3 and a resistor R6 which are connected in series, the anode of the diode D2 is connected with a VSS (voltage source), the cathode of the diode D2 is connected with the anode of the diode D3, the cathode of the diode D3 is connected with one end of a resistor R6 and serves as an output end of a clamping voltage VM1, and the other end of the resistor R6 serves as a high-voltage end VM of a lithium battery charging protection circuit chip.

4. The circuit of claim 3 for reducing battery 0V inhibit charging of high voltage thick gate oxide MOS transistor, wherein: the diodes D2 and D3 are replaced by NPN triodes, PNP triodes, NMOS tubes or PMOS tubes in a diode connection mode, the number of the series diodes is determined according to the withstand voltage condition of the MOS tubes in the voltage sampling circuit to be protected, 2-10 diodes are selected, the number of the series diodes is increased, and then the clamping voltage VM1 is reduced.

5. The circuit of claim 1 for reducing battery 0V inhibit charging of high voltage thick gate oxide MOS transistor, wherein: the voltage clamp circuit comprises diodes D4 and D5, NMOS transistors N5, N6, N7 and N8 and a resistor R5; the drain of the NMOS transistor N5 and the drain of the NMOS transistor N6 are interconnected and connected with VDD, the source of the NMOS transistor N5 is in short circuit with the gate and is connected with the gate of the NMOS transistor N6 and the anode of the diode D4, the cathode of the diode D4 is connected with the anode of the diode D5, the cathode of the diode D5 is connected with VSS, the source of the NMOS transistor N6 is connected with the gate and the drain of the NMOS transistor N7, the source of the NMOS transistor N7 is connected with the gate and the drain of the NMOS transistor N8, the source of the NMOS transistor N8 is connected with one end of a resistor R5 and serves as an output end of a clamping voltage VM1, the other end of the resistor R5 serves as a high-voltage end VM, and the drain of the NMOS transistor N5 is dissipative.

6. The circuit of claim 5 for reducing battery 0V inhibit charging of high voltage thick gate oxide MOS transistor, wherein: the diodes D4 and D5 are replaced by NPN triodes, PNP triodes, NMOS tubes or PMOS tubes in a diode connection mode, the NMOS tubes N7 and N8 are replaced by NPN triodes, PNP triodes, NMOS tubes or PMOS tubes in a diode connection mode, the number of the diodes D4 and D5 and the number of the NMOS tubes N7 and N8 in series are determined according to the withstand voltage condition of the MOS tubes in the voltage sampling circuit, 1-20 diodes are selected, the number of the diodes D4 and D5 in series is increased, the clamping voltage of the VM1 is increased, the number of the NMOS tubes N7 and N8 is increased, and the clamping voltage of the VM1 is reduced.

7. The circuit of claim 5 for reducing battery 0V inhibit charging of high voltage thick gate oxide MOS transistor, wherein: the drain is notwithstanding that N5 is replaced by a resistor above 1M Ω or a current mirror drawn by a current bias.

8. The circuit of claim 1 for reducing battery 0V inhibit charging of high voltage thick gate oxide MOS transistor, wherein: the high voltage dissipation in the output control circuit is despite the fact that N9 and N12 are replaced with resistors above 1M Ω.

9. The circuit of claim 1 for reducing battery 0V inhibit charging of high voltage thick gate oxide MOS transistor, wherein: the source electrode of the high-voltage thin gate oxide NMOS transistor N10 is connected with VSS.