CN109062306A - Threshold reference current generating circuit - Google Patents
Threshold reference current generating circuit Download PDFInfo
- Publication number
- CN109062306A CN109062306A CN201810984613.1A CN201810984613A CN109062306A CN 109062306 A CN109062306 A CN 109062306A CN 201810984613 A CN201810984613 A CN 201810984613A CN 109062306 A CN109062306 A CN 109062306A
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- China
- Prior art keywords
- nmos transistor
- transistor
- mirror current
- grid
- current source
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The invention discloses a kind of threshold reference current generating circuits, the substrate of one end of first~third mirror current source and the first PMOS transistor is connected with power voltage terminal VPWR, the other end of first mirror current source is connected with the grid of the source electrode of the first PMOS transistor and the first NMOS transistor, and the node of connection is denoted as VIN；The drain electrode of first NMOS transistor is connected with the other end of the second mirror current source, and source electrode is connected with the grid of one end of first resistor and the second NMOS transistor, and the node of connection is denoted as VRES；The other end of third mirror current source is connected with the grid of the drain electrode of the second NMOS transistor and the first PMOS transistor；The source electrode and Substrate ground of the drain electrode of first PMOS transistor, the substrate of the other end of first resistor and the first NMOS transistor and the second NMOS transistor.The present invention can reduce inverting amplifier transfer characteristic, with mains voltage variations.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of threshold reference current generating circuit.
Background technique
Threshold reference current generating circuit is widely used in analog circuit.
As shown in connection with fig. 1, amplify the threshold reference current generating circuit to form feedback based on the amplification of voltage positive and reverse phase
Structure is simple, does not need operational amplifier, and the device number needed is few.
Threshold reference electric current Ires=Vgsn2/RES, wherein Vgsn2 is the grid and source voltage of NMOS transistor NM2
Difference.
In Fig. 1, it further includes two PMOS transistor PM1 that IP1, IP2, which are the mirror current source that PMOS transistor is constituted,
PM2, two NMOS transistors NM1, NM2 and resistance RES.Wherein PMOS transistor PM2 and NMOS transistor NM2 shape
At inverting amplifier, PMOS transistor PM1 and NMOS transistor NM1 form non-inverting amplifier.
One end of mirror current source IP1, IP2 are connected with power voltage terminal VPWR, the other end of mirror current source IP1 with
The source electrode of PMOS transistor PM1 is connected with the grid of NMOS transistor NM1, and the node of connection is denoted as VIN.PMOS transistor
The grounded drain of PM1, substrate are connected with power voltage terminal VPWR.
The other end of mirror current source IP2 is connected with the drain electrode of NMOS transistor NM1, the source electrode of NMOS transistor NM1
It is connected with the grid of one end of resistance RES, the grid of PMOS transistor PM2 and NMOS transistor NM2, the node note of connection
For VRES.The other end of resistance RES and the Substrate ground of NMOS transistor NM1.The source electrode and substrate and electricity of PMOS transistor PM2
Source voltage end VPWR is connected, and drain electrode is connected with the grid of the drain electrode of NMOS transistor NM2 and PMOS transistor PM1.
The source electrode and Substrate ground of NMOS transistor NM2.
Circuit shown in Fig. 1 has the drawback that threshold reference electric current is linearly increased with the increase of supply voltage, variation
Greatly.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of threshold reference current generating circuits, can reduce threshold reference
Electric current with mains voltage variations amplitude.
In order to solve the above technical problems, threshold reference current generating circuit of the invention, by three mirror current sources, one
PMOS transistor, two NMOS transistors and a resistance composition；
The substrate of one end of first~third mirror current source and the first PMOS transistor is connected with power voltage terminal VPWR
It connecing, the other end of the first mirror current source is connected with the grid of the source electrode of the first PMOS transistor and the first NMOS transistor,
Its node connected is denoted as VIN；
The drain electrode of first NMOS transistor is connected with the other end of the second mirror current source, source electrode and first resistor
One end is connected with the grid of the second NMOS transistor, and the node of connection is denoted as VRES；
The other end of third mirror current source and the drain electrode of the second NMOS transistor and the grid phase of the first PMOS transistor
Connection；
The drain electrode of first PMOS transistor, the substrate of the other end of first resistor and the first NMOS transistor and second
The source electrode and Substrate ground of NMOS transistor.
Using threshold reference current generating circuit of the invention, the supply voltage characteristic of threshold reference electric current can be improved,
And then threshold reference current precision is improved, threshold reference electric current is effectively reduced with the amplitude of mains voltage variations.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is existing threshold reference current generating circuit schematic diagram；
Fig. 2 is improved one embodiment schematic diagram of threshold reference current generating circuit；
Fig. 3 is node VRES and VIN the burning voltage point schematic diagram in Fig. 2；
Fig. 4 is simulation result diagram.
Specific embodiment
It is shown in Figure 2, improved threshold reference current generating circuit, in the following embodiments by mirror current source
IP1~IP3, PMOS transistor PM1, NMOS transistor NM1, NM2 and a resistance RES composition.Comparing Fig. 1 and Fig. 2 can be with
Find out, improved threshold reference current generating circuit, be to change the PMOS transistor PM2 in Fig. 1 into mirror current source IP3,
Inverting amplifier is formed by PMOS transistor PM1 and mirror current source IP3, can reduce threshold reference electric current in this way with power supply electricity
The amplitude of buckling.
Improved threshold reference current generating circuit particular circuit configurations shown in Fig. 2 are:
One end of mirror current source IP1~IP3 is connected with power voltage terminal VPWR, the other end of mirror current source IP1
It is connected with the grid of the source electrode of PMOS transistor PM1 and NMOS transistor NM1, the node of connection is denoted as VIN.PMOS crystal
The grounded drain of pipe PM1, substrate are connected with power voltage terminal VPWR.
The other end of mirror current source IP2 is connected with the drain electrode of NMOS transistor NM1, the source electrode of NMOS transistor NM1
It is connected with the grid of one end of resistance RES and NMOS transistor NM2, the node of connection is denoted as VRES.Resistance RES's is another
The Substrate ground at end and NMOS transistor NM1.The other end of mirror current source IP3 and the drain electrode of NMOS transistor NM2 and PMOS
The grid of transistor PM1 is connected.The source electrode and Substrate ground of NMOS transistor NM2.
The course of work of foregoing circuit are as follows: node VIN and VRES form positive by NMOS transistor NM1 and resistance RES
Amplification, node VRES and VIN form reverse phase amplification by mirror current source IP3 and PMOS transistor PM1.Positive amplification and reverse phase
Amplification forms the burning voltage point 1 (as shown in connection with fig. 3) of node VRES and VIN.
The threshold reference electric current Ires=Vgsn2/RES that foregoing circuit generates.
Fig. 4 is simulation result, wherein 1 represents simulation result of the invention, 2, which represent existing threshold reference electric current, generates electricity
Road simulation result.As seen from the figure, using circuit of the invention, threshold reference electric current is non-with the amplitude that supply voltage increases variation
Often small, precision is high.And available circuit threshold reference electric current increases with supply voltage, linearly increases, threshold reference electric current is unstable
It is fixed, precision degree.
Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (4)
1. a kind of threshold reference current generating circuit, it is characterised in that: by three mirror current sources, PMOS transistor, two
A NMOS transistor and a resistance composition；
One end of first~third mirror current source is connected with power voltage terminal VPWR, the other end of the first mirror current source with
The grid of the source electrode of first PMOS transistor and the first NMOS transistor is connected, and the node of connection is denoted as VIN, the first PMOS
The grounded drain of transistor, substrate are connected with power voltage terminal VPWR；
The other end of second mirror current source is connected with the drain electrode of the first NMOS transistor, the source electrode of the first NMOS transistor with
One end of first resistor is connected with the grid of the second NMOS transistor, and the node of connection is denoted as VRES；First resistor it is another
The Substrate ground of one end and the first NMOS transistor；
The other end of third mirror current source is connected with the grid of the drain electrode of the second NMOS transistor and the first PMOS transistor,
The source electrode and Substrate ground of second NMOS transistor.
2. circuit as described in claim 1, it is characterised in that: the node VIN and VRES by the first NMOS transistor and
First resistor forms positive amplification, and the node VRES and VIN is formed by third mirror current source and the first PMOS transistor
Reverse phase amplification.
3. circuit as described in claim 1, it is characterised in that: positive amplification and reverse phase amplify to be formed node VRES and
The burning voltage point of VIN.
4. circuit as described in claim 1, it is characterised in that: threshold reference electric current Ires=Vgsn2/RES, wherein Vgsn2
Poor for the grid and source voltage of the second NMOS transistor, RES is first resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810984613.1A CN109062306B (en) | 2018-08-28 | 2018-08-28 | Threshold reference current generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810984613.1A CN109062306B (en) | 2018-08-28 | 2018-08-28 | Threshold reference current generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109062306A true CN109062306A (en) | 2018-12-21 |
| CN109062306B CN109062306B (en) | 2020-06-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810984613.1A Active CN109062306B (en) | 2018-08-28 | 2018-08-28 | Threshold reference current generating circuit |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1206864A (en) * | 1997-07-29 | 1999-02-03 | 株式会社东芝 | Reference voltage and current generating circuit |
| US6275075B1 (en) * | 1998-12-15 | 2001-08-14 | Hyundai Electronics Industries Co., Ltd. | Current comparator |
| US20080007243A1 (en) * | 2006-07-07 | 2008-01-10 | Akinori Matsumoto | Reference voltage generation circuit |
| US20080074173A1 (en) * | 2006-09-25 | 2008-03-27 | Avid Electronics Corp. | Current source circuit having a dual loop that is insensitive to supply voltage |
| US20100097047A1 (en) * | 2008-10-16 | 2010-04-22 | Freescale Semiconductor,Inc | Series regulator circuit |
| CN106155172A (en) * | 2015-03-31 | 2016-11-23 | 成都锐成芯微科技有限责任公司 | A kind of have the start-up circuit without overshoot characteristics and band-gap reference circuit |
| CN106484016A (en) * | 2015-08-24 | 2017-03-08 | 敦泰电子股份有限公司 | Voltage turnover type zero compensation circuit |
| CN206563916U (en) * | 2017-03-15 | 2017-10-17 | 深圳慧能泰半导体科技有限公司 | A kind of current source circuit, chip and electronic equipment |
| CN107831816A (en) * | 2017-09-29 | 2018-03-23 | 上海华虹宏力半导体制造有限公司 | Internal electric source generation circuit in reference current generating circuit |
-
2018
- 2018-08-28 CN CN201810984613.1A patent/CN109062306B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1206864A (en) * | 1997-07-29 | 1999-02-03 | 株式会社东芝 | Reference voltage and current generating circuit |
| US6275075B1 (en) * | 1998-12-15 | 2001-08-14 | Hyundai Electronics Industries Co., Ltd. | Current comparator |
| US20080007243A1 (en) * | 2006-07-07 | 2008-01-10 | Akinori Matsumoto | Reference voltage generation circuit |
| US20080074173A1 (en) * | 2006-09-25 | 2008-03-27 | Avid Electronics Corp. | Current source circuit having a dual loop that is insensitive to supply voltage |
| US20100097047A1 (en) * | 2008-10-16 | 2010-04-22 | Freescale Semiconductor,Inc | Series regulator circuit |
| CN106155172A (en) * | 2015-03-31 | 2016-11-23 | 成都锐成芯微科技有限责任公司 | A kind of have the start-up circuit without overshoot characteristics and band-gap reference circuit |
| CN106484016A (en) * | 2015-08-24 | 2017-03-08 | 敦泰电子股份有限公司 | Voltage turnover type zero compensation circuit |
| CN206563916U (en) * | 2017-03-15 | 2017-10-17 | 深圳慧能泰半导体科技有限公司 | A kind of current source circuit, chip and electronic equipment |
| CN107831816A (en) * | 2017-09-29 | 2018-03-23 | 上海华虹宏力半导体制造有限公司 | Internal electric source generation circuit in reference current generating circuit |
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|---|---|
| CN109062306B (en) | 2020-06-09 |
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