CN107132405B - Zero-crossing detection circuit for synchronous buck converter - Google Patents
Zero-crossing detection circuit for synchronous buck converter Download PDFInfo
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- CN107132405B CN107132405B CN201710517085.4A CN201710517085A CN107132405B CN 107132405 B CN107132405 B CN 107132405B CN 201710517085 A CN201710517085 A CN 201710517085A CN 107132405 B CN107132405 B CN 107132405B
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- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to the field of buck converters, in particular to a zero crossing detection circuit for a synchronous buck converter. The invention discloses a zero crossing detection circuit for a synchronous buck converter, which comprises a zero crossing comparator and a multiplier, wherein two input ends of the zero crossing comparator are respectively connected with an output end of the multiplier and a drain electrode of a synchronous tube of the synchronous buck converter, the output end of the zero crossing comparator is connected with an input end of a driving circuit of the synchronous buck converter, a first input end of the multiplier is connected with a voltage output end of the synchronous buck converter, and a second input end of the multiplier is connected with a positive temperature coefficient current source. The invention fully considers the deviation of the temperature and the set output voltage in the synchronous buck converter to the zero crossing detection, and improves the accuracy of the zero crossing detection.
Description
Technical Field
The invention belongs to the field of buck converters, and particularly relates to a zero-crossing detection circuit for a synchronous buck converter.
Background
In recent years, with the development of Chinese economy and the rising of the electronic industry, the rapid popularization of consumer electronic products, particularly portable electronic devices, makes power supply technology trend to have the characteristics of high power, high energy efficiency, high integration level and the like. Dc converters are widely used in power management systems due to their high efficiency.
Synchronous buck converters in dc converters have two modes of operation: a Connected Conduction Mode (CCM) and a Discontinuous Conduction Mode (DCM). In the discontinuous conduction mode, a zero-crossing detection circuit is needed to detect whether the inductance current crosses zero, and when the inductance current is detected to be zero, the synchronous tube is turned off, so that the power consumption is reduced to improve the efficiency.
Fig. 1 shows a zero-crossing detection circuit for a synchronous buck converter in the prior art, that is, a zero-crossing comparison circuit is arranged on the buck converter, and is mainly implemented by using a zero-crossing comparator a. The detection mode of the inductance L current is shown in fig. 2. IL in fig. 2 is the inductor L current, itrip is the zero crossing trigger value set by zero crossing comparator a, tdly is the delay of zero crossing comparator a. Considering the delay Tdly of the zero-crossing comparator a, since the inductor L current is continuing to decrease during the period of time that the zero-crossing comparator a delays, it is common to set Itrip to a value higher than il=0 by a certain range to cancel the detection deviation due to the zero-crossing comparator a delay.
Ideal for
It can be seen from equation (1) that the ideal Itrip is affected by the inductance value L, the output voltage Vout, the zero-crossing comparator a delay Tdly, which is the external output inductance, since Tdly is the comparator itself delay, L is the external output inductance, both of which are fixed. Therefore, the ideal value of offset voltage Vos introduced by the zero-crossing comparator should be
Vos＝Itrip*Ron
Ron is the on-resistance of the synchronous tube and is affected by temperature. The traditional zero crossing point detection is not compensated or a fixed offset voltage Vos is introduced into the zero crossing comparator to compensate, so that detection deviation caused by delay of the zero crossing comparator A cannot be accurately counteracted.
Disclosure of Invention
The invention aims to solve the problems and provide a zero-crossing detection circuit for a synchronous buck converter, which fully considers the deviation of temperature and set output voltage to zero-crossing detection in the synchronous buck converter and improves the accuracy of zero-crossing detection.
The invention discloses a zero crossing detection circuit for a synchronous buck converter, which comprises a zero crossing comparator and a multiplier, wherein two input ends of the zero crossing comparator are respectively connected with an output end of the multiplier and a drain electrode of a synchronous tube of the synchronous buck converter, the output end of the zero crossing comparator is connected with an input end of a driving circuit of the synchronous buck converter, a first input end of the multiplier is connected with a voltage output end of the synchronous buck converter, and a second input end of the multiplier is connected with a positive temperature coefficient current source.
Further, the multiplier comprises a PNP triode M2-M5, an NMOS tube M0-M1 and a resistor R0-R1, wherein the emitter of the PNP triode M2 is connected with a power supply VCC, the collector of the PNP triode M2 is connected with the drain of the NMOS tube M0, the source series resistor R0 of the NMOS tube M0 is grounded, the grid electrode of the NMOS tube M0 is connected with the voltage output end VOUT of the synchronous buck converter, the base of the PNP triode M2 and the emitter of the PNP triode M3 are connected with a positive temperature coefficient current source Iptat, the collector of the PNP triode M3 is grounded, the grid electrode of the NMOS tube M1 is connected with the collector of the PNP triode M2, the bases of the PNP triode M3 and the NMOS tube M4 and the source of the NMOS tube M1 are connected with a bias current source Itest, the drain of the NMOS tube M1 is connected with the power supply VCC, the emitter of the PNP triode M4 and the base of the PNP triode M5 are connected with a constant temperature coefficient current source Iconst, the PNP triode M4 is grounded, the base of the PNP triode M5 and the collector of the PNP triode M5 is connected with the collector of the drain of the NMOS tube M1, and the collector of the PNP triode M1 is connected with the collector of the drain of the NMOS tube.
Furthermore, the NMOS transistors M0-M1 are all enhanced NMOS transistors.
Further, the multiplier comprises an NPN triode M2, an NPN triode M3, a PNP triode M4, an NPN triode M5, an NMOS tube M0, a PMOS tube M1 and resistors R0-R1, wherein the emitter of the NPN triode M2 is grounded, the collector of the NPN triode M2 and the grid of the PMOS tube M1 are connected with the output end of the first current mirror, the source of the NMOS tube M0 is connected with the ground through a series resistor R0, the grid of the NMOS tube M0 is connected with the voltage output end VOUT of the synchronous buck converter, the drain of the NMOS tube M0 is connected with the input end of the first current mirror, the base of the NPN triode M2 and the emitter of the NPN triode M3 are connected with a positive temperature coefficient current source Iptat, the base of the NPN triode M3 and the grid of the PNP triode M4 are connected with the output end of the bias current source Iail, the drain of the PMOS tube M1 is grounded, the drain of the NPN triode M4 and the grid of the constant temperature triode M5 are connected with the output end of the second current mirror, and the drain of the NPN triode M1 is connected with the output end of the second current mirror through the negative temperature coefficient of the NPN triode M1.
Furthermore, the NMOS tube M0 is an enhanced NMOS tube, and the PMOS tubes M1 are enhanced PMOS tubes.
Further, the generating circuit of the positive temperature coefficient current source comprises an NPN triode M6-M7, a resistor R2-R3 and a third current mirror, wherein a collector serial resistor R2 of the NPN triode M6 is connected with a power supply VCC, an emitter of the NPN triode M6 is grounded, a base of the NPN triode M6 is simultaneously connected with a collector of the NPN triode M6 and a base of the NPN triode M7, an emitter serial resistor R3 of the NPN triode M7 is grounded, a collector of the NPN triode M7 is connected with an input end of the third current mirror, and an output end of the third current mirror outputs a positive temperature coefficient current source Iptat.
Further, the generating circuit of the positive temperature coefficient current source comprises an NPN triode M6 resistor R2 and a fourth current mirror, wherein the collector serial resistor R2 of the NPN triode M6 is connected with the input end of the fourth current mirror, the emitter of the NPN triode M6 is grounded, the base of the NPN triode M6 is connected with the collector of the NPN triode M6, and the output end of the fourth current mirror outputs the positive temperature coefficient current source Iptat.
The beneficial technical effects of the invention are as follows:
the offset voltage of the zero crossing comparator is obtained by multiplying the output voltage of the synchronous buck converter by the positive temperature coefficient current source, the deviation of the temperature and the set output voltage in the synchronous buck converter on zero crossing detection is fully considered, and the accuracy of zero crossing detection is improved. And the circuit structure is simple and easy to realize.
Drawings
FIG. 1 is a prior art zero crossing detection circuit diagram for a synchronous buck converter;
FIG. 2 is a schematic diagram of a prior art zero crossing detection method for a synchronous buck converter;
fig. 3 is a zero-crossing detection circuit diagram for a synchronous buck converter according to a first embodiment of the present invention;
FIG. 4 is a diagram of a multiplier circuit according to a second embodiment of the present invention;
FIG. 5 is a circuit diagram of a positive temperature coefficient current source according to an embodiment of the present invention;
fig. 6 is a circuit diagram of another generation circuit of the ptc current source according to an embodiment of the present invention.
Detailed Description
The invention will now be further described with reference to the drawings and detailed description.
Example 1
As shown in fig. 3, the zero crossing detection circuit for the synchronous buck converter comprises a zero crossing comparator A and a multiplier, wherein the inverting input end of the zero crossing comparator A is connected with a synchronous tube M of the synchronous buck converter L The non-inverting input of the zero-crossing comparator A is connected with the output end Vos of the multiplier, the output end of the zero-crossing comparator A is connected with the input end of the driving circuit of the synchronous buck converter, the first input end of the multiplier is connected with the voltage output end VOUT of the synchronous buck converter, and the second input end of the multiplier is connected with the positive temperature coefficient current source Iptat.
In this embodiment, the multiplier includes PNP transistors M2-M5, NMOS transistors M0-M1, and resistors R0-R1, the emitter of the PNP transistor M2 is connected to the power VCC, the collector of the PNP transistor M2 is connected to the drain of the NMOS transistor M0, the source series resistor R0 of the NMOS transistor M0 is grounded, the gate of the NMOS transistor M0 is connected to the voltage output terminal VOUT of the synchronous buck converter, the base of the PNP transistor M2 and the emitter of the PNP transistor M3 are connected to the positive temperature coefficient current source Iptat, the collector of the PNP transistor M3 is grounded, the gate of the NMOS transistor M1 is connected to the collector of the PNP transistor M2, the bases of the PNP transistors M3 and M4 and the source of the NMOS transistor M1 are connected to the bias current source Itail, the drain of the NMOS transistor M1 is connected to the power source, the emitter of the PNP transistor M4 and the base of the PNP transistor M5 are connected to the constant temperature coefficient current source Iconst, the base of the PNP transistor M4 is grounded, and the collector of the PNP transistor M5 is connected to the voltage source of the output terminal VCC, and the collector of the PNP transistor M1 is connected to the output node of the PNP transistor is connected to the drain of the resistor.
In this embodiment, the NMOS transistors M0-M1 are all enhanced NMOS transistors.
Working principle: the ideal value of offset voltage Vos of zero-crossing comparator a should be
Wherein Vout is output voltage of synchronous buck converter, ron is synchronous tube M L Tdly is the delay of the zero-crossing comparator a and L is the filter inductance of the synchronous buck converter. Ron is positive temperature coefficient, increasing with increasing temperature, i.e. ron=ron_0 (1+at), ron_0 being the synchronization tube M at a temperature of 0 L On-resistance of (c). Tdly is constant with L for a given design. Therefore, the ideal offset voltage Vos is simplified to vos=a×vout (1+at).
In this embodiment, the offset voltage output by the output terminal Vos of the multiplier
Wherein Iptat is a positive temperature coefficient current source, iptat=iptat_0 (1+at), iptat_0 is a current value when the temperature is 0, iconst is a constant temperature coefficient current source, therefore, offset voltage Vos given by the multiplier satisfies vos=a=vout (1+at), thereby accurately counteracting deviation caused by temperature and set output voltage to zero crossing detection, and improving zero crossing detection accuracy.
Example two
The difference between this embodiment and the first embodiment is that the specific circuit structure of the multiplier is different, specifically, as shown in fig. 4, the multiplier includes an NPN triode M2, an NPN triode M3, a PNP triode M4, an NPN triode M5, an NMOS tube M0, a PMOS tube M1 and a resistor R0-R1, the emitter of the NPN triode M2 is grounded, the collector of the NPN triode M2 and the gate of the PMOS tube M1 are connected to the output terminal of the first current mirror 1, the source of the NMOS tube M0 is connected in series with a resistor R0, the gate of the NMOS tube M0 is connected to the voltage output terminal VOUT of the synchronous buck converter, the drain of the NMOS tube M0 is connected to the input terminal of the first current mirror 1, the power supply of the first current mirror 1 is connected to the power VCC, the base of the NPN triode M2 and the emitter of the NPN triode M3 are connected to the positive temperature coefficient current source iptt, the collector of the NPN triode M3 and the base of the PNP triode M4 are connected to the output terminal of the first current mirror, the base of the PNP triode M1 and the drain of the PNP triode M1 are connected to the output terminal of the second current mirror 5, and the drain of the second current mirror 5 is connected to the input terminal of the second current mirror 2 is connected to the input terminal of the NPN transistor, and the drain of the second current mirror is connected to the second current mirror 2 is connected to the output terminal of the second current mirror 2.
In this embodiment, the NMOS transistor M0 is an enhanced NMOS transistor, and the PMOS transistors M1 are enhanced PMOS transistors.
The working principle is similar to that of the first embodiment, and reference is made to the first embodiment, which will not be described in detail.
In the above embodiments, two preferred circuit diagrams of the multiplier are given, but in other embodiments, the multiplier may also be an existing multiplier, which can be easily implemented by those skilled in the art, and will not be described in detail.
The positive temperature coefficient current source Iptat can be realized by adopting the generating circuit of the positive temperature coefficient current source shown in fig. 5, and comprises an NPN triode M6-M7, resistors R2-R3 and a third current mirror, wherein a collector serial resistor R2 of the NPN triode M6 is connected with a power supply VCC, an emitter of the NPN triode M6 is grounded, a base of the NPN triode M6 is simultaneously connected with the collector of the NPN triode M6 and the base of the NPN triode M7, an emitter serial resistor R3 of the NPN triode M7 is grounded, a collector of the NPN triode M7 is connected with an input end of the third current mirror, a power supply input end of the third current mirror 3 is connected with the power supply VCC, and an output end of the third current mirror outputs the positive temperature coefficient current source Iptat.
The positive temperature coefficient current source Iptat may also be implemented by adopting the generating circuit of the positive temperature coefficient current source shown in fig. 6, which includes an NPN triode M6 resistor R2 and a fourth current mirror, the collector series resistor R2 of the NPN triode M6 is connected to the input end of the fourth current mirror, the power input end of the fourth current mirror 4 is connected to the power VCC, the emitter of the NPN triode M6 is grounded, the base of the NPN triode M6 is connected to the collector of the NPN triode M6, and the output end of the fourth current mirror outputs the positive temperature coefficient current source Iptat.
Of course, the ptc current source Iptat may also be implemented by an existing ptc current source generating circuit, which is easily implemented by those skilled in the art, and will not be described in detail.
The constant temperature coefficient current source Iconst and the bias current source Itail are implemented using existing circuitry, which can be easily implemented by a person skilled in the art, and will not be described in detail.
The first current mirror 1, the second current mirror 2, the third current mirror 3 and the fourth current mirror 4 are implemented using existing current mirror circuits, which can be easily implemented by a person skilled in the art, and which will not be described in detail.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1. A zero crossing detection circuit for a synchronous buck converter, characterized by: the zero-crossing comparator comprises a zero-crossing comparator and a multiplier, wherein two input ends of the zero-crossing comparator are respectively connected with an output end of the multiplier and a drain electrode of a synchronous tube of the synchronous buck converter, an output end of the zero-crossing comparator is connected with an input end of a driving circuit of the synchronous buck converter, a first input end of the multiplier is connected with a voltage output end of the synchronous buck converter, and a second input end of the multiplier is connected with a positive temperature coefficient current source;
the multiplier comprises PNP triodes M2-M5, NMOS transistors M0-M1 and resistors R0-R1, wherein the emitter of the PNP triode M2 is connected with a power supply VCC, the collector of the PNP triode M2 is connected with the drain of the NMOS transistor M0, the source of the NMOS transistor M0 is connected with the ground, the grid electrode of the NMOS transistor M0 is connected with the voltage output end VOUT of the synchronous buck converter, the base of the PNP triode M2 and the emitter of the PNP triode M3 are connected with a positive temperature coefficient current source Ittat, the collector of the PNP triode M3 is grounded, the grid electrodes of the NMOS transistor M1 are connected with the collector of the PNP triode M2, the bases of the PNP triodes M3 and M4 and the source of the NMOS transistor M1 are connected with a bias current source Itail, the drain of the NMOS transistor M1 is connected with the power supply, the emitter of the PNP triode M4 and the base of the PNP triode M5 are connected with a constant temperature coefficient current source Iconst, the collector of the PNP triode M4 is grounded, and the collector of the PNP triode M5 is connected with the collector of the VCC 1, and the collector of the PNP triode M1 is connected with the drain of the NMOS transistor M1;
or, the multiplier includes NPN triode M2, NPN triode M3, PNP triode M4, NPN triode M5, NMOS tube M0, PMOS tube M1 and resistance R0-R1, NPN triode M2's projecting pole ground, NPN triode M2's collecting electrode and PMOS tube M1's grid connect the output of first current mirror, NMOS tube M0's source series resistance R0 ground, NMOS tube M0's grid connect synchronous buck converter's voltage output VOUT, NMOS tube M0's drain electrode connects the input of first current mirror, NPN triode M2's base and NPN triode M3's projecting pole connect positive temperature coefficient Iptat, NPN triode M3's collecting electrode connects power VCC, NPN triode M3's base and PNP triode M4's source connect bias current source Itail, PMOS tube M1's drain electrode ground, PNP triode M4's and PNP triode M5's constant current source connect the voltage output of second current mirror, the drain electrode of PNP triode M5 connects the input of second current mirror to the output of second current mirror, the triode M1's the drain electrode is connected with the input of second current mirror, the drain electrode of NPN triode M1 is connected with the output of second current mirror.
2. The zero crossing detection circuit for a synchronous buck converter of claim 1, wherein: the NMOS transistors M0-M1 are all enhanced NMOS transistors.
3. The zero crossing detection circuit for a synchronous buck converter of claim 1, wherein: the NMOS tube M0 is an enhanced NMOS tube, and the PMOS tubes M1 are enhanced PMOS tubes.
4. The zero crossing detection circuit for a synchronous buck converter of claim 1, wherein: the generating circuit of the positive temperature coefficient current source comprises an NPN triode M6-M7, a resistor R2-R3 and a third current mirror, wherein a collector serial resistor R2 of the NPN triode M6 is connected with a power supply VCC, an emitter of the NPN triode M6 is grounded, a base of the NPN triode M6 is simultaneously connected with the collector of the NPN triode M6 and the base of the NPN triode M7, the emitter serial resistor R3 of the NPN triode M7 is grounded, a collector of the NPN triode M7 is connected with an input end of the third current mirror, and an output end of the third current mirror outputs a positive temperature coefficient current source Iptat.
5. The zero crossing detection circuit for a synchronous buck converter of claim 1, wherein: the generating circuit of the positive temperature coefficient current source comprises an NPN triode M6 resistor R2 and a fourth current mirror, wherein a collector serial resistor R2 of the NPN triode M6 is connected with the input end of the fourth current mirror, an emitter of the NPN triode M6 is grounded, a base of the NPN triode M6 is connected with a collector of the NPN triode M6, and an output end of the fourth current mirror outputs a positive temperature coefficient current source Iptat.
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| CN201710517085.4A CN107132405B (en) | 2017-06-29 | 2017-06-29 | Zero-crossing detection circuit for synchronous buck converter |
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| CN201710517085.4A CN107132405B (en) | 2017-06-29 | 2017-06-29 | Zero-crossing detection circuit for synchronous buck converter |
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| CN111478563B (en) * | 2020-05-15 | 2023-03-24 | 电子科技大学 | Zero-crossing detection circuit suitable for BUCK converter |
| CN115575700B (en) * | 2022-11-09 | 2023-03-10 | 上海芯龙半导体技术股份有限公司 | Zero-crossing detection circuit |
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