CN109004025A - A kind of thin SOI LIGBT with junction type drift region structure - Google Patents
A kind of thin SOI LIGBT with junction type drift region structure Download PDFInfo
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- CN109004025A CN109004025A CN201810863342.4A CN201810863342A CN109004025A CN 109004025 A CN109004025 A CN 109004025A CN 201810863342 A CN201810863342 A CN 201810863342A CN 109004025 A CN109004025 A CN 109004025A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000000605 extraction Methods 0.000 claims abstract description 3
- 239000004020 conductor Substances 0.000 claims description 32
- 230000005611 electricity Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 abstract description 10
- 239000007924 injection Substances 0.000 abstract description 10
- 230000002708 enhancing effect Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract description 2
- 230000001133 acceleration Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 3
- 230000003014 reinforcing effect Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 210000000056 organ Anatomy 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention belongs to power semiconductor technologies fields, and in particular to a kind of SOI LIGBT (Lateral Insulator Gate Bipolar Transistor).Present invention be primarily characterized in that: baltimore groove and junction type drift region structure are used, spill trench bottom is not contacted with buried oxide layer, and only there are extremely narrow conductive paths.When forward conduction, spill groove sidewall stops the hole in drift region to be extracted by cathode, therefore improves the hole concentration of drift region cathode terminal, according to the requirement of electroneutral, more electronics are by injection drift region, so that the carrier concentration of drift region cathode terminal is obviously improved, i.e. injection enhancing.Therefore, the conductivity modulation effect enhancing of device drift region, forward conduction voltage drop reduce；When device turns off, the P item acceleration in drift region structure exhausts N-type drift region, and provides the extraction path in hole, improves the turn-off speed of device, reduces turn-off power loss.Beneficial effects of the present invention are that, relative to traditional SOI LIGBT structure, the present invention has lower forward conduction voltage drop, while having good turn-off characteristic.
Description
Technical field
The invention belongs to power semiconductor technologies fields, are related to a kind of thin SOI LIGBT with junction type drift region structure
(Lateral Insulator Gate Bipolar Transistor, landscape insulation bar double-pole-type transistor).
Background technique
LIGBT is a kind of structure mixed by lateral fet and bipolar junction transistor, it has both
MOSFET input impedance height and the advantage for driving simple advantage and the high and low conduction voltage drop of BJT device current density,
As one of the core electron component in the application of modern power electronic circuit.Compared to LDMOS have bigger current density and
Smaller conduction voltage drop.SOI LIGBT avoids the problem that body silicon leakage current is big, turn-off power loss is big, and has insulation performance
Well, the advantages that parasitic capacitance is small and integrated level is high, is widely used in the consumption electronic products such as automotive electronics, Switching Power Supply.
Researcher is concentrated mainly in thick top layer silicon the work of SOI LIGBT, less to the device concern of thin top layer silicon.
Compared to thick top layer silicon, simple process and low cost of the thin top layer silicon in device isolation and integrated chip.But due to top layer silicon
The SOI LIGBT of excessively thin and compound siloxy surface presence, thin top layer silicon has that conduction voltage drop is excessive.
Summary of the invention
In order to promote the current capacity of thin SOI LIGBT, the compromise for improving SOI LIGBT conduction voltage drop and turn-off power loss is closed
System, the invention proposes a kind of thin SOI LIGBT with junction type drift region structure.
The invention mainly comprises the innovations in terms of following two: first is that generating electron injection enhancement effect by introducing baltimore groove
It answers, improves SOI LIGBT close to the carrier concentration of cathode side drift region, and then reduce the conduction voltage drop of SOI LIGBT；Two
It is to introduce junction type drift region, the P-doped zone of junction type drift region accelerates the broadening of depletion region in device turn off process, simultaneously
It is provided for the hole in drift region and extracts path, therefore can speed up shutdown and reduce turn-off power loss.
Below the injection enhancing principle of middle concave slot of the present invention is made briefly to illustrate.In device on-state, drift region
Hole by the blocking of baltimore groove, can not be extracted by cathode electrode, for maintain drift region electroneutral, by the electronics of Channeling implantation
Also correspondingly to increase, therefore carrier concentration of the drift region close to cathode terminal side is just significantly improved.Spill trench bottom
Guiding path width between buried oxide layer upper surface is T, and T is smaller, and injection reinforcing effect is more significant, as shown in Figure 1, device exists
Conduction voltage drop is lower in the case where identical conducting electric current, as shown in Figure 2.According to simulation result, when T is more than 400nm, injection
Enhancement effect disappears, at this time the conduction voltage drop of device no advantage compared with common traditional structure.To realize minimum T value,
In practical devices manufacture, the SOI material of thin top layer silicon is preferably used, while baltimore groove can aoxidize skill by lithographic technique or LOCOS
Art etc. is realized.
The technical scheme is that
A kind of thin SOI LIGBT with junction type drift region structure, including along device vertical direction successively layer from bottom to top
Substrate layer 1, buried oxide layer 2 and the N-type top semiconductor layer 4 of folded setting；4 surface of N-type top semiconductor layer is respectively formed P
Type well region 3 and N-type well region 9 have therebetween spacing, and depending on the part pressure resistance of distance values visual organ, the doping concentration of N-type well region 9 is higher than N
Type top semiconductor layer 4；The surface of the P type trap zone 3 forms the p-type heavily doped region 5 and N-type heavily doped region 6 to contact with each other, institute
It states p-type heavily doped region 5 and cathode electrode is drawn in 6 upper surface of N-type heavily doped region jointly；In N-type heavily doped region 6 and close to N-type trap
3 surface of P type trap zone between 3 edge of P type trap zone in area 9 forms medium 7, forms conductive material 8,7 He of medium on 7 surface of medium
The grid structure of device is collectively formed in conductive material 8, draws gate electrode by 8 surface of conductive material；In the surface shape of N-type well region 9
Anode electrode is drawn at p-type heavily doped region 10, and by 10 surface of p-type heavily doped region.
N-type top semiconductor layer 4 between P type trap zone 3 and N-type well region 9 forms groove close to the side of P type trap zone 3
Structure, the two sidewalls and bottom of groove are covered by thin-layered medium 7-1, and the thin-layered medium 7-1 thickness is less than the thickness of gate medium 7
Degree, the surface the thin-layered medium 7-1 form layer of conductive material 8-1, the conductive material 8-1 connection gate electrode；It is described recessed
It is the extremely narrow conductive path that spacing is T between 2 upper surface of trench bottom and buried oxide layer, and T should be not more than 400nm.P-type
There are junction type drift regions 11 between well region 3 and N-type well region 9.
In above scheme, the device transverse direction and device vertical direction are mutually perpendicular to；The device longitudinal direction is
Third dimension direction vertical with device transverse direction and device vertical direction simultaneously；Device transverse direction, is indulged at vertical direction
Three-dimensional cartesian coordinate system is constituted to direction, corresponding with Fig. 1 to be, device transverse direction corresponds to X-axis, and device vertical direction is corresponding
Y-axis, device longitudinal direction correspond to Z axis.
Further, the conductive material 8-1 is being not attached to close to 3 side of P type trap zone with conductive material 8.
Further, the conductive material 8-1 is filled with entire groove.And the conductive material 8-1 is close to P type trap zone
3 sides are connected with conductive material 8.
Further, the conductive material 8-1 covers the groove close to 3 side of P type trap zone and part recess structure bottom
Portion.And the conductive material 8-1 is being connected close to 3 side of P type trap zone with conductive material 8.
Further, the junction type drift region structure by longitudinal Disjunct distribution P-doped zone 11-1 and N-doped zone
11-2 composition.
Further, the side of the P-doped zone 11-1 and N-doped zone 11-2 is contacted with N-type buffer layer 9.
Further, it the side of the P-doped zone 11-1 and N-doped zone 11-2 and protrudes into below baltimore groove.
Further, it the side of the P-doped zone 11-1 and N-doped zone 11-2 and protrudes into below baltimore groove, it is another
Side is contacted with N-type buffer layer 9.
Further, the junction type drift region structure is made of RESURF structure.The RESURF structure is by P-doped zone
11-1 composition, the longitudinally covered entire drift region P-doped zone 11-1, and its bottom is contacted with N-type top semiconductor layer 4.
Further, the junction type drift region structure is made of RESURF structure.The RESURF structure is by being in top
N-type heavily doped region 11-2 it is parallel with the P-doped zone 11-1 being below form, the N-type heavily doped region 11-2, p-type are mixed
The miscellaneous longitudinally covered entire drift region area 11-1, and N-type heavily doped region 11-2 is contacted with P-doped zone 11-1 vertical direction.The P
The type bottom doped region 11-1 is contacted with N-type top semiconductor drift layer 4.
Beneficial effects of the present invention are, compared to traditional LIGBT, to have faster turn-off speed and smaller loss；Phase
Than in traditional IEGT implementation, there is higher realizability and the characteristic compatible with CMOS technology；Compared to thick top layer
Silicon IGBT, the technique in device isolation and integrated chip of the invention is simpler, and cost is lower.
Detailed description of the invention
Fig. 1 is the injection reinforcing effect contrast schematic diagram of the present invention with traditional structure；
Fig. 2 is the conduction voltage drop contrast schematic diagram of the present invention with traditional structure；
Fig. 3 is the structural schematic diagram of embodiment 1；
Fig. 4 is the structural schematic diagram of embodiment 2；
Fig. 5 is the structural schematic diagram of embodiment 3；
Fig. 6 is the structural schematic diagram of embodiment 4；
Fig. 7 is the structural schematic diagram of embodiment 5；
Fig. 8 is the structural schematic diagram of embodiment 6；
Fig. 9 is the structural schematic diagram of embodiment 7；
Figure 10 is the structural schematic diagram of embodiment 8；
Figure 11 is the structural schematic diagram of embodiment 9；
Figure 12 is the structural schematic diagram of embodiment 10.
Specific embodiment
With reference to the accompanying drawings and examples, the technical schemes of the invention are described in detail.
Embodiment 1
As shown in Figure 1, this example is a kind of thin SOI LIGBT with junction type drift region structure, including along device Vertical Square
To substrate layer 1, buried oxide layer 2 and the N-type top semiconductor layer 4 being cascading from bottom to top；The N-type top semiconductor
4 surface of layer are respectively formed P type trap zone 3 and N-type well region 9, there is spacing therebetween, depending on the part pressure resistance of distance values visual organ, N-type trap
The doping concentration in area 9 is higher than N-type top semiconductor layer 4；The surface of the P type trap zone 3 forms the p-type heavily doped region to contact with each other
5 and N-type heavily doped region 6, the p-type heavily doped region 5 and 6 upper surface of N-type heavily doped region draw cathode electrode jointly；In N-type weight
Doped region 6 and 3 surface of P type trap zone between 3 edge of P type trap zone of N-type well region 9 form medium 7, in 7 surface shape of medium
At conductive material 8, the grid structure of device is collectively formed in medium 7 and conductive material 8, draws grid electricity by 8 surface of conductive material
Pole；P-type heavily doped region 10 is formed on the surface of N-type well region 9, and anode electrode is drawn by 10 surface of p-type heavily doped region.
N-type top semiconductor layer 4 between P type trap zone 3 and N-type well region 9 forms groove close to the side of P type trap zone 3
Structure, the two sidewalls and bottom of groove are covered by thin-layered medium 7-1, the thin-layered medium 7-1 thickness can be, but not limited to
Gate medium 7 is consistent, and the surface the thin-layered medium 7-1 forms layer of conductive material 8-1, the conductive material 8-1 connection grid electricity
Pole；And the conductive material 8-1 is being not attached to close to 3 side of P type trap zone with conductive material 8.The bottom portion of groove and buried oxide layer 2
It is the extremely narrow conductive path that spacing is T between upper surface, and T should be not more than 400nm.P type trap zone 3 and N type well region 9
Between there are junction type drift regions 11.
The working principle of this example are as follows:
It is not contacted using dielectric impedance slot and the junction type drift region structure containing PN junction, medium trench bottom with buried oxide layer.It is positive
When conducting, medium groove sidewall physically stops hole access, promotes hole concentration, according to the requirement of electroneutral, more electricity
Son is by injection drift region, i.e. injection enhancing.Therefore, the conductivity modulation effect enhancing of device drift region, forward conduction voltage drop reduce；
Device turn off when, the PN junction of junction type drift region structure exhausts mutually, accelerates the extraction of carrier, improve device turn-off speed,
Reduce turn-off power loss.
Beneficial effects of the present invention are that, relative to conventional thin SOI LIGBT structure, the present invention has lower forward conduction
Pressure drop, while there is good turn-off characteristic.
Embodiment 2
As shown in Fig. 2, this example the difference from embodiment 1 is that, conductive material 8-1 described in this example is filled with entire groove.
And the conductive material 8-1 is being connected close to 3 side of P type trap zone with conductive material 8.It is consistent in its working mechanism and embodiment 1；
Compared with Example 1, new device technology is simpler in this example.
Embodiment 3
As shown in figure 3, this example the difference from example 2 is that, conductive material 8-1 described in this example is covered close to p-type
The groove and part recess structural base of 3 side of well region.And the conductive material 8-1 is close to 3 side of P type trap zone and conduction
Material 8 is connected.Compared with Example 2, new device injection reinforcing effect weakens in this example, but hot carrier in jection is smaller, device
Reliability enhancing.
Embodiment 4
As shown in figure 4, this example is a kind of thin SOI LIGBT device with longitudinal alternately PN junction structure, this example and implementation
The difference of example 2 is junction type drift region structure described in this example by the P-doped zone 11-1 and n-type doping of longitudinal Disjunct distribution
Area 11-2 composition.
Embodiment 5
As shown in figure 5, this example is a kind of thin SOI LIGBT device with longitudinal alternately PN junction structure, this example and implementation
The difference of example 4 is that the side of P-doped zone 11-1 described in this example and N-doped zone 11-2 are contacted with N-type buffer layer 9.
Embodiment 6
As shown in fig. 6, this example is a kind of thin SOI LIGBT device with longitudinal alternately PN junction structure, this example and implementation
The difference of example 5 is the side of P-doped zone 11-1 described in this example and N-doped zone 11-2 and protrudes into below baltimore groove, but
It is not contacted with N-type buffer layer 9.
Embodiment 7
As shown in fig. 7, this example is a kind of thin SOI LIGBT device with longitudinal alternately PN junction structure, this example and implementation
The difference of example 5 is the side of P-doped zone 11-1 described in this example and N-doped zone 11-2 and protrudes into below baltimore groove, separately
Side is contacted with N-type buffer layer 9.
Embodiment 8
As shown in figure 8, this example is a kind of thin SOI LIGBT device with RESURF structure, the area of this example and embodiment 2
It is not to introduce P-doped zone in junction type drift region described in this example, the upper surface of the P-doped zone 11-1 is partly led with N-type
Body layer surface has spacing.
Embodiment 9
As shown in figure 9, this example is a kind of thin SOI LIGBT device with RESURF structure, the area of this example and embodiment 2
It is not that the surface of junction type drift region described in this example introduces P-doped zone, the P-doped zone 11-1.
Embodiment 10
As shown in Figure 10, this example is a kind of thin SOI LIGBT device with RESURF structure, this example and embodiment 8
Difference is that junction type drift region structure described in this example is made of RESURF structure.The RESURF structure is by the N in top
Type heavily doped region 11-2 is parallel with the P-doped zone 11-1 being below to be formed, the N-type heavily doped region 11-2, P-doped zone
The longitudinally covered entire drift region 11-1, and N-type heavily doped region 11-2 is contacted with P-doped zone 11-1 vertical direction.The p-type is mixed
The bottom miscellaneous area 11-1 is contacted with N-type top semiconductor drift layer 4.
Claims (7)
1. a kind of thin SOI LIGBT with junction type drift region structure, including stacked gradually from bottom to top along device vertical direction
Substrate layer (1), buried oxide layer (2) and the N-type top semiconductor layer (4) of setting；N-type top semiconductor layer (4) both ends point
Not Xing Cheng P type trap zone (3) and N-type well region (9), the doping concentration of N-type well region (9) is higher than the doping of N-type top semiconductor layer (4)
Concentration；
The surface of the P type trap zone (3) forms the p-type heavily doped region (5) and N-type heavily doped region (6) to contact with each other, and N-type weight
Doped region (6) is located at close to the side of N-type well region (9), and the p-type heavily doped region (5) and N-type heavily doped region (6) upper surface are total
With extraction cathode electrode；
There are medium (7) in the upper surface of part N-type heavily doped region (6), and medium (7) extends and covers to N-type well region (9) side
The upper surface of lid P type trap zone (3) forms grid conductive material (8) on medium (7) surface, and medium (7) and grid conductive material (8) are altogether
With the grid structure for forming device, gate electrode is drawn by conductive material (8) surface；
P-type heavily doped region (10) are formed on the surface of N-type well region (9), and anode electricity is drawn by p-type heavily doped region (10) surface
Pole；
In N-type top semiconductor layer (4) between P type trap zone (3) and N-type well region (9), in the side close to P type trap zone (3)
Groove structure is formed, the two sidewalls and bottom of groove are covered by thin-layered medium (7-1), the thickness of the thin-layered medium (7-1)
Less than the thickness of medium (7)；It is covered with conductive material (8-1) on the thin-layered medium (7-1), the conductive material (8-1) is even
Connect gate electrode；It is the conductive path that spacing is T between the bottom portion of groove and buried oxide layer (2) upper surface, and T should be not more than
400nm；
There are junction type drift region (11) in N-type top semiconductor layer (4) between groove and N-type well region (9).
2. a kind of thin SOI LIGBT with junction type drift region structure according to claim 1, which is characterized in that described
The coverage area of conductive material (8-1) are as follows: only cover recess sidewall and the part recess bottom close to P type trap zone (3).
3. a kind of thin SOI LIGBT with junction type drift region structure according to claim 1, which is characterized in that described
Conductive material (8-1) completely covers groove two sidewalls and bottom.
4. a kind of thin SOI LIGBT with junction type drift region structure according to claim 2, which is characterized in that described
Junction type drift region (11) is made of the alternatively distributed P-doped zone of longitudinal direction (11-1) and N-doped zone (11-2)；
The device longitudinal direction is third dimension direction vertical with device transverse direction and device vertical direction simultaneously.
5. a kind of thin SOI LIGBT with junction type drift region structure according to claim 2, which is characterized in that described
Junction type drift region (11) is specially P-doped zone (11-1), the P-doped zone surface (11-1) and N-type top semiconductor layer (4) table
The spacing in face is W, and W is greater than or equal to 0.
6. a kind of thin SOI LIGBT with junction type drift region structure according to claim 3, which is characterized in that described
Junction type drift region (11) is made of the alternatively distributed P-doped zone of longitudinal direction (11-1) and N-doped zone (11-2)；
The device longitudinal direction is third dimension direction vertical with device transverse direction and device vertical direction simultaneously.
7. a kind of thin SOI LIGBT with junction type drift region structure according to claim 3, which is characterized in that described
Junction type drift region (11) is specially P-doped zone (11-1), the P-doped zone surface (11-1) and N-type top semiconductor layer (4) table
The spacing in face is W, and W is greater than or equal to 0.
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| CN110444590A (en) * | 2019-09-05 | 2019-11-12 | 电子科技大学 | A kind of superjunction LIGBT power device |
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| CN110459609A (en) * | 2019-08-29 | 2019-11-15 | 电子科技大学 | A kind of short circuit anode thin layer high voltage power device |
| CN110473907A (en) * | 2019-08-29 | 2019-11-19 | 电子科技大学 | A kind of super low-power consumption thin layer high voltage power device |
| CN110459609B (en) * | 2019-08-29 | 2020-09-15 | 电子科技大学 | Short-circuit anode thin-layer high-voltage power device |
| CN110473869A (en) * | 2019-08-30 | 2019-11-19 | 广东瑞森半导体科技有限公司 | A kind of LIGBT type ESD protective device with oxide layer |
| CN110473869B (en) * | 2019-08-30 | 2022-05-24 | 瑞森半导体科技(广东)有限公司 | LIGBT type ESD protection device with oxide layer |
| CN110444590A (en) * | 2019-09-05 | 2019-11-12 | 电子科技大学 | A kind of superjunction LIGBT power device |
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Application publication date: 20181214 |