CN108987337B - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN108987337B CN108987337B CN201811027840.1A CN201811027840A CN108987337B CN 108987337 B CN108987337 B CN 108987337B CN 201811027840 A CN201811027840 A CN 201811027840A CN 108987337 B CN108987337 B CN 108987337B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The embodiment of the invention provides an array substrate, a manufacturing method thereof and a display device, and relates to the technical field of display. The manufacturing method comprises the following steps: forming a first pattern over a substrate base plate; forming an insulating layer covering the first pattern; forming a protective pattern above the insulating layer, wherein the protective pattern exposes a part of the insulating layer on which a via hole is to be formed; etching a part to be formed with a via hole on the insulating layer by etching gas to form a hole, wherein the bottom of the hole is provided with a residual film layer with a preset thickness; wherein the preset thickness is more than or equal to 0 and less than the thickness of the insulating layer; polymers generated by the reaction of etching gas and the insulating layer are formed in the holes; and etching the holes by inert gas to remove the polymer and the residual film layer and form the through holes exposing the first pattern. The array substrate is used for manufacturing a display device.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display device.
Background
A Thin Film Transistor (TFT) may be used as a pixel switching element of a flat panel display. According to different materials used for the active layer in the TFT structure, the TFT can be classified into: amorphous silicon TFTs, polycrystalline silicon TFTs, single crystal silicon TFTs, and oxide semiconductor TFTs; among them, an amorphous silicon TFT active layer can be easily deposited on a large area and easily processed under a low temperature condition, but has a disadvantage of low charge mobility; although the polysilicon TFT active layer has high charge migration and excellent electrical characteristics, the polysilicon TFT active layer needs to be processed under high temperature conditions and has unstable reliable consistency; oxide semiconductor (e.g., IGZO, indium gallium zinc oxide) TFTs have high carrier mobility and can better meet the driving requirements of ultra-large-sized liquid crystal displays, and oxide semiconductor TFTs also have the characteristics of uniform components, low cost, high transparency, and the like, and thus are receiving attention of research and development personnel.
In the prior art, for an oxide semiconductor TFT array substrate, because H element in the gas used in the preparation of a silicon nitride insulating layer has reducibility to an oxide channel, which may cause an increase of oxygen vacancy and make an oxide active layer conductive, a silicon dioxide film or a silicon dioxide and silicon nitride composite film is usually used as an insulating protective layer.
In order to simplify the process flow, a via hole penetrating through the insulating protection layer is usually manufactured by dry etching, and the bottom of the via hole is the upper surface of the drain electrode. Typically using a fluorocarbon gas (e.g. CF)4) And oxygen is used as etching gas to etch the silicon dioxide film, in the etching process, a large amount of fluorocarbon polymers grow in the through holes made of silicon dioxide materials, the shapes of the fluorocarbon polymers are different, and the fluorocarbon polymers cannot be easily removed in the subsequent process, so that the electrical connection between the pixel electrode and the drain electrode is influenced, and the display of the display is poor.
Disclosure of Invention
In order to solve the above problems in the prior art, embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device. The manufacturing method removes the polymer formed in the via hole in the etching process, thereby avoiding the adverse effect of the polymer on the electrical communication of the first pattern and the second pattern. In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in one aspect, an embodiment of the present invention provides a method for manufacturing an array substrate, where the method for manufacturing an array substrate includes: forming a first pattern over a substrate base plate; forming an insulating layer covering the first pattern; forming a protective pattern over the insulating layer, the protective pattern exposing a portion of the insulating layer where a via is to be formed; etching the part to be formed with the via hole on the insulating layer by etching gas to form a hole, wherein the bottom of the hole is provided with a residual film layer with a preset thickness; wherein the preset thickness is more than 0 and less than the thickness of the insulating layer; a polymer generated by the reaction of the etching gas and the insulating layer is formed in the hole; and etching the hole by inert gas to remove the polymer and the residual film layer and form the via hole exposing the first pattern.
Optionally, when the hole is etched by using an inert gas, the bombardment energy of the inert gas is greater than that of the etching gas.
Optionally, when the hole is etched by using an inert gas, the bombardment energy of the inert gas is greater than that of the etching gas, and the method includes: and increasing the self-bias voltage of the etching equipment compared with the etching of the part to be formed with the via hole on the insulating layer by etching gas.
Optionally, the inert gas comprises Ar gas.
Optionally, the insulating layer comprises a silicon dioxide insulating layer; the etching gas includes: a first etching gas, wherein the first etching gas is composed of fluorocarbon gas and oxygen gas; the etching the portion of the insulating layer where the via hole is to be formed by the etching gas includes: etching a part, corresponding to the via hole to be formed, on the silicon dioxide insulating layer by using the first etching gas to form a first hole; the bottom of the first hole is provided with a residual film layer with a preset thickness; the preset thickness is more than 0 and less than the thickness of the silicon dioxide insulating layer; and a fluorocarbon polymer generated by the reaction of the first etching gas and the silicon dioxide insulating layer is formed in the first hole.
Optionally, the insulating layer further includes: a silicon nitride insulating layer covering the silicon dioxide insulating layer; the etching gas further includes: a second etching gas, wherein the second etching gas is composed of sulfur-fluorine gas and oxygen; before the etching, by the first etching gas, a portion of the silicon dioxide insulating layer corresponding to the via to be formed, the etching, by the etching gas, the portion of the insulating layer on which the via is to be formed further includes: etching a part, corresponding to the via hole to be formed, on the silicon nitride insulating layer through the second etching gas to form a second hole exposing the silicon dioxide insulating layer; the position of the first hole to be formed corresponds to the second hole; the hole is composed of the first hole and the second hole to be formed.
Optionally, after the step of forming the via hole exposing the first pattern, the method for manufacturing the array substrate further includes: removing the protective pattern; forming a second pattern over the insulating layer; the second pattern is in contact with the first pattern through the via hole.
Optionally, the preset thickness is more than 0 and less than the thickness of the insulating layer; the bottom of the via hole is provided with a step with the height equal to the preset thickness; the height of the step is less than or equal to 1/8 the film thickness of the second pattern.
Optionally, before the step of forming the insulating layer covering the first pattern, the method for manufacturing the array substrate further includes: sequentially forming a grid electrode, a grid insulation layer covering the grid electrode, an oxide active layer arranged on the grid insulation layer, a source electrode and a drain electrode which are arranged on the grid insulation layer and are in contact with the oxide active layer on the substrate base plate; the first pattern is the drain electrode; the second pattern is a pixel electrode.
Optionally, the material of the protection pattern is a photoresist material.
On the other hand, the embodiment of the invention also provides an array substrate, and the array substrate is prepared by the manufacturing method of the array substrate.
In another aspect, an embodiment of the present invention further provides a display device, where the display device includes the array substrate described above.
Based on this, according to the manufacturing method provided by the embodiment of the present invention, in the process of etching the insulating layer, etching is performed by using the etching gas, and then at the final stage of etching, that is, when the residual film layer at the bottom of the hole reaches the preset thickness, the etching is performed on the hole by using the inert gas, so as to remove the polymer and the residual film layer generated by the reaction of the etching gas and the insulating layer, form the via hole, and the second pattern to be formed subsequently contacts with the first pattern through the via hole, so that the polymer formed in the via hole is prevented from affecting the electrical communication between the first pattern and the second pattern.
For example, when the first pattern is a drain and the second pattern is a pixel electrode, the method can prevent the polymer formed in the via hole from influencing the electrical connection between the pixel electrode and the drain, thereby improving the process yield.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic view of an array substrate in the related art;
FIG. 2 is a schematic diagram of an electron microscope showing a large amount of fluorocarbon polymer grown on the surface of a via hole after etching a silicon dioxide insulating layer by fluorocarbon gas and oxygen in the related art;
fig. 3 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a result after completion of step S03;
FIG. 5(a) is a diagram illustrating a result of completing step S04 in FIG. 3;
FIG. 5(b) is a schematic diagram showing another result of completing step S04 in FIG. 3;
FIG. 6(a) is a diagram illustrating the result of completing step S05 based on the structure shown in FIG. 5 (a);
FIG. 6(b) is a diagram illustrating the result of completing step S05 based on the structure shown in FIG. 5 (b);
FIG. 7 is a diagram illustrating another result of completing step S03;
FIG. 8 is a diagram illustrating the result of completing step S041 based on the structure shown in FIG. 7;
FIG. 9 is a diagram illustrating the result of completing step S042 based on the structure shown in FIG. 8;
FIG. 10(a) is a diagram illustrating the result of completing step S07 based on the structure shown in FIG. 6 (a);
FIG. 10(b) is a diagram illustrating the result of completing step S07 based on the structure shown in FIG. 6 (b);
fig. 11 is a schematic view of an array substrate manufactured by a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 12 is a schematic diagram illustrating a result obtained after step e is completed in a process of manufacturing a specific array substrate by using the manufacturing method of an array substrate according to the embodiment of the present invention;
fig. 13 is a schematic view showing a result after step f is completed in a process of manufacturing a specific array substrate by using the method for manufacturing an array substrate according to the embodiment of the present invention;
fig. 14 is a schematic diagram illustrating a result obtained after step g is completed in a process of manufacturing a specific array substrate by using the manufacturing method of an array substrate according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like as used in the description and in the claims of the present patent application do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. In the description of the present invention, it is to be understood that the terms "upper", "lower", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, a specific orientation configuration and operation, and thus, should not be construed as limiting the present invention.
In the related art, as shown in fig. 1, an oxide semiconductor TFT array substrate includes: the pixel structure comprises a substrate 1, a grid 2, a grid insulating layer 3, an active layer 4, a drain electrode 5, a source electrode 6, a silicon dioxide insulating layer 71, a silicon nitride insulating layer 72, an organic insulating layer 8, a common electrode 9 and a pixel electrode 10.
The gate electrode 2, the active layer 4, the drain electrode 5, and the source electrode 6 constitute a TFT.
In the oxide semiconductor TFT array substrate, the material of the insulating layer 7 is usually conventional silicon dioxide, or silicon dioxide and silicon nitride.
Referring to fig. 1, when the insulating layer 7 is made of silicon dioxide or silicon nitride, since the active layer 4 is easily made conductive by the direct contact between the silicon nitride layer 72 and the active layer 4, the silicon dioxide layer 71 is selected to be in direct contact with the active layer 4, and the silicon nitride layer 72 is further formed on the silicon dioxide layer 71.
In order to simplify the process flow, a via hole 11 penetrating through the insulating layer 7 is usually formed by dry etching, and the bottom of the via hole 11 exposes the upper surface of the drain electrode 5.
Fluorocarbon gases (e.g. CF) are typically selected4) And oxygen as a working gas to etch the silicon dioxide layer 71. In the etching process, as shown in fig. 2, fluorocarbon gas and oxygen react with the silicon dioxide layer 71, so that a large amount of fluorocarbon polymer grows on the inner wall of the via hole of the silicon dioxide layer 71, and cannot be easily stripped and removed in the subsequent process, and thus the pixel electrode 10 and the drain electrode 5 formed subsequently are not in good lap joint, thereby causing poor display.
In order to solve the above technical problem, an embodiment of the present invention provides a method for manufacturing an array substrate, as shown in fig. 3, the method includes 5 steps, and the following steps of the method are specifically described with reference to fig. 4, fig. 5(a), fig. 5(b), fig. 6(a), and fig. 6 (b):
step S01, forming a first pattern 5 over the base substrate 1;
step S02, forming an insulating layer 7 covering the first pattern 5;
step S03, as shown in fig. 4, forming a protective pattern 12 over the insulating layer 7, the protective pattern 12 exposing the portion 73 of the insulating layer 7 where the via is to be formed;
step S04, etching the portion 73 to be formed with the via hole on the insulating layer 7 by using the etching gas to form a hole 110 as shown in fig. 5(a) or fig. 5(b), wherein the bottom of the hole 110 has a residual film layer with a predetermined thickness (marked as d in fig. 5 (b)); wherein 0 < predetermined thickness < thickness of the insulating layer (marked as a in fig. 5 (b)); polymers generated by the reaction of etching gas and the insulating layer 7 are formed in the holes 110;
step S05, etching the hole 110 with an inert gas to remove the polymer and the residual film layer, and forming a via hole 11 exposing the first pattern 5 as shown in fig. 6(a) or fig. 6 (b).
It should be noted that the first and second patterns 5 may be any pattern in the array substrate that needs to be contacted with other structures through the via hole 11 on the insulating layer.
Second, in step S03, the above of the insulating layer 7 refers to a surface of the insulating layer 7 on a side away from the first pattern 5 and above the surface.
In addition, the protective pattern 12 is an etch-resistant layer, and functions such that only a region not covered with the protective pattern 12, i.e., a portion 73 of the insulating layer 7 where the via 11 is to be formed, is etched during etching.
Thirdly, in step S04, as shown in fig. 5(a), when the predetermined thickness is 0, there is no film layer left on the bottom of the hole 110, that is, the bottom of the hole 110 exposes the first pattern 5, and at this time, the hole 110 is the via hole 11 shown in fig. 6(a) having a polymer formed by the reaction of the etching gas and the insulating layer 7 on the sidewall 110 a; in the subsequent step S05, the polymer on the sidewall 110a of the hole 110 is removed by inert gas etching to obtain the via hole 11 shown in fig. 6 (a).
As shown in fig. 5(b), when 0 < the predetermined thickness < the thickness of the insulating layer, the bottom 110b of the hole 110 has a residual film with a predetermined thickness, and at this time, both the sidewall 110a and the bottom 110b of the hole 110 (i.e., the surface of the residual film) have a polymer generated by the reaction of the etching gas and the insulating layer 7; in the subsequent step S05, the polymer and the residual film layer in the hole 110 are removed by inert gas etching.
Fourthly, in step S04, when etching the portion 73 to be formed with the via hole on the insulating layer 7, if the etching is directly performed with the inert gas, since the etching performed with the inert gas only has bombardment in the direction perpendicular to the substrate base plate and does not have the effect of side etching, the formed via hole 11 has a steep sidewall, which is not favorable for the formation of other pattern layers in the via hole 11, which are required to be in contact with the first pattern.
Fifth, in step S05, the hole 110 is etched by the inert gas, and as can be seen from the foregoing description, since the etching by the inert gas only has bombardment in the direction perpendicular to the substrate base plate, no new polymer is generated in the via hole.
Based on this, according to the manufacturing method provided by the embodiment of the present invention, in the process of etching the insulating layer 7, etching is performed by using the etching gas, and then at the final stage of etching, that is, when the residual film layer at the bottom of the hole 110 reaches the preset thickness, the etching process is performed on the hole 110 by using the inert gas, so as to remove the polymer and the residual film layer generated by the reaction between the etching gas and the insulating layer 7, to form the via hole 11, and the second pattern to be formed subsequently contacts with the first pattern 5 through the via hole 11, so that the polymer formed in the via hole 11 is prevented from affecting the electrical communication between the first pattern and the second pattern.
For example, when the first pattern is a drain and the second pattern is a pixel electrode, the method can prevent the polymer formed in the via hole 11 from affecting the electrical connection between the pixel electrode and the drain, thereby increasing the process yield.
Preferably, the bombardment energy of the inert gas in step S05 is greater than the bombardment energy of the etching gas in step S04.
Thus, the inert gas plasma moving at high speed can more fully bombard the polymer and the residual film layer in the hole 110, so that the polymer and the residual film layer are more thoroughly etched and removed, and the upper surface of the first pattern 5 at the bottom is exposed to form the via hole 11.
For example, the bombardment energy of the inert gas is greater than that of the etching gas, which can be realized by the following steps:
in step S05, the self-bias of the etching apparatus is increased compared to step S04.
When the etching apparatus used is, for example, an ICP (Inductively Coupled Plasma) etching apparatus, the self bias (lower electrode power) is set to 15W when step S04 is performed; in performing step S05, the self-bias (lower electrode power) is increased to 60W.
In step S05, increasing the self-bias voltage of the etching apparatus can make the inert gas plasma to be subjected to a larger self-bias voltage, so that it has a higher moving energy in the direction perpendicular to the substrate base plate, so that the inert gas plasma moving at a high speed can more fully bombard the polymer and the residual film layer in the hole 110 to form the via hole 11.
Further, when the ICP etching apparatus is used as the etching apparatus, the power of the upper electrode thereof may be increased and/or the flow rate of the inert gas may be increased when step S05 is performed. For example, in performing step S04, the upper electrode power is set to 800W, and/or the etching gas flow rate is set to 120/20sccm (standard milliliters per minute); in performing step S05, the upper electrode power is increased to 1000W, and/or the inert gas flow rate is increased to 150 sccm.
In step S05, increasing the power of the upper electrode of the ICP etching apparatus and/or increasing the flow rate of the inert gas may ionize more inert gas into the inert gas plasma, so that more inert gas plasma may bombard the polymer and the residual film layer in the hole 110 to form the via hole 11.
For example, the inert gas is generally Ar gas because argon (Ar) has a low ionization potential and is easily ionized into plasma.
Since the insulating layer 7 serves to protect the first pattern 5, for example, to prevent the surface of the first pattern 5 from being oxidized in a subsequent process, an insulating material such as nitride, oxide, or oxynitride having a dense structure and high oxidation resistance at high temperature may be used.
The material of the insulating layer 7 is silicon dioxide, or silicon dioxide and silicon nitride.
When the insulating layer 7 comprises only a silicon dioxide insulating layer, the silicon dioxide insulating layer is typically etched with fluorocarbon gas and oxygen gas, depending on the nature of the silicon dioxide material. For convenience of description, the fluorocarbon gas and the oxygen gas will be referred to as a first etching gas hereinafter. The first etching gas etches the silicon dioxide insulating layer at a slow speed, so that the finally formed through hole 11 has a gentle side wall, and a pattern layer to be formed subsequently is formed in the through hole 11.
Correspondingly, step S04 is specifically:
etching a portion 73 of the silicon dioxide insulating layer corresponding to the via hole 11 to be formed by the first etching gas to form a hole 110 as shown in fig. 5(a) or 5 (b); wherein, the bottom of the hole 110 has a residual film layer with a predetermined thickness (marked as d in fig. 5 (b)); 0 < predetermined thickness < thickness of the silicon dioxide insulating layer (labeled as a in fig. 5 (b)).
The first etching gas reacts with the silicon dioxide insulating layer to generate fluorocarbon polymer, which is attached in the hole 110.
That is, when the thickness of the residual film layer is not zero, the fluorocarbon polymer is attached to the sidewall 110a and the bottom 110b of the hole 110 (i.e., the surface of the residual film layer);
when the predetermined thickness is 0, the fluorocarbon polymer is attached only to the sidewall 110a of the hole 110.
In order to facilitate a better understanding of the examples of the present application, the following description will be made of the process for forming fluorocarbon polymers:
fluorocarbon (CF)4，C4F8，CHF3Plasma) is often used to etch SiO2Si, and other related materials. CF (compact flash)4Decomposition into ionic CF in plasma state2With reactive F groups, see reaction formula (1), wherein CF2Can be mixed with SiO2(or Si) surface reaction to form (CF)2)nThe high molecular weight polymer is also referred to as fluorocarbon polymer, and is shown in the reaction formula (2). The reaction formula is as follows:
CF4→2F↑+CF2×) ×; reaction formula (1)
nCF2↑→(CF2)n(ii) a Reaction formula ((2)
CF4CF, CF in plasma2The radicals mainly result from the collision of electrons with the source gas, and in C4F8Wherein the CF is mainly from electron pair CF2The collision of (2) is resolved.
CF4Etching SiO2The process of (a) generally comprises three stages: firstly, the fluorocarbon film is on SiO2A deposition process on the surface of the insulating layer, followed by a process in which the growth of the fluorocarbon film is inhibited, and finally SiO2The process of etching the insulating layer is as follows: deposition of fluorocarbon polymers on SiO2Of (2) is provided. CF from fluorocarbon thin filmxRadicals with SiO2Reaction to form SiFxCO2Subsequently decomposed to SiF under bombardment by F atoms or ionsx. So that the fluorocarbon polymer is aligned with SiO2The etching effect is large.
Further, as shown in fig. 7, the insulating layer 7 may further include a silicon nitride insulating layer 72 disposed on the silicon dioxide insulating layer 71.
Because the silicon nitride material has better water resistance and permeability resistance compared with the silicon dioxide material, the manufactured array substrate has better water resistance and permeability resistance.
Sulfur-fluorine gas (e.g., SF) is typically selected based on the properties of the silicon nitride material6) And oxygen etching the silicon nitride insulating layer 72.
For convenience of description, the sulfurous fluorine gas and the oxygen gas will be referred to as a second etching gas hereinafter. The second etching gas etches the silicon nitride insulating layer 72 at a slower rate, so that the finally formed via hole 11 has a smoother sidewall, so that a pattern layer to be formed subsequently is formed in the via hole 11.
Accordingly, referring to fig. 7 to 9, the specific steps of step S04 include:
step S041, etching the portion 73 of the silicon nitride insulating layer 72 corresponding to the via 11 to be formed by using a second etching gas, so as to form a second hole 111 exposing the silicon dioxide insulating layer 71 as shown in fig. 8;
step S042, etching a portion of the silicon dioxide insulating layer 71 corresponding to the via 11 to be formed by the first etching gas, as shown in fig. 9, to form a first hole 112 (the dotted line L on the silicon dioxide insulating layer 71 in fig. 9)2The lower position).
In this process, the first etching gas continues to laterally etch the sidewall of the silicon nitride insulating layer 72, so that it is retracted to the periphery. First hole 111 (dotted line L in FIG. 9)1And L2In between) corresponds to the second hole 112, i.e. the first hole 111 and the second hole 112 together constitute the hole 110.
It should be noted that, in the above etching process, since the first etching gas etches the silicon nitride insulating layer 72 at a relatively high rate, if the silicon nitride insulating layer 72 is etched by the first etching gas, the sidewall of the via hole is relatively steep, which affects the contact between the second pattern to be formed subsequently and the first pattern 5, for example, makes the overlap joint between the pixel electrode and the drain electrode formed subsequently poor; since the second etching gas hardly etches the silicon dioxide insulating layer 71, the effect of etching the silicon nitride insulating layer 72 and the silicon dioxide insulating layer 71 by using the first etching gas or the second etching gas is unsatisfactory. Therefore, the silicon nitride insulating layer 72 is first etched by the second etching gas, and then the silicon dioxide insulating layer 71 is etched by the first etching gas, i.e., the insulating layers of different materials are etched using different etching gases
As shown in fig. 6(a) and 10(a), after the step of forming the via hole 11 exposing the first pattern 5, the method for manufacturing an array substrate further includes:
step S06, removing the protective pattern 12;
step S07, forming a second pattern 10 over the insulating layer 7; the second pattern 10 is in contact with the first pattern 5 through the via hole 11.
Specifically, the material of the protective pattern 12 may be a photoresist material. The photoresist protection pattern may be removed using a lift-off process.
Here, the second pattern 10 may include, but is not limited to, a pattern of a pixel electrode, which is not limited in this embodiment of the invention and may be flexibly adjusted according to a design requirement of an array substrate to be formed.
Referring to fig. 5(b), fig. 6(b) and fig. 10(b), in step S04, when 0 < the predetermined thickness < the thickness of the insulating layer, the bottom of the hole 110 has a residual film layer with a predetermined thickness; in step S05, the bottom of the via hole 11 after etching is formed with a step 74 having a height equal to the predetermined thickness due to the bombardment etching of the inert gas plasma perpendicular to the substrate surface. In order to prevent the second pattern 10 from crossing at the step 74 at the bottom of the via 11, a predetermined thickness (i.e., the height of the step 74, labeled as D in fig. 6 (b)) is required to be 1/8, and the film thickness of the second pattern (labeled as D in fig. 10 (b)) is required to be greater than or equal to 1/8, so that the second pattern 10 can sufficiently cover the step, and the second pattern 10 is prevented from generating a fault at the step and affecting the electrical connection with the first pattern 5.
As shown in fig. 11, before the step S02, the method for manufacturing an array substrate further includes:
sequentially forming a gate electrode 2, a gate insulating layer 3 covering the gate electrode, an oxide active layer 4 disposed on the gate insulating layer 3, and a source electrode 6 and a drain electrode 5 disposed on the gate insulating layer 3 and contacting the oxide active layer 4 on a substrate 1; the first pattern 5 is a drain electrode 5; the second pattern 10 is a pixel electrode 10; the bottom of the via hole is the upper surface of the drain electrode 5, and the pixel electrode 10 is electrically connected with the drain electrode 5 through the via hole.
The pixel electrode may be made of ITO (indium tin oxide) material.
It should be noted that, although the drain electrode of the thin film transistor is electrically connected to the pixel electrode in the embodiment of the present invention, it should be understood by those skilled in the art that the source electrode of the thin film transistor may be electrically connected to the pixel electrode due to the interchangeability of the structure and the composition of the source electrode and the drain electrode of the thin film transistor, which belongs to the equivalent transformation of the above embodiment of the present invention.
To further illustrate the present invention, the first pattern is used as a drain electrode; the second pattern is a pixel electrode; the insulating layer comprises a silicon dioxide insulating layer and a silicon nitride insulating layer; the material of the protective pattern is photoresist; the etching gas including a sulfur fluorine gas and an oxygen gas, and a fluorocarbon gas and an oxygen gas are used in conjunction with the specific embodiment to describe in detail the method for fabricating the array substrate according to the present invention.
It should be understood that the following examples are presented to illustrate the present invention and to provide a detailed description and specific examples, which are not intended to limit the scope of the present invention, but are provided to further illustrate the features and advantages of the present invention.
For simplicity of description, the area where the via needs to be etched is selected and described separately below.
a) Referring to fig. 7, a drain electrode 5 is formed over a substrate base plate 1; a silicon oxide insulating layer 71 is formed to cover the drain electrode 5, and a silicon nitride insulating layer 72 is formed to cover the silicon oxide insulating layer 71.
b) Referring to fig. 7, a photoresist mask layer pattern 12 of a via to be formed is formed on a silicon nitride insulating layer 72 by coating, exposing, and developing, so that the photoresist mask layer pattern 12 exposes a portion 73 of the insulating layer 7 where the via is to be formed.
c) Referring to fig. 8, using an ICP etcher as an etching apparatus, and using a sulfur fluorine gas and an oxygen gas as etching gases, etching a portion 73 of the silicon nitride insulating layer 72 corresponding to a via hole 11 to be formed, and forming a second hole 111 exposing the silicon dioxide insulating layer 72;
in this process, the upper electrode power of the ICP etching apparatus was set to 800W, the lower electrode power (self-bias) was set to 15W, and the sulfur fluorine gas and oxygen gas flow rates were set to 100/20 sccm.
d) Referring to fig. 9, after step c is completed, continuing to use an ICP etching apparatus as an etching apparatus, and using fluorocarbon gas and oxygen gas as etching gases to etch a portion of the silicon dioxide insulating layer 71 corresponding to the via hole 11 to be formed, until the remaining film thickness of the silicon dioxide insulating layer 71 is d, forming a first hole 112;
in this process, the upper electrode power of the ICP etching apparatus was set to 800W, the lower electrode power (self-bias) was set to 30W, and the flow rates of the fluorocarbon gas and oxygen gas were set to 120/20 sccm.
It should be noted that, in this process, the fluorocarbon gas and the oxygen gas will also continue to laterally etch the sidewall of the second hole 111 on the silicon nitride insulating layer 72, so that the sidewall of the second hole 111 continues to retract toward the periphery.
As can be seen from the foregoing description, the sidewall of the first hole 112 and the upper surface of the remaining film layer will generate fluorocarbon polymer which is difficult to be removed by the etching in step d.
e) As shown in fig. 12, after step d, continuing to use an ICP etching apparatus as an etching apparatus and Ar gas as a working gas to perform etching treatment on the hole 110 to remove the fluorocarbon polymer and the residual film layer until the upper surface of the drain 5 at the bottom is exposed, so as to form a via hole 11;
in this process, ICP upper electrode power was set to 1000W, lower electrode power (self bias) was set to 60W, and Ar flow was set to 150 sccm.
f) After step e is completed, the photoresist mask layer pattern 12 is removed, as shown in fig. 13.
g) As shown in fig. 14, after step f is completed, depositing an ITO film layer on the insulating layer 7, and performing a corresponding patterning process on the ITO film layer to form a pixel electrode 10; the pixel electrode 10 is electrically connected to the drain electrode 5 through the via hole 11. On the basis, the embodiment of the invention also provides the array substrate obtained by adopting the manufacturing method.
Based on this, in the array substrate obtained by the above manufacturing method, at the final stage of etching, that is, when the residual film layer at the bottom of the hole 110 reaches the preset thickness, the adjustment is performed by etching the hole 110 with inert gas, so that the polymer and the residual film layer generated by the reaction of the etching gas and the insulating layer 7 are removed, the via hole 11 is formed, and the second pattern to be formed subsequently contacts with the first pattern 5 through the via hole 11, thereby preventing the polymer formed in the via hole 11 during the etching process from affecting the electrical communication between the first pattern 5 and the second pattern 10.
For example, when the first pattern 5 is a drain and the second pattern 10 is a pixel electrode, the polymer generated in the via hole 11 during the etching process is removed from the array substrate obtained by the above manufacturing method, so that the polymer can be prevented from affecting the electrical connection between the pixel electrode and the drain, and the process yield is improved.
Specifically, the array substrate may further include other structures such as a common electrode, and the like, which may particularly follow the related art, and the embodiment of the present invention does not limit this.
Further, an embodiment of the present invention further provides a display device, including the array substrate.
The Display device can be a product or a component with any Display function, such as a liquid crystal panel, a liquid crystal Display, a liquid crystal television, an OLED (Organic Light-Emitting Display), an OLED television or electronic paper, a digital photo frame, a mobile phone, a tablet computer, and the like.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. The manufacturing method of the array substrate is characterized by comprising the following steps:
forming a first pattern over a substrate base plate;
forming an insulating layer covering the first pattern;
forming a protective pattern over the insulating layer, the protective pattern exposing a portion of the insulating layer where a via is to be formed;
etching the part to be formed with the via hole on the insulating layer by etching gas to form a hole, wherein the bottom of the hole is provided with a residual film layer with a preset thickness; wherein the preset thickness is more than 0 and less than the thickness of the insulating layer; a polymer generated by the reaction of the etching gas and the insulating layer is formed in the hole;
etching the hole through inert gas to remove the polymer and the residual film layer and form the via hole exposing the first pattern;
when the holes are etched by the inert gas, the bombardment energy of the inert gas is larger than that of the etching gas, and the method comprises the following steps:
and increasing the self-bias voltage of the etching equipment compared with the etching of the part to be formed with the via hole on the insulating layer by etching gas.
2. The method of claim 1, wherein the inert gas comprises Ar gas.
3. The method for manufacturing the array substrate according to claim 1, wherein the insulating layer comprises a silicon dioxide insulating layer; the etching gas includes: a first etching gas, wherein the first etching gas is composed of fluorocarbon gas and oxygen gas;
the etching the portion of the insulating layer where the via hole is to be formed by the etching gas includes:
etching a part, corresponding to the via hole to be formed, on the silicon dioxide insulating layer by using the first etching gas to form a first hole; the bottom of the first hole is provided with a residual film layer with a preset thickness; the preset thickness is more than 0 and less than the thickness of the silicon dioxide insulating layer; and a fluorocarbon polymer generated by the reaction of the first etching gas and the silicon dioxide insulating layer is formed in the first hole.
4. The method for manufacturing the array substrate according to claim 3, wherein the insulating layer further comprises: a silicon nitride insulating layer covering the silicon dioxide insulating layer; the etching gas further includes: a second etching gas, wherein the second etching gas is composed of sulfur-fluorine gas and oxygen;
before the etching, by the first etching gas, a portion of the silicon dioxide insulating layer corresponding to the via to be formed, the etching, by the etching gas, the portion of the insulating layer on which the via is to be formed further includes:
etching a part, corresponding to the via hole to be formed, on the silicon nitride insulating layer through the second etching gas to form a second hole exposing the silicon dioxide insulating layer;
the position of the first hole to be formed corresponds to the second hole; the hole is composed of the first hole and the second hole to be formed.
5. The method for manufacturing the array substrate according to claim 1, wherein after the step of forming the via hole exposing the first pattern, the method for manufacturing the array substrate further comprises:
removing the protective pattern;
forming a second pattern over the insulating layer;
the second pattern is in contact with the first pattern through the via hole.
6. The method for manufacturing the array substrate according to claim 5, wherein the bottom of the via hole has a step with a height equal to the preset thickness; the height of the step is less than or equal to 1/8 the film thickness of the second pattern.
7. The method for manufacturing an array substrate according to claim 6, wherein before the step of forming the insulating layer covering the first pattern, the method for manufacturing an array substrate further comprises:
sequentially forming a grid electrode, a grid insulation layer covering the grid electrode, an oxide active layer arranged on the grid insulation layer, a source electrode and a drain electrode which are arranged on the grid insulation layer and are in contact with the oxide active layer on the substrate base plate; the first pattern is the drain electrode; the second pattern is a pixel electrode.
8. The method for manufacturing an array substrate according to any one of claims 1 to 7, wherein the material of the protective pattern is a photoresist material.
9. An array substrate, wherein the array substrate is manufactured by the method for manufacturing an array substrate according to any one of claims 1 to 8.
10. A display device comprising the array substrate according to claim 9.
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| CN1501448A (en) * | 2002-11-19 | 2004-06-02 | 台湾积体电路制造股份有限公司 | Method for making contact hole on top of nickel silicide layer |
| CN1604288A (en) * | 2003-10-03 | 2005-04-06 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
| CN101452879A (en) * | 2007-12-05 | 2009-06-10 | 联华电子股份有限公司 | Cleaning method after opening etching |
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| CN1501448A (en) * | 2002-11-19 | 2004-06-02 | 台湾积体电路制造股份有限公司 | Method for making contact hole on top of nickel silicide layer |
| CN1604288A (en) * | 2003-10-03 | 2005-04-06 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
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