CN111129955B - Low-temperature plasma dry etching method and application thereof - Google Patents

Low-temperature plasma dry etching method and application thereof Download PDF

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CN111129955B
CN111129955B CN201911229068.6A CN201911229068A CN111129955B CN 111129955 B CN111129955 B CN 111129955B CN 201911229068 A CN201911229068 A CN 201911229068A CN 111129955 B CN111129955 B CN 111129955B
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CN111129955A (en
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武艳青
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CETC 13 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/3013—AIIIBV compounds

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Abstract

The invention relates to the technical field of micromachining etching, in particular to a low-temperature plasma dry etching method and application thereof. The method comprises the steps of carrying out dry etching on the ridge structure after the photoetching process is finished in an ICP device, and carrying out etching in four steps, namely removing the residual glue bottom film before etching, carrying out dry etching on the upper part of the dielectric layer, carrying out dry etching on the lower part of the dielectric layer, and removing residual glue and polymer. The etching method can keep the vertical etching morphology of the medium, reduce the ion bombardment on the window substrate and reduce the substrate lattice damage, thereby improving the carrier mobility and reducing the ohmic contact resistivity of the device.

Description

Low-temperature plasma dry etching method and application thereof
Technical Field
The invention relates to the technical field of micromachining etching, in particular to a low-temperature plasma dry etching method.
Background
Silicon dioxide (SiO)2) The etching process of the dielectric material is widely applied to the processing of semiconductor devices. In order to meet the requirements of the structure precision and the photoelectric performance of the micro-nano device, the etching morphology is often required to be accurately controlled, and the ion damage to the substrate is reduced as much as possible.
Inductively coupled ion etching (ICP) is a plasma dry etching technique that is widely used in the manufacturing process of optoelectronic devices at present, and can be used for etching dielectric materials such as silicon dioxide. The ICP has two groups of power supplies, namely an RF power supply consisting of an upper electrode and a lower electrode and a spiral LF power supply around a cavity, in order to pursue etching rate and control etching morphology in etching, the two groups of power supplies can be used in a matched mode, but medium residue ears are generated on two sides of the ridge after etching, or a medium protective layer on the side face of the ridge is etched due to the fact that the etching method is relatively fast to photoresist, and serious ion damage is caused to a window substrate. The etched appearances of the ear and the medium on the two sides of the ridge are shown in the figure 1-a/1-b respectively. If the method is used for etching the P-type ohmic contact window of the ridge waveguide structure semiconductor laser, the resistivity of the P-type ohmic contact is increased to 10 after annealing-5Ω·cm2。
Disclosure of Invention
Aiming at the problems that ICP can cause medium residue ears on two sides of a ridge, a medium protection layer on the side surface of the ridge is etched and ion damage is caused to a window substrate, the invention provides a low-temperature plasma dry etching method.
The invention also provides application of the low-temperature plasma dry etching method in an etching process of a P-type ohmic contact window of a ridge-type semiconductor laser with a window substrate material comprising indium, gallium and arsenic.
In order to achieve the purpose of the invention, the embodiment of the invention adopts the following technical scheme:
a low-temperature plasma dry etching method is characterized in that a dielectric layer is deposited on a substrate with a ridge structure, the substrate is made of a window base material including indium, gallium and arsenic, the substrate is coated with glue, exposed, developed and hardened after the dielectric layer is deposited, photoresist right above the ridge structure in the substrate is developed, photoresist in grooves in two sides of the ridge structure is reserved, and dry etching is carried out on the substrate after the substrate is hardened by using inductive coupling ion etching equipment, wherein the dry etching method comprises the following steps:
s1, removing the residual adhesive film right above the ridge-shaped structure;
s2, etching under the first process condition until the residual thickness of the dielectric layer right above the ridge-shaped structure is equal to
Figure BDA0002303028910000021
Wherein the physical etching is greater than the chemical etching in the first process condition;
s3, etching under a second process condition until the dielectric layer right above the ridge-shaped structure is over-etched, wherein the chemical etching is larger than the physical etching in the second process condition;
and S4, removing residual glue and etching products.
Optionally, the thickness of the photoresist is 0.8 μm to h, where h is a ridge height in the ridge structure.
Optionally, the inductively coupled ion etching apparatus uses at least four etching gases including oxygen (O)2) Trifluoromethane (CHF)3) Sulfur hexafluoride (SF)6) And argon (Ar); the pressure of the chamber is 5 mTorr-20 mTorr.
Optionally, the inductively coupled ion etching apparatus uses helium as a cooling gas for the chassis.
Optionally, the purity of the gas is greater than or equal to 99.999%.
Optionally, the parameters for removing the residual adhesive film in S1 are: RF power: 200W plus or minus 10W; helium flow rate: 13sccm +/-2 sccm; the oxygen flow is 50sccm +/-2 sccm; chamber pressure: 15mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃.
Optionally, the parameters of the etching in S2 are: RF power: 200W plus or minus 10W; oxygen flow rate: 3sccm +/-2 sccm; helium flow rate: 13sccm +/-2 sccm; flow rate of trifluoromethane: 30sccm +/-2 sccm; argon flow: 10sccm +/-2 sccm; chamber pressure: 20mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃.
Optionally, the parameters of the etching in S3 are: LF power: 1000W +/-15W; helium flow rate: 13sccm +/-2 sccm; flow of sulfur hexafluoride: 45sccm +/-2 sccm; chamber pressure: 10mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃. This step is performed on the remaining SiO2The dielectric is etched and proper over-etching is required to ensure that the dielectric is completely etched through.
Optionally, the parameters for removing the residual glue and the polymer by using the oxygen plasma in S4 are as follows: LF power: 800W +/-15W; helium flow rate: 13sccm +/-2 sccm; the oxygen flow is 100sccm +/-2 sccm; chamber pressure: 10mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃.
The embodiment of the invention also provides application of the low-temperature plasma dry etching method in an etching process of a P-type ohmic contact window of a ridge waveguide semiconductor laser with the window substrate material comprising indium, gallium and arsenic. The etching method is used for etching the P-type ohmic contact window of the ridge waveguide semiconductor laser with the window substrate material comprising indium, gallium and arsenic, so that the ohmic contact resistivity of the device can be reduced, and the reliability of the device can be improved.
Adopt the produced beneficial effect of above-mentioned technical scheme to lie in: the etching method can reach the thickness of the dielectric layer
Figure BDA0002303028910000031
Selecting different etching process conditions before and after, namely firstly carrying out high-damage etching under the first process condition that the physical etching is larger than the chemical etching to realize vertical etching without influencing the side wall, and then carrying out low-damage etching under the second process condition that the chemical etching is larger than the physical etching, wherein the side wall is etched under the second process conditionPart will react away in the next place, but
Figure BDA0002303028910000032
The side wall reaction is not completed under the etching time of the thickness of the dielectric layer, so that the method not only can keep the vertical etching appearance of the dielectric layer, but also can reduce the ion bombardment on the window substrate made of the substrate material including indium, gallium and arsenic, and reduce the crystal lattice damage of the substrate, thereby improving the carrier mobility and reducing the ohmic contact resistivity of the device. The method can be applied to etching the P-type ohmic contact window of the ridge waveguide semiconductor laser with the window substrate material comprising indium, gallium and arsenic.
Drawings
FIG. 1-a the conventional etching method produces ears on both sides of the ridge after etching;
FIG. 1-b illustrates the dielectric on both sides of the ridge being etched after the conventional etching;
FIG. 2 is a flow chart of a low-temperature plasma dry etching method according to an embodiment of the present invention;
FIG. 3 is a schematic view of the topography of the present invention, wherein (a) is the topography of FIG. 2 after step 202 is completed, (b) is the topography of FIG. 2 after step 203 is completed, and (c) is the topography of FIG. 2 after step 204 is completed;
fig. 4 to 7 are actual topography maps according to an embodiment of the present invention, where fig. 4 is an actual topography map after step S1 is completed, fig. 5 is an actual topography map after step S2 in fig. 2 is completed, fig. 6 is an actual topography map after step S3 in fig. 2 is completed, and fig. 7 is an actual topography map after step S4 in fig. 2 is completed.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Referring to fig. 2, an embodiment of the present invention provides a low temperature plasma dry etching method, including the following steps:
step 200, depositing a dielectric layer on the substrate with the ridge structure, wherein the material of the window base comprises indium, gallium and arsenic, gluing, exposing, developing and hardening the substrate after the dielectric layer is deposited, so that the photoresist right above the ridge structure in the substrate is developed, and the photoresist in the grooves at the two sides of the ridge structure is reserved. Placing the obtained substrate in an inductively coupled ion etching device for dry etching;
step 201, removing a residual adhesive film right above a ridge structure;
step 202, etching under the first process condition until the residual thickness of the dielectric layer right above the ridge structure is
Figure BDA0002303028910000041
Wherein the physical etching is greater than the chemical etching in the first process condition;
step 203, etching under a second process condition until the dielectric layer right above the ridge-shaped structure is over-etched, wherein the chemical etching is larger than the physical etching in the second process condition;
and step 204, removing residual glue and etching products.
The etching method can reach the thickness of the dielectric layer
Figure BDA0002303028910000042
Selecting different etching process conditions before and after, namely firstly carrying out high damage etching under a first process condition that the physical etching is larger than the chemical etching to realize vertical etching without influencing the side wall, and then carrying out low damage etching under a second process condition that the chemical etching is larger than the physical etching, wherein the side wall can react to remove a part under the second process condition, but the side wall can react to remove the part under the second process condition
Figure BDA0002303028910000043
The side wall of the dielectric layer is not completely reacted in the etching time of the thickness of the dielectric layer, so that the method can not only keep the vertical etching appearance of the dielectric layer, but also reduce the ion bombardment on the window substrate made of substrate materials including indium, gallium and arsenic, and reduce the crystal lattice damage of the substrate, thereby improving the mobility of current carriers and reducing the deviceOhmic contact resistivity. The method can be applied to etching the P-type ohmic contact window of the ridge waveguide semiconductor laser with the window substrate material comprising indium, gallium and arsenic.
The dielectric layer may be selected from silicon dioxide or silicon nitride.
Referring to fig. 4, in another embodiment, the photoresist has a thickness of 0.8 μm to h, where h is the ridge height in the ridge structure. The thickness can ensure that the media on the two sides of the ridge structure are not etched and no 'ears' are left on the two sides of the ridge structure after etching. The coating has wider thickness range, reduces the requirement on the precision of the exposure process, and is beneficial to improving the production rate and reducing the production cost. And after hardening, carrying out dry etching on the ridge structure.
In another embodiment, the inductively coupled ion etching apparatus uses at least four etching gases, including oxygen, trifluoromethane, sulfur hexafluoride, and argon; the pressure of the chamber of the inductive coupling ion etching equipment is 5 mTorr-20 mTorr.
In another embodiment, the inductively coupled ion etching apparatus uses helium as a cooling gas for the chassis.
In another embodiment, the purity of the gas is greater than or equal to 99.999%.
In another embodiment, the parameters for removing the residual adhesive film in step 201 are as follows: RF power: 200W plus or minus 10W; helium flow rate: 13sccm +/-2 sccm; oxygen flow rate: 50sccm +/-2 sccm; chamber pressure: 15mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃. This step is achieved by relying on high concentrations of O2The plasma reacts with the photoresist with C, H, O as the main component element to remove the residual photoresist, so as to prevent the residual photoresist film on the top of the ridge structure from influencing the stability of etching between batches and the smoothness of the window substrate, and the by-products of the production can be discharged by a cavity air exhaust system of the inductively coupled ion etching equipment.
In another embodiment, the parameters of the etching in step 202 are: RF power: 200W plus or minus 10W; oxygen flow rate: 3sccm +/-2 sccm; helium flow rate: 13sccm +/-2 sccm; flow rate of trifluoromethane: 30sccm +/-2 sccm; argon flow: 10sccm +/-2 sccm; chamber pressure: 20mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃. This step employs reactive ion etchingIn this way, the RF source of the device is selected mainly based on physical bombardment, which can keep the vertical etching of the medium to the maximum extent and protect the exposed medium at the two sides of the ridge from side etching, and the RF source is left as the RF source after the step is finished
Figure BDA0002303028910000051
Thick SiO2The medium, so ion damage to the window substrate due to high energy physical bombardment is avoided.
In another embodiment, the etching parameters in step 203 are: LF power: 1000W +/-15W; helium flow rate: 13sccm +/-2 sccm; flow of sulfur hexafluoride: 45sccm +/-2 sccm; chamber pressure: 10mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃. The etching of the step directly determines the etching morphology of the medium and the damage degree to the window substrate on the ridge, so that the etching equipment LF source is mainly used for chemical reaction etching, the physical bombardment effect is very small, and the ion damage to the window substrate can be greatly reduced. When the dielectric layer is silicon dioxide, the chemical reaction etching equation is as follows: SiO 22+SF6→SiF4+SO2. The etching mode exposes the uncovered areas of the photoresist on the two sides of the ridge2Has side etching effect, but due to residual SiO2Is thin and does not affect the protection even if a small amount of etching is carried out on the side surface.
In another embodiment, the parameters for removing the residual glue and the polymer by using the oxygen plasma in step 204 are as follows: LF power: 800W +/-15W; helium flow rate: 13sccm +/-2 sccm; the oxygen flow is 100sccm +/-2 sccm; chamber pressure: 10mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃. The window substrate is exposed after the etching process of step 203, but the photoresist and the polymer generated during the etching process need to be removed, and the high concentration O generated by LF is also used for controlling the ion damage2And removing residual glue by using the plasma.
The embodiment of the invention also discloses application of the low-temperature plasma dry etching method in an etching process of a P-type ohmic contact window of a ridge waveguide structure semiconductor laser with a window substrate material comprising indium, gallium and arsenic, and the real topography of the specific embodiment refers toReferring to FIG. 4, the substrate is a 3 inch wafer with ridge height of 1.8 μm + -0.1 μm and base material of indium, gallium and arsenic. Depositing on the wafer
Figure BDA0002303028910000061
SiO2And then, carrying out processes of gluing, exposing, developing and hardening to develop the photoresist right above the ridge-shaped structure in the wafer, and reserving the photoresist in the grooves at the two sides of the ridge-shaped structure. When gluing, the glue thickness of the two sides of the ridge is controlled to be 0.8-1.8 μm (as shown in figure 4). After hardening, the wafer is placed into an ICP equipment transfer chamber, the wafer is sent into a main etching chamber through a robot arm in the transfer chamber, the etching program is divided into four steps, and the programming program is as follows:
step S1, setting ICP equipment parameters as: RF power: 200W plus or minus 10W; he flow rate: 13sccm +/-2 sccm; o is2The flow rate is 50sccm +/-2 sccm; chamber pressure: 15mTorr +/-2 mTorr; setting the temperature of the chassis: 25 +/-2 ℃; the photoresist stripping time is 3 min.
Step S2, setting ICP equipment parameters as: RF power: 200W plus or minus 10W; o is2Flow rate: 3sccm +/-2 sccm; he flow rate: 13 sccm; CHF3Flow rate: 30sccm +/-2 sccm; ar flow rate: 10sccm +/-2 sccm; chamber pressure: 20mTorr +/-2 mTorr; setting the temperature of the chassis: 25 +/-2 ℃; the etching time is 8min, and the ridge morphology after the etching is shown in figure 5.
Step S3, setting ICP equipment parameters as: LF power: 1000W +/-15W; he flow rate: 13sccm +/-2 sccm; SF6Flow rate: 45sccm +/-2 sccm; ar flow rate: 10sccm +/-2 sccm; chamber pressure: 10mTorr +/-2 mTorr; setting the temperature of the chassis: 25 +/-2 ℃; the etching time is 1.5min, and the ridge morphology after the etching is shown in figure 6.
Step S4, setting ICP equipment parameters as: LF power: 800W +/-15W; o is2Flow rate: 100sccm +/-2 sccm; he flow rate: 13sccm +/-2 sccm; chamber pressure: 10mTorr +/-2 mTorr; setting the temperature of the chassis: 25 +/-2 ℃; the etching time is 5min, and the ridge morphology after the etching is shown in FIG. 7.
Using the dielectric window of the obtained ridge-type structure wafer for P-type ohmic contact of the ridge waveguide semiconductor laser, and annealing to ensure that the ohmic contact resistivity is 10-5Ω·cm2Down to 10-7Ω·cm2And the device reliability is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents or improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A low-temperature plasma dry etching method is characterized in that a dielectric layer is deposited on a substrate with a ridge structure, the material of a window base comprises indium, gallium and arsenic, the substrate after the dielectric layer is deposited is subjected to gluing, exposure, development and hardening, photoresist right above the ridge structure in the substrate is developed, the photoresist in grooves at two sides of the ridge structure is reserved, and dry etching is carried out on the substrate after the hardening by using an inductive coupling ion etching device, wherein the dry etching comprises the following steps:
s1, removing the residual adhesive film right above the ridge-shaped structure;
s2, etching under the first process condition until the residual thickness of the dielectric layer right above the ridge-shaped structure is equal to
Figure FDA0002943909580000011
Wherein, the physical etching is larger than the chemical etching in the first process condition, so that the vertical etching is realized without influencing the side wall;
s3, etching under a second process condition until the dielectric layer right above the ridge structure is over-etched, wherein the chemical etching is larger than the physical etching in the second process condition, the side wall reacts a part but does not completely react, the vertical etching morphology of the dielectric layer is maintained, the ion bombardment on a window substrate made of substrate materials including indium, gallium and arsenic is reduced, and the substrate lattice damage is reduced;
and S4, removing residual glue and etching products.
2. The low-temperature plasma dry etching method according to claim 1, wherein the dielectric layer is silicon dioxide or silicon nitride; and/or
The thickness of the photoresist is 0.8 mu m-h, and h is the ridge height in the ridge structure.
3. The low-temperature plasma dry etching method according to claim 1, wherein the inductively coupled ion etching apparatus uses at least four etching gases including oxygen, trifluoromethane, sulfur hexafluoride, and argon; the chamber pressure of the inductive coupling ion etching equipment is 5 mTorr-20 mTorr.
4. The method according to claim 3, wherein the inductively coupled ion etching apparatus uses helium as a cooling gas for a chassis.
5. The low-temperature plasma dry etching method according to claim 3 or 4, wherein the purity of the gas is not less than 99.999%.
6. The method according to claim 4, wherein the parameters for removing the residual adhesive film in S1 are as follows: RF power: 200W plus or minus 10W; helium flow rate: 13sccm +/-2 sccm; oxygen flow rate: 50sccm +/-2 sccm; chamber pressure: 15mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃.
7. The low-temperature plasma dry etching method according to claim 4, wherein the etching parameters in S2 are as follows: RF power: 200W plus or minus 10W; oxygen flow rate: 3sccm +/-2 sccm; helium flow rate: 13sccm +/-2 sccm; flow rate of trifluoromethane: 30sccm +/-2 sccm; argon flow: 10sccm +/-2 sccm; chamber pressure: 20mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃.
8. The low-temperature plasma dry etching method according to claim 4, wherein the etching parameters in S3 are as follows: LF power: 1000W +/-15W; helium flow rate: 13sccm +/-2 sccm; flow of sulfur hexafluoride: 45sccm +/-2 sccm; chamber pressure: 10mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃.
9. The method according to claim 4, wherein the removing the residual photoresist and the etching product in S4 is removing the residual photoresist and the polymer by using oxygen plasma, and the parameters of removing the residual photoresist and the polymer by using the oxygen plasma are as follows: LF power: 800W +/-15W; helium flow rate: 13sccm +/-2 sccm; the oxygen flow is 100sccm +/-2 sccm; chamber pressure: 10mTorr +/-2 mTorr; temperature of the chassis: 25 ℃ plus or minus 2 ℃.
10. The application of the low-temperature plasma dry etching method as claimed in any one of claims 1 to 9 in an etching process of a P-type ohmic contact window of a ridge waveguide semiconductor laser with a window substrate material including indium, gallium and arsenic.
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CN115097570B (en) * 2022-08-22 2023-04-07 上海羲禾科技有限公司 Waveguide etching method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1439598A (en) * 2003-03-21 2003-09-03 中国电子科技集团公司第十三研究所 Dry deeply etching silicone wafer manufacture
CN1933263A (en) * 2006-10-13 2007-03-21 中国科学院上海微系统与信息技术研究所 Method for raising III-V family strain multi-quantum pit luminous intensity
CN103854992A (en) * 2012-11-30 2014-06-11 北京北方微电子基地设备工艺研究中心有限责任公司 Substrate etching method
CN104253017A (en) * 2013-06-27 2014-12-31 北京北方微电子基地设备工艺研究中心有限责任公司 Substrate etching method
CN104282548A (en) * 2014-09-12 2015-01-14 电子科技大学 Etching method for III-V-group compound semiconductor materials
CN104752159A (en) * 2013-12-31 2015-07-01 北京北方微电子基地设备工艺研究中心有限责任公司 Substrate etching method
CN108847573A (en) * 2018-06-27 2018-11-20 湖北光安伦科技有限公司 Vertical cavity surface emitting laser and preparation method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719498A (en) * 1984-05-18 1988-01-12 Fujitsu Limited Optoelectronic integrated circuit
FR2744225B1 (en) * 1996-01-25 1998-05-07 Menigaux Louis PROCESS FOR THE PRODUCTION OF A 45 DEGREE INCLINED PLAN ON A 3-5 CRYSTAL COMPONENT AND OPTICAL COMPONENT
JPH10242573A (en) * 1997-02-25 1998-09-11 Sharp Corp Formation of reflector end surface of nitride semiconductor
CN106684061B (en) * 2016-12-14 2019-01-25 中国电子科技集团公司第五十五研究所 A kind of production method of indium phosphide dorsal pore

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1439598A (en) * 2003-03-21 2003-09-03 中国电子科技集团公司第十三研究所 Dry deeply etching silicone wafer manufacture
CN1933263A (en) * 2006-10-13 2007-03-21 中国科学院上海微系统与信息技术研究所 Method for raising III-V family strain multi-quantum pit luminous intensity
CN103854992A (en) * 2012-11-30 2014-06-11 北京北方微电子基地设备工艺研究中心有限责任公司 Substrate etching method
CN104253017A (en) * 2013-06-27 2014-12-31 北京北方微电子基地设备工艺研究中心有限责任公司 Substrate etching method
CN104752159A (en) * 2013-12-31 2015-07-01 北京北方微电子基地设备工艺研究中心有限责任公司 Substrate etching method
CN104282548A (en) * 2014-09-12 2015-01-14 电子科技大学 Etching method for III-V-group compound semiconductor materials
CN108847573A (en) * 2018-06-27 2018-11-20 湖北光安伦科技有限公司 Vertical cavity surface emitting laser and preparation method thereof

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