CN108987337A - A kind of array substrate and preparation method thereof, display device - Google Patents
A kind of array substrate and preparation method thereof, display device Download PDFInfo
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- CN108987337A CN108987337A CN201811027840.1A CN201811027840A CN108987337A CN 108987337 A CN108987337 A CN 108987337A CN 201811027840 A CN201811027840 A CN 201811027840A CN 108987337 A CN108987337 A CN 108987337A
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- 239000000758 substrate Substances 0.000 title claims abstract description 69
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 138
- 239000007789 gas Substances 0.000 claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 claims abstract description 38
- 239000011261 inert gas Substances 0.000 claims abstract description 34
- 229920000642 polymer Polymers 0.000 claims abstract description 31
- 230000004224 protection Effects 0.000 claims abstract description 21
- 238000012545 processing Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 187
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- 239000000377 silicon dioxide Substances 0.000 claims description 55
- 235000012239 silicon dioxide Nutrition 0.000 claims description 36
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 26
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 19
- 239000001301 oxygen Substances 0.000 claims description 19
- 229910052760 oxygen Inorganic materials 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 16
- 229920002313 fluoropolymer Polymers 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 8
- XGCDHPDIERKJPT-UHFFFAOYSA-N [F].[S] Chemical compound [F].[S] XGCDHPDIERKJPT-UHFFFAOYSA-N 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000003491 array Methods 0.000 claims 1
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- 239000010409 thin film Substances 0.000 description 6
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 229910003978 SiClx Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
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- 239000004973 liquid crystal related substance Substances 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
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- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 241000790917 Dioxys <bee> Species 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- 229910001882 dioxygen Inorganic materials 0.000 description 1
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- 230000003628 erosive effect Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- 150000004767 nitrides Chemical class 0.000 description 1
- -1 oxide Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The embodiment of the invention provides a kind of array substrates and preparation method thereof, display device, it is related to field of display technology, the production method eliminates the polymer formed in etching process in via hole, the adverse effect so as to avoid the polymer to the electrical communication of first pattern and the second pattern.The production method includes: that the first pattern is formed above underlay substrate；Form the insulating layer of the first pattern of covering；Rectangular at protection pattern on the insulating layer, protection pattern exposes the part of via hole to be formed on insulating layer；By the part of the via hole to be formed on etching gas etching insulating layer, hole is formed, the bottom of hole has the residual film layer of preset thickness；Wherein, the thickness of 0≤preset thickness < insulating layer；It is formed with etching gas in hole and reacts the polymer generated with insulating layer；Processing is performed etching to hole by inert gas, to remove polymer and residual film layer, forms the via hole for exposing the first pattern.The array substrate is for making display device.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrate and preparation method thereof, display device.
Background technique
Thin film transistor (TFT) (Thin Film Transistor, abbreviation TFT) can be used as the pixel switch member of flat-panel monitor
Part.TFT can point be: non-crystalline silicon tft, polysilicon by the different materials according to used by the active layer in thin-film transistor structure
TFT, monocrystalline silicon TFT and oxide semiconductor TFT；Wherein, non-crystalline silicon tft active layer can be easy deposition on large regions and
It is easy to process under cryogenic, but has the shortcomings that charge mobility is low；Although multi-crystal TFT active layer charge migration
It is high, with excellent electrical characteristics, but need to process under the high temperature conditions and its reliable consistency is unstable；Oxide is partly led
Body (such as IGZO, indium gallium zinc oxide, indium gallium zinc oxide) TFT carrier mobility with higher,
The driving requirement of the liquid crystal display of oversize can preferably be met, also, oxide semiconductor TFT also has component equal
One, the features such as cost is relatively low, transparent rate is higher, therefore by the concern of research staff.
In the prior art, used when due to preparing silicon nitride dielectric layer for oxide semiconductor tft array substrate
H element in gas has reproducibility to oxide trenches, can lead to Lacking oxygen and increases and make oxide active layer conductor, institute
Silica membrane or silica and silicon nitride laminated film are selected with usual insulating protective layer.
For simplification of flowsheet, generallys use dry etching and produce via hole through insulating protective layer, the bottom of via hole
For the upper surface of drain electrode.Usually utilize carbon fluorine gas (such as CF4) and oxygen be etching gas etching silicon dioxide film, carving
During erosion, growth has a large amount of fluorocarbon polymer in the via hole of silica material, and fluorocarbon polymer is different, and rear
It can not be easily removed during continuous, thus will affect the electric connection of pixel electrode and drain electrode, to cause display
It shows bad.
Summary of the invention
To solve above-mentioned the problems of the prior art, the embodiment of the invention provides a kind of array substrate and its production sides
Method, display device.The production method eliminates the polymer formed in the vias in etching process, so as to avoid the polymer
Adverse effect to the electrical communication of first pattern and the second pattern.In order to achieve the above objectives, the embodiment of the present invention is using such as
Lower technical solution:
On the one hand, the embodiment of the invention provides a kind of production method of array substrate, the production sides of the array substrate
Method includes: that the first pattern is formed above underlay substrate；Form the insulating layer for covering first pattern；On the insulating layer
It is rectangular at protection pattern, the protection pattern exposes the part of via hole to be formed on the insulating layer；It is etched by etching gas
The part of the via hole to be formed on the insulating layer, forms hole, and the bottom of described hole has the residual of preset thickness
Film layer；Wherein, 0 the thickness of insulating layer described in the≤preset thickness <；The etching gas and institute are formed in described hole
State the polymer that insulating layer reaction generates；Processing is performed etching to described hole by inert gas, to remove the polymer
With the residual film layer, the via hole for exposing first pattern is formed.
Optionally, described when performing etching processing to described hole by inert gas, the bombardment energy of the inert gas
Amount is greater than the bombarding energy of the etching gas.
Optionally, described when performing etching processing to described hole by inert gas, the bombardment energy of the inert gas
Amount is greater than the bombarding energy of the etching gas, comprising: compared to described in being etched on the insulating layer by etching gas to
When forming the part of via hole, increase the automatic bias of etching apparatus.
Optionally, the inert gas includes Ar gas.
Optionally, the insulating layer includes silicon dioxide insulating layer；The etching gas includes: the first etching gas, institute
The first etching gas is stated to be made of carbon fluorine gas and oxygen；It is described by etching gas etch on the insulating layer described in shape
Part at via hole include: by first etching gas etch on the silicon dioxide insulating layer correspond to it is described to shape
At the part of via hole, the first hole is formed；Wherein, the bottom of first hole has the residual film layer of preset thickness；0≤institute
State the thickness of silicon dioxide insulating layer described in preset thickness <；First etching gas and institute are formed in first hole
State the fluorocarbon polymer that silicon dioxide insulating layer reaction generates.
Optionally, the insulating layer further include: the silicon nitride dielectric layer being covered on above the silicon dioxide insulating layer；Institute
State etching gas further include: the second etching gas, second etching gas are made of sulphur fluorine gas and oxygen；Pass through described
It is described before first etching gas etches the part corresponding to the via hole to be formed on the silicon dioxide insulating layer
The part of the via hole to be formed on the insulating layer is etched by etching gas further include: pass through second etching gas
The part corresponding to the via hole to be formed on the silicon nitride dielectric layer is etched, is formed and exposes the silicon dioxide insulating layer
The second hole；The position of first hole to be formed corresponds to second hole；Described hole is by first hole
Hole and second hole to be formed are constituted.
Optionally, after described the step of forming the via hole for exposing first pattern, the array substrate
Production method further include: remove the protective layer；The second pattern is formed above the insulating layer；Second pattern passes through institute
Via hole is stated to be in contact with first pattern.
Optionally, the thickness of insulating layer described in preset thickness < described in 0 <；There is height to be equal to institute for the bottom of the via hole
State the step of preset thickness；The thicknesses of layers of height≤1/8 of the step second pattern.
Optionally, before described the step of forming the insulating layer for covering first pattern, the production of the array substrate
Method further include: it is exhausted in the grid that grid, the gate insulation layer of the covering grid, setting are sequentially formed on the underlay substrate
Oxide active layer in edge layer, the source electrode for being arranged on the gate insulation layer and being in contact with the oxide active layer and leakage
Pole；First pattern is the drain electrode；Second pattern is pixel electrode.
Optionally, the material of the protection pattern is Other substrate materials.
On the other hand, the embodiment of the invention also provides a kind of array substrate, the array substrate passes through described above
The production method of array substrate is made.
In another aspect, the display device includes described above the embodiment of the invention also provides a kind of display device
Array substrate.
Based on this, the above-mentioned production method provided through the embodiment of the present invention is first due to during etching insulating layer
It is performed etching first with etching gas, then in the final stage of etching, i.e., when the residual film layer of the bottom of hole reaches default
It when thickness, is adjusted to perform etching processing to hole using inert gas, reacts generation to remove etching gas with insulating layer
Polymer and residual film layer, form via hole, subsequent second pattern to be formed is in contact by via hole with the first pattern, to keep away
Having exempted from the polymer formed in via hole influences the electrical communication of first pattern and the second pattern.
For example, when the second pattern is pixel electrode, being formed in the avoidable via hole of the above method when the first pattern is drain electrode
Polymer influence pixel electrode is electrically connected with drain electrode, improves process rate.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of array substrate schematic diagram in the related art；
Fig. 2 is in the related art, after carbon fluorine gas and oxygen etching silicon dioxide insulating layer, to cross hole surface life
Electronic Speculum schematic diagram with a large amount of fluorocarbon polymer；
Fig. 3 is a kind of flow diagram of the production method of array substrate provided in an embodiment of the present invention；
Fig. 4 is a kind of result schematic diagram completed after step S03；
Fig. 5 (a) is a kind of result schematic diagram for completing step S04 in Fig. 3；
Fig. 5 (b) is another result schematic diagram for completing step S04 in Fig. 3；
Fig. 6 (a) is to complete the result schematic diagram of step S05 in the structure basis shown in Fig. 5 (a)；
Fig. 6 (b) is to complete the result schematic diagram of step S05 in the structure basis shown in Fig. 5 (b)；
Fig. 7 is another result schematic diagram for completing step S03；
Fig. 8 is to complete the result schematic diagram of step S041 in structure basis shown in Fig. 7；
Fig. 9 is to complete the result schematic diagram of step S042 in structure basis shown in Fig. 8；
Figure 10 (a) is to complete the result schematic diagram of step S07 in the structure basis shown in Fig. 6 (a)；
Figure 10 (b) is to complete the result schematic diagram of step S07 in the structure basis shown in Fig. 6 (b)；
Figure 11 is a kind of a kind of prepared array of production method of the array substrate provided through the embodiment of the present invention
Substrate schematic diagram；
Figure 12 is that a kind of production method of the array substrate provided through the embodiment of the present invention makes a kind of specific array base
Result schematic diagram during plate, after completing step e；
Figure 13 is that a kind of production method of the array substrate provided through the embodiment of the present invention makes a kind of specific array base
Result schematic diagram during plate, after completing step f；
Figure 14 is that a kind of production method of the array substrate provided through the embodiment of the present invention makes a kind of specific array base
Result schematic diagram during plate, after completing step g.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
It should be pointed out that " first " used in present patent application specification and claims, " the
Two " and similar word be not offered as any sequence, quantity or importance, and be used only to distinguish different composition portions
Point.In the description of the present invention, it is to be understood that, the orientation or positional relationship of the instructions such as term " on ", "lower" is based on attached
Orientation or positional relationship shown in figure, is merely for convenience of description of the present invention and simplification of the description, rather than indication or suggestion is signified
Device or element must have a particular orientation, specific orientation construction and operation, therefore should not be understood as to of the invention
Limitation.
In the related art, as shown in Figure 1, oxide semiconductor tft array substrate includes: underlay substrate 1, grid 2, grid
Pole insulating layer 3, active layer 4, drain electrode 5, source electrode 6, silicon dioxide insulating layer 71, silicon nitride dielectric layer 72, organic insulator 8, public affairs
Common electrode 9, pixel electrode 10.
Wherein, grid 2, active layer 4, drain electrode 5, source electrode 6 constitute TFT.
In oxide semiconductor tft array substrate, the material of insulating layer 7 usually selects conventional silica or two
Silica and silicon nitride.
Refering to what is shown in Fig. 1, when the material selection silica and silicon nitride of insulating layer 7, due to silicon nitride layer 72 with have
The directly contact of active layer 4 is easy to cause 4 conductor of active layer, so, select silicon dioxide layer 71 to be directly in contact with active layer 4,
Silicon nitride layer 72 is re-formed on silicon dioxide layer 71.
For simplification of flowsheet, generallys use dry etching and produce via hole 11 through insulating layer 7, the bottom of via hole 11
Expose the upper surface of drain electrode 5.
Usually select carbon fluorine gas (such as CF4) and oxygen silicon dioxide layer 71 is performed etching as working gas.?
During etching, as shown in Fig. 2, since carbon fluorine gas and oxygen react with silicon dioxide layer 71, so that silica
The grown on interior walls of 71 via holes has a large amount of fluorocarbon polymer, and cannot remove removal easily in the follow-up process, thus
Meeting is so that the pixel electrode 10 being subsequently formed and 5 overlap joint of drain electrode are bad, to cause to show bad.
In order to solve the above technical problems, the embodiment of the invention provides a kind of production method of array substrate, such as Fig. 3 institute
Show, which includes 5 steps, it is illustrated below with reference to key step of Fig. 4~Fig. 6 to the production method:
Step S01, the first pattern 5 is formed above underlay substrate 1；
Step S02, the insulating layer 7 of the first pattern 5 of covering is formed；
Step S03, as shown in figure 4, forming protection pattern 12 above insulating layer 7, protection pattern 12 exposes on insulating layer 7
The part 73 of via hole to be formed；
Step S04, by the part 73 of the via hole to be formed on etching gas etching insulating layer 7, formed such as Fig. 5 (a) or
Hole 110 shown in Fig. 5 (b), the bottom of hole 110 have the residual film layer of preset thickness (label is in Fig. 5 (b))；Its
In, the thickness of 0≤preset thickness < insulating layer (label is in Fig. 5 (b))；Etching gas and insulating layer are formed in hole 110
The polymer that 7 reactions generate；
Step S05, processing is performed etching to hole 110 by inert gas, to remove polymer and residual film layer, is formed
Expose the via hole 11 of the first pattern 5 such as Fig. 6 (a) or as shown in Fig. 6 (b).
It should be noted that the first, first pattern 5 can for need in array substrate by via hole 11 on insulating layer with
The arbitrary graphic pattern that other structures are in contact.
The second, in step S03, surface of the insulating layer 7 far from 5 side of the first pattern is referred to above insulating layer 7 and should
The top on surface.
In addition, protection pattern 12 is etch-resistant layer, effect, which is such that in etching process, only etches unprotected pattern
The region of 12 covering protections, i.e., the part 73 of via hole 11 to be formed on insulating layer 7.
Third, in step S04, as shown in Fig. 5 (a), when preset thickness=0, the bottom of hole 110 does not have residual film
Layer, i.e. the bottom of hole 110 exposed the first pattern 5, at this point, hole 110 is that have etching gas and absolutely on side wall 110a
Via hole 11 as shown in Fig. 6 (a) for the polymer that the reaction of edge layer 7 generates；It only needs to pass through inert gas in subsequent step S05
Via hole 11 as shown in Fig. 6 (a) can be obtained in polymer on etching removal 110 side wall 110a of hole.
As shown in Fig. 5 (b), when the thickness of 0 < preset thickness < insulating layer, the bottom 110b of hole 110 has default
The residual film layer of thickness, at this point, the side wall 110a and bottom 110b (remaining the surface of film layer) of hole 110 all have etching gas
Body reacts the polymer generated with insulating layer 7；It needs to etch by inert gas in removal hole 110 in subsequent step S05
Polymer and residual film layer.
4th, in step S04, at the part 73 of the via hole to be formed on etching insulating layer 7, if directlyed adopt lazy
Property gas perform etching, due to inert gas carry out etching there is only the bombardments on the direction perpendicular to underlay substrate, do not have
There is the effect of side etch, then will lead to the via hole 11 to be formed with steeper side wall, be unfavorable for subsequent needs and the first pattern
Formation of other pattern layers being in contact in via hole 11.
5th, in step S05, processing is performed etching to hole 110 by inert gas, by foregoing description it is found that by
In the etching carried out by inert gas, there is only the bombardments on the direction perpendicular to underlay substrate, therefore, will not be in via hole
Generate new polymer.
Based on this, the above-mentioned production method provided through the embodiment of the present invention, due to during etching insulating layer 7,
It is performed etching first with etching gas, then in the final stage of etching, i.e., when the residual film layer of the bottom of hole 110 reaches
When preset thickness, it is adjusted to perform etching processing to hole 110 using inert gas, it is anti-to remove etching gas and insulating layer 7
The polymer and residual film layer that should be generated, form via hole 11, subsequent second pattern to be formed passes through via hole 11 and the first pattern 5
It is in contact, the electrical communication of first pattern and the second pattern is influenced so as to avoid the polymer formed in via hole 11.
For example, when the second pattern is pixel electrode, the above method can avoid being formed in via hole 11 when the first pattern is drain electrode
Polymer influence being electrically connected for pixel electrode and drain electrode, improve process rate.
Preferably, in step S05 inert gas bombarding energy be greater than step S04 in etching gas bombarding energy.
The inert gas plasma of high-speed motion is allowed more fully to bombard the polymer in hole 110 in this way
With residual film layer, make the more thorough of its removal that is etched, to expose the upper surface of the first pattern 5 of bottom, forms via hole
11。
Exemplary, the bombarding energy that the bombarding energy of above-mentioned inert gas is greater than etching gas can specifically pass through following sides
Formula is realized:
Increase the automatic bias of etching apparatus when executing step S05 compared to step S04.
Such as when the etching apparatus used is ICP (Inductively Coupled Plasma, inductively coupled plasma
Body) etching apparatus when, when executing step S04, set 15W for automatic bias (lower electrode power)；Executing step S05
When, automatic bias (lower electrode power) is increased into 60W.
When executing step S05, the automatic bias for increasing etching apparatus can make inert gas plasma by bigger
Automatic bias, make its on the direction perpendicular to underlay substrate have higher kinergety, so as to the indifferent gas of high-speed motion
Bulk plasmon can more fully bombard polymer and residual film layer in hole 110, form via hole 11.
Further, when using ICP etching apparatus as etching apparatus, when executing step S05, upper part can also be increased
Electrode power and/or the flow for increasing inert gas.For example, being by upper electrode power setting when executing step S04
800W, and/or 120/20sccm (standard milliliters/per minute) are set by etching gas flow；It, will when executing step S05
Upper electrode power increases to 1000W, and/or inert gas flow is increased to 150sccm.
When executing step S05, increases the upper electrode power of ICP etching apparatus and/or increase the flow of inert gas
More ionized inert gas can be made at inert gas plasma, so that more inert gas plasmas
Body bombards polymer and residual film layer in hole 110, forms via hole 11.
It is exemplary, it since the ionization potential of argon gas (Ar) is lower, is easier to be ionized into plasma, so above-mentioned inert gas
Usually select Ar gas.
Since the effect of insulating layer 7 is the first pattern 5 of protection, for example, avoiding the surface of the first pattern 5 in subsequent technique
In be oxidized, the insulating materials such as inoxidizability stronger nitride, oxide, nitrogen oxides when compact structure, high temperature can be selected.
The material of insulating layer 7 usually selects silica or silica and silicon nitride.
When insulating layer 7 only includes silicon dioxide insulating layer, according to the property of earth silicon material, carbon fluorine gas is usually selected
Body and oxygen etching silicon dioxide insulating layer.For ease of description, carbon fluorine gas and oxygen are referred to as the first etching gas below.
The rate of first etching gas etching silicon dioxide insulating layer is more slow, and the via hole 11 eventually formed can be made to have more
Gentle side wall, in order to which subsequent pattern layer to be formed is formed in via hole 11.
Correspondingly, above-mentioned steps S04 specifically:
By the part 73 corresponding to via hole 11 to be formed on above-mentioned first etching gas etching silicon dioxide insulating layer,
Form the hole 110 as shown in Fig. 5 (a) or Fig. 5 (b)；Wherein, there is preset thickness (to mark in Fig. 5 (b) for the bottom of hole 110
For residual film layer d)；The thickness of 0≤preset thickness < silicon dioxide insulating layer (label is in Fig. 5 (b)).
Above-mentioned first etching gas is reacted with silicon dioxide insulating layer generates fluorocarbon polymer, which is attached to
In hole 110.
That is, fluorocarbon polymer is attached to the side wall 110a and bottom 110b of hole 110 when residual thicknesses of layers is not zero
On (remaining the surface of film layer)；
When preset thickness=0, which is only attached on 110 side wall 110a of hole.
For the ease of more fully understanding the embodiment of the present application, the generating process of fluorocarbon polymer is illustrated below:
Carbon fluorine (CF4, C4F8, CHF3Deng) plasma often be used to etching SiO2, Si and other associated materials.CF4?
The CF of ionic state is resolved under plasmoid2With active F base, reaction equation (1) is seen, wherein CF2It can be with SiO2(or Si) table
Face reaction, forms (CF2)nHigh molecular polymer that is to say fluorocarbon polymer, see reaction equation (2).Reaction equation is as follows:
CF4→2F↑+CF2↑；Reaction equation (1)
nCF2↑→(CF2)n；Reaction equation ((2)
CF4CF, CF in plasma2Collision of the equal groups mainly from electronics to source gas, and in C4F8Middle CF is main
From electronics to CF2Collisional decomposition.
CF4Etch SiO2Process be generally divided into three phases: be fluorocarbon film first in SiO2It is heavy on surface of insulating layer
Product process is then that fluorocarbon film grows repressed process, is then finally SiO2The process that insulating layer is etched, that is to say:
Fluorocarbon polymer deposition is in SiO2Surface.CF from fluorocarbon filmxGroup and SiO2Reaction generates SiFxCO2, then in F original
SiF is resolved under son or ion bombardmentx.So fluorocarbon polymer is to SiO2The influence of etching is very big.
Further, as shown in fig. 7, insulating layer 7 can also include the silicon nitride being arranged on silicon dioxide insulating layer 71
Insulating layer 72.
Since silicon nitride material has better waterproofness and anti-permeability relative to earth silicon material, so that system
The array substrate made has better waterproofness and anti-permeability.
According to the property of silicon nitride material, sulphur fluorine gas (such as SF is usually selected6) and oxygen etch silicon nitride insulating layer
72。
For ease of description, sulphur fluorine gas and oxygen are referred to as the second etching gas below.Second etching gas etches nitrogen
The rate of SiClx insulating layer 72 is more slow, and the via hole 11 eventually formed can be made to have more gentle side wall, in order to
Subsequent pattern layer to be formed is formed in via hole 11.
Correspondingly, with reference to shown in Fig. 7~Fig. 9, the specific steps of above-mentioned steps S04 include:
Step S041, pass through the portion corresponding to via hole 11 to be formed on the second etching gas etch silicon nitride insulating layer 72
Divide 73, forms the second hole 111 of exposing silicon dioxide insulating layer 71 as shown in Figure 8；
Step S042, by corresponding to via hole 11 to be formed on the first etching gas etching silicon dioxide insulating layer 71
Part, as shown in figure 9, forming the first hole 112 (dotted line L on silicon dioxide insulating layer 71 in Fig. 92The position of lower section).
In the process, the first etching gas continues the side wall of laterally etched silicon nitride dielectric layer 72, generates it to four
The retraction in week.First hole 111 (dotted line L in Fig. 91And L2Between position) position correspond to the second hole 112, that is, first
Hole 111 and the second hole 112 collectively form hole 110.
It should be noted that in above-mentioned etching process, due to the speed of the first etching gas etch silicon nitride insulating layer 72
Rate is very fast, if it is steeper to will result in via sidewall by the first etching gas etch silicon nitride insulating layer 72, thus after influencing
Continue the second pattern to be formed and the contact of the first pattern 5, for example, making the pixel electrode being subsequently formed and the overlap joint of drain electrode not
It is good；It is difficult etching silicon dioxide insulating layer 71 because of the second etching gas again, so individual first etching gas of selection or the
Two etching gas perform etching silicon nitride dielectric layer 72 and the effect of silicon dioxide insulating layer 71 is all not fully up to expectations.So first
The second etching gas etch silicon nitride insulating layer 72 is first passed through, the first etching gas etching silicon dioxide insulating layer is then passed through
71, i.e. the insulating layer of different materials performs etching processing using different etching gas
In conjunction with shown in Fig. 6 (a) and Figure 10 (a), after the step of forming via hole 11 for exposing the first pattern 5, the array
The production method of substrate further include:
Step S06, removal protection pattern 12；
Step S07, the second pattern 10 is formed above insulating layer 7；Second pattern 10 passes through via hole 11 and the first pattern 10
It is in contact.
Specifically, the material of protection pattern 12 can be Other substrate materials.The photoresist can be removed using stripping technology
Protect pattern.
Here, above-mentioned second pattern 10 can include but is not limited to the pattern of pixel electrode, the embodiment of the present invention to this not
It limits, can be adjusted flexibly according to the design requirement of array substrate to be formed.
With reference to shown in Fig. 5 (b), Fig. 6 (b) and Figure 10 (b), in step S04, when the thickness of 0 < preset thickness < insulating layer
When spending, i.e., the bottom of hole 110 have preset thickness residual film layer；In step S05, since inert gas plasma hangs down
It is directly etched in underlay substrate surface bombardment, the bottom of the via hole 11 after the completion of etching can generate a height equal to preset thickness
Step 74.The second pattern 10 is at the step 74 of 11 bottom of via hole across disconnected in order to prevent, it is desirable that preset thickness (the i.e. height of step 74
Degree, label is in Fig. 6 (b)) thicknesses of layers (label is in Figure 10 (b)) of≤1/8 second pattern, so as to 10 energy of the second pattern
It is enough sufficiently to cover step, it avoids the second pattern 10 from generating tomography at step, influences the electrical communication with the first pattern 5.
As shown in figure 11, before executing above-mentioned steps S02, the production method of above-mentioned array substrate further include:
Grid 2, the gate insulation layer 3 for covering grid, the oxygen being arranged on gate insulation layer 3 are sequentially formed on underlay substrate 1
Compound active layer 4, the source electrode 6 for being arranged on gate insulation layer 3 and being in contact with oxide active layer 4 and drain electrode 5；First pattern 5
For drain electrode 5；Second pattern 10 is pixel electrode 10；The bottom of via hole is the upper surface of drain electrode 5, and pixel electrode 10 and drain electrode 5 are logical
Via hole is electrically connected.
The pixel electrode can be made of ITO (indium tin oxide aoxidizes cigarette tin) material.
It should be noted that although in embodiments of the present invention, being electrically connected with the drain electrode of thin film transistor (TFT) with pixel electrode
For be illustrated, however it should be apparent to a person skilled in the art that since the source electrode and drain electrode of thin film transistor (TFT) is in structure
With the interchangeability on composition, the source electrode of thin film transistor (TFT) can also be electrically connected with pixel electrode, this belongs to of the invention upper
State the equivalents of embodiment.
It in order to further illustrate the present invention, will be below drain electrode with the first pattern；Second pattern is pixel electrode；Insulating layer
Including silicon dioxide insulating layer and silicon nitride dielectric layer；The material for protecting pattern is photoresist；Etching gas includes sulphur fluorine gas
The production method of array substrate provided by the invention is retouched in detail in conjunction with specific embodiments with oxygen, carbon fluorine gas and oxygen
It states.
It should be understood that following embodiments are to be implemented under the premise of the technical scheme of the present invention, give in detail
Thin embodiment and specific operating process, only to further illustrate the features and advantages of the present invention, rather than to this hair
The limitation of bright claim, protection scope of the present invention are also not necessarily limited to following embodiments.
To simplify description, chooses the region of etching vias is needed individually to be illustrated below.
A) refering to what is shown in Fig. 7, forming drain electrode 5 above underlay substrate 1；Form the silicon dioxide insulating layer of covering drain electrode 5
71, form the silicon nitride dielectric layer 72 of covering silicon dioxide insulating layer 71.
B) it refering to what is shown in Fig. 7, on silicon nitride dielectric layer 72, is produced by modes such as gluing, exposure, developments to be formed
The photoresist mask layer pattern 12 of via hole exposes the part of via hole to be formed on insulating layer 7 so that photoresist exposure mask layer pattern 12
73。
C) refering to what is shown in Fig. 8, using ICP etching machine as etching apparatus, using sulphur fluorine gas and oxygen as etching gas, nitrogen is etched
The part 73 corresponding to via hole 11 to be formed on SiClx insulating layer 72 forms the second hole for exposing silicon dioxide insulating layer 72
111；
In the process, the upper electrode power setting of ICP etching apparatus is 800W, and lower electrode power (automatic bias) is set
It is set to 15W, sulphur fluorine gas and oxygen flow are set as 100/20sccm.
D) refering to what is shown in Fig. 9, after the completion of step c, continue using ICP etching apparatus as etching apparatus, with carbon fluorine gas and oxygen
Gas is etching gas, the part corresponding to via hole 11 to be formed on etching silicon dioxide insulating layer 71, until etching into dioxy
When the remaining thicknesses of layers of SiClx insulating layer 71 is d, the first hole 112 is formed；
In the process, the power setting of ICP etching apparatus upper electrode is 800W, lower electrode power (automatic bias) setting
For 30W, carbon fluorine gas and oxygen flow are set as 120/20sccm.
It should be noted that in the process, carbon fluorine gas and oxygen also continue to laterally etched silicon nitride dielectric layer
The side wall of the second hole 111 on 72 makes the side wall of the second hole 111 continue to be retracted around.
By foregoing description it is found that by step d etching, the side wall of the first hole 112 and the upper table of remaining film layer
Face can generate the more difficult fluorocarbon polymer being removed.
E) as shown in figure 12, after the completion of step d, continue using ICP etching apparatus as etching apparatus, using Ar gas as work gas
Body performs etching processing to hole 110, to remove fluorocarbon polymer and remaining film layer, until exposing the upper of the drain electrode 5 of bottom
Surface forms via hole 11；
In the process, the power setting of ICP upper electrode is 1000W, and lower electrode power (automatic bias) is set as 60W,
Ar flow set is 150sccm.
F) as shown in figure 13, after the completion of step e, photoresist mask layer pattern 12 is removed.
G) as shown in figure 14, after the completion of step f, the deposition of ITO films on insulating layer 7 carries out corresponding structure to ito film layer
Figure process forms pixel electrode 10；Wherein, pixel electrode 10 is electrically connected by via hole 11 and drain electrode 5.On above-mentioned basis
On, the embodiment of the invention also provides a kind of array substrates obtained using above-mentioned production method.
Based on this, the array substrate obtained by above-mentioned production method works as hole due to the final stage in etching
When the residual film layer of 110 bottom reaches preset thickness, it is adjusted to perform etching processing to hole 110 using inert gas, goes
In addition to etching gas reacts the polymer generated and residual film layer with insulating layer 7, via hole 11, subsequent second figure to be formed are formed
Case is in contact by via hole 11 with the first pattern 5, is influenced so as to avoid the polymer formed in etching process in via hole 11
The electrical communication of first pattern 5 and the second pattern 10.
For example, when the second pattern 10 is pixel electrode, being obtained by above-mentioned production method when the first pattern 5 is drain electrode
Array substrate, due to eliminating the polymer generated in etching process in via hole 11, it is possible to the polymer be avoided to influence
Pixel electrode is electrically connected with drain electrode, improves process rate.
Specifically, may also include the other structures such as public electrode in above-mentioned array substrate, the relevant technologies can be specifically continued to use, this
Inventive embodiments are not construed as limiting this.
Further, the embodiment of the invention also provides a kind of display devices, including above-mentioned array substrate.
The display device can be liquid crystal display panel, liquid crystal display, LCD TV, OLED (OrganicLight-
Emitting Display, ORGANIC ELECTROLUMINESCENCE DISPLAYS) display, OLED TV or Electronic Paper, Digital Frame, mobile phone, plate
Computer etc. has the product or component of any display function.
In the description of above embodiment, particular features, structures, materials, or characteristics can be at any one or more
It can be combined in any suitable manner in a embodiment or example.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (12)
1. a kind of production method of array substrate, which is characterized in that the production method of the array substrate includes:
The first pattern is formed above underlay substrate；
Form the insulating layer for covering first pattern；
Protection pattern is formed above the insulating layer, the protection pattern exposes the portion of via hole to be formed on the insulating layer
Point；
The part of the via hole to be formed on the insulating layer is etched by etching gas, forms hole, the bottom of described hole
Portion has the residual film layer of preset thickness；Wherein, 0 the thickness of insulating layer described in the≤preset thickness <；Shape in described hole
At there is the etching gas to react with the insulating layer polymer generated；
Processing is performed etching to described hole by inert gas, to remove the polymer and the residual film layer, forms dew
The via hole of first pattern out.
2. the production method of array substrate according to claim 1, which is characterized in that it is described by inert gas to described
When hole performs etching processing, the bombarding energy of the inert gas is greater than the bombarding energy of the etching gas.
3. the production method of array substrate according to claim 2, which is characterized in that it is described by inert gas to described
When hole performs etching processing, the bombarding energy of the inert gas is greater than the bombarding energy of the etching gas, comprising:
Compared to the via hole to be formed etched by etching gas on the insulating layer part when, increase etching apparatus
Automatic bias.
4. the production method of array substrate according to claim 1, which is characterized in that the inert gas includes Ar gas.
5. the production method of array substrate according to claim 1, which is characterized in that the insulating layer includes silica
Insulating layer；The etching gas includes: the first etching gas, and first etching gas is made of carbon fluorine gas and oxygen；
The part that the via hole to be formed on the insulating layer is etched by etching gas includes:
The part corresponding to the via hole to be formed on the silicon dioxide insulating layer is etched by first etching gas,
Form the first hole；Wherein, the bottom of first hole has the residual film layer of preset thickness；0≤preset thickness the <
The thickness of the silicon dioxide insulating layer；It is formed with first etching gas in first hole and the silica is exhausted
The fluorocarbon polymer that edge layer reaction generates.
6. according to right want 5 described in array substrate production method, which is characterized in that the insulating layer further include: be covered on
Silicon nitride dielectric layer above the silicon dioxide insulating layer；The etching gas further include: the second etching gas, described second
Etching gas is made of sulphur fluorine gas and oxygen；
Correspond to the via hole to be formed on the silicon dioxide insulating layer in described etch by first etching gas
Part before, the part that the via hole to be formed on the insulating layer is etched by etching gas further include:
The part corresponding to the via hole to be formed on the silicon nitride dielectric layer, shape are etched by second etching gas
At the second hole for exposing the silicon dioxide insulating layer；
The position of first hole to be formed corresponds to second hole；Described hole is by first hole and to shape
At second hole constitute.
7. the production method of array substrate according to claim 1, which is characterized in that expose described first in the formation
After the step of via hole of pattern, the production method of the array substrate further include:
Remove the protective layer；
The second pattern is formed above the insulating layer；
Second pattern is in contact by the via hole with first pattern.
8. the production method of array substrate according to claim 7, which is characterized in that described in preset thickness < described in 0 <
The thickness of insulating layer；
The step that there is height to be equal to the preset thickness for the bottom of the via hole；Height≤1/8 of the step described second
The thicknesses of layers of pattern.
9. the production method of array substrate according to claim 8, which is characterized in that the formation covers first figure
Before the step of insulating layer of case, the production method of the array substrate further include:
Grid, the gate insulation layer of the covering grid, setting are sequentially formed on the underlay substrate on the gate insulation layer
Oxide active layer, the source electrode and drain electrode that is arranged on the gate insulation layer and is in contact with the oxide active layer；Institute
Stating the first pattern is the drain electrode；Second pattern is pixel electrode.
10. the production method of described in any item array substrates according to claim 1~9, which is characterized in that the protection pattern
Material be Other substrate materials.
11. a kind of array substrate, which is characterized in that the array substrate passes through the described in any item arrays of claim 1~10
The production method of substrate is made.
12. a kind of display device, which is characterized in that the display device includes array substrate described in claim 11.
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| CN109671610A (en) * | 2018-12-20 | 2019-04-23 | 深圳市华星光电半导体显示技术有限公司 | A kind of surface treatment method for aligned polymer film |
| CN110379819A (en) * | 2019-06-11 | 2019-10-25 | 滁州惠科光电科技有限公司 | Array substrate, manufacturing method thereof and display panel |
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| CN110379819B (en) * | 2019-06-11 | 2022-02-18 | 滁州惠科光电科技有限公司 | Array substrate, manufacturing method thereof and display panel |
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