CN108984805B - Optimization method and system for improving CMP defects - Google Patents
Optimization method and system for improving CMP defects Download PDFInfo
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- CN108984805B CN108984805B CN201710398820.4A CN201710398820A CN108984805B CN 108984805 B CN108984805 B CN 108984805B CN 201710398820 A CN201710398820 A CN 201710398820A CN 108984805 B CN108984805 B CN 108984805B
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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Abstract
The embodiment of the invention discloses an optimization method and system for improving CMP defects, wherein after the initial surface morphology of a chip after metal filling is determined, CMP simulation of the chip is carried out to obtain a simulated defect grid area, then, filling depth adjustment and CMP simulation are carried out on the defect grid area, so that the groove depth of the defect grid area when the defects are improved is determined, and the groove depth is used as the final groove depth of the defect grid area. Because the groove depth is determined again in the area which is easy to have defects in the chip, the defects of the defective grid area are improved under the groove depth, so that the defects in the CMP process can be reduced, meanwhile, the area which needs to be filled with redundant metal under the same process condition is greatly reduced, the quantity of the redundant metal is reduced, and the problem of parasitic parameters caused by the filling of the redundant metal is greatly reduced.
Description
Technical Field
The invention relates to the field of manufacturability design of integrated circuits, in particular to an optimization method and system for improving CMP defects.
Background
In a large scale integrated circuit manufacturing process, CMP (chemical mechanical planarization) is a planarization process combining chemical and mechanical actions, and is a main means for global planarization of a chip surface.
In the CMP process, there are two main drawbacks: metal dishing and oxide erosion (oxidation), the defects of which are especially prominent in the node process below 45nm, directly affect the performance of the device and the yield of the chip. At present, the defect of the metal butterfly is mainly solved by a redundant metal filling technology (dummy fill), and the technology is to fill redundant metal in a place where the defect is likely to occur, so that the layout density is homogenized, and the generation of the defect is reduced.
At present, the integrated circuit technology is developing towards high speed, high density and low power consumption, however, the filling of the redundant metal can bring the parasitic effect of the interconnection line to cause time delay, which becomes one of the key factors restricting the development of large-scale integrated circuits after the manufacturing process enters the nanometer era.
Disclosure of Invention
The invention provides an optimization method and an optimization system for improving CMP defects, and CMP defects and parasitic effects are reduced.
An optimized method for improving CMP defects, comprising:
carrying out grid division on the layout, and extracting equivalent parameters of grids;
obtaining the initial surface morphology of the chip after metal filling according to the equivalent parameters and the initial groove depth;
performing CMP simulation on the chip under the initial surface morphology of the chip to obtain a defect grid area, wherein the defect grid area is a grid area where the defects of the CMP simulation are located;
optimizing the defective grid region, specifically including: adjusting the depth of the groove of the defective grid area, determining the initial surface appearance of the defective grid area according to the equivalent parameters and the adjusted depth of the groove, and performing CMP simulation on the defective grid area so as to improve the defect of the defective grid area;
and taking the depth of the groove when the defect is improved as the depth of the groove after the defect grid area is optimized in the etching process.
Preferably, the optimizing the defective mesh region includes:
setting a depth range and a step length of the groove;
and within the range of the depth of the groove, increasing the depth of the groove by taking the minimum depth of the groove as an initial value and the step length, respectively obtaining the initial appearance of the defective grid area under different depths of the groove according to the equivalent parameters and different depths of the groove, respectively carrying out CMP simulation on the defective grid area, and determining the defect improved result from different CMP simulation results.
Preferably, the determination of the improved defect results from the different CMP simulation results comprises:
and selecting the final shape fluctuation with the minimum value from different CMP simulation results as a result of improving the defects.
Preferably, the metal filling process is an ECP copper electroplating process.
Preferably, the method further comprises the following process steps:
etching the groove, wherein the optimized groove depth is adopted in the defect area, and the initial groove depth is adopted in the area outside the defect area;
metal filling and CMP are performed.
An optimization system for improving CMP defects, comprising:
the equivalent parameter acquisition unit is used for carrying out grid division on the layout and extracting equivalent parameters of the grids;
the chip initial surface morphology determining unit is used for determining the initial surface morphology of the chip after metal filling according to the equivalent parameters and the initial groove depth;
the defect grid area acquisition unit is used for performing CMP simulation on the chip under the initial surface morphology of the chip to obtain a defect grid area, wherein the defect grid area is a grid area where the defects of the CMP simulation are located;
the defective mesh area optimizing unit is configured to optimize the defective mesh area, and specifically includes: adjusting the depth of the groove of the defective grid area, determining the initial surface appearance of the defective grid area according to the equivalent parameters and the adjusted depth of the groove, and performing CMP simulation on the defective grid area so as to improve the defect of the defective grid area;
and the defect area groove depth determining unit is used for taking the groove depth when the defect is improved as the groove depth after the defect grid area is optimized in the etching process.
Preferably, the defect mesh region optimizing unit includes:
the parameter setting unit is used for setting the depth range and the step length of the groove;
and the simulation unit is used for increasing the depth of the groove by taking the minimum depth of the groove as an initial value and the step length within the depth range of the groove, respectively obtaining the initial morphology of the defective grid area under different depths of the groove according to the equivalent parameters and different depths of the groove, respectively carrying out CMP simulation on the defective grid area, and determining the defect improved result from different CMP simulation results.
Preferably, in the simulation unit, determining a result of improving the defect from different CMP simulation results includes:
and selecting the final shape fluctuation with the minimum value from different CMP simulation results as a result of improving the defects.
Preferably, the metal filling process is an ECP copper electroplating process.
According to the optimization method and system for improving the CMP defects, provided by the embodiment of the invention, after the initial surface morphology of the chip after metal filling is determined, CMP simulation of the chip is carried out to obtain a simulated defect grid area, then, the filling depth is adjusted and the CMP simulation is carried out on the defect grid area, so that the groove depth of the defect grid area when the defects are improved is determined, and the groove depth is used as the groove depth of the defect grid area in the actual etching process. Because the depth of the groove is determined again in the area which is easy to have defects in the chip, the defects of the grid area with the defects are improved under the depth of the groove, so the defects in the CMP process after subsequent filling can be reduced, meanwhile, the area which needs to be filled with redundant metal under the same process condition is greatly reduced, the quantity of the redundant metal is reduced, and the problem of parasitic parameters caused by the filling of the redundant metal is greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic flow chart illustrating an optimization method for improving CMP defects according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an optimization system for improving CMP defects according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, the reduction of CMP defects by the filling of the redundant metal can cause parasitic effect of the interconnect, and the time delay caused by the parasitic effect restricts the development of the lsi towards high speed, high density and low power consumption after the manufacturing process enters the nano era.
The optimization method for improving the CMP defects comprises the steps of carrying out CMP simulation on a chip after determining the initial surface morphology of the chip after metal filling to obtain a simulated defect grid area, and then carrying out filling depth adjustment and CMP simulation on the defect grid area to determine the groove depth of the defect grid area when the defects are improved, wherein the groove depth is used as the groove depth of the defect grid area. Because the groove depth is determined again in the area which is easy to have defects in the chip, the defects of the defective grid area are improved under the groove depth, so that the defects in the CMP process can be reduced, meanwhile, the area which needs to be filled with redundant metal under the same process condition is greatly reduced, the quantity of the redundant metal is reduced, and the problem of parasitic parameters caused by the filling of the redundant metal is greatly reduced.
In order to better understand the technical solutions and effects of the present invention, the following description will be given with reference to specific examples.
Referring to fig. 1, in step S01, a mesh division of the layout is performed, and equivalent parameters of the mesh are extracted.
The CMP optimization design method of the embodiment of the invention is an optimization simulation method aiming at a chip layout, and in the step, the chip layout is subjected to grid division, namely, the whole chip layout is divided into a plurality of grid windows through a grid with a fixed size, the size of the grid can be determined according to specific requirements, and usually, a square with the width of D is set for carrying out layout division.
After dividing the grid, extracting equivalent parameters of the grid, wherein a plurality of graphs are arranged in the grid, and layout characteristic parameters in the grid can be obtained by traversing the circumferences, the areas and the graph intervals of all the graphs and then establishing and solving a one-dimensional quadratic equation.
In step S02, according to the equivalent parameters and the initial trench depth, the initial surface topography of the chip after metal filling is obtained.
In this step, the initial surface topography of the chip after metal filling before CMP, i.e., the surface of the chip before CMP, is simulated, and the initial surface topography of the entire chip is obtained in this step, which refers to the surface height distribution of the entire chip.
For different filling processes, the initial surface topography of the filled chip can be established through a proper model, and for metal filling, the equivalent parameters and the initial groove depth can be determined. The initial trench depth refers to the depth of a trench determined in a manufacturing process, and at this time, a trench with a certain depth is formed in a certain process step of the whole chip, the trench is used for filling metal, and a metal layer with a certain thickness is formed, and the metal layer is usually a through hole or a metal interconnection layer. The method for determining the initial surface morphology of the chip after metal filling is different according to different metal filling and filling modes and according to equivalent parameters and initial groove depth, and most of rear-section metal layers are copper processes in the current manufacturing process. The filling mode mainly comprises conformal filling, super filling and over filling, wherein the conformal filling is suitable for areas with relatively large line width, the super filling is suitable for areas with small line width and relatively large space, and the over filling is suitable for areas with small line width and space.
Taking an ECP (electrolytic copper plating) copper electroplating process and overfilling as an example, the initial surface morphology of the chip after metal filling can be obtained by the following formula (1):
H＝H0+H0(TeL/D2) -Tp formula (1)
Wherein H0For the growth height of the empty region, TeThe lateral growth factor, the grid width D, the total circumference of the wires in the grid L, rho is the surface density of the wires in the grid, and T is the depth of the groove to be filled.
In this step, T takes the value of the initial trench depth T0。
In step S03, CMP simulation of the chip is performed under the initial surface topography of the chip to obtain a defect grid area, where the defect grid area is a grid area where a defect of the CMP simulation is located.
In the step, CMP simulation is performed under the determined initial surface topography of the chip, and related process parameters of CMP, such as a down pressure P, a rotational speed Vp of a polishing pad, a rotational speed Vw of a wafer, and the like, may be set according to a specific process during the simulation. Meanwhile, parameters corresponding to the generation of defects, such as the lower limit of the height value after CMP, may be set, and defects are considered to exist below the lower limit.
After the CMP simulation, all defects can be obtained, which may be butterfly defects or other CMP defects, and the grid regions where the defects are located are extracted as the defect grid regions and used as the objects of the subsequent simulation optimization.
In step S04, the optimizing the defective mesh region specifically includes: and adjusting the depth of the groove of the defective grid area, determining the initial surface morphology of the defective grid area according to the equivalent parameters and the adjusted depth of the groove, and performing CMP simulation on the defective grid area so as to improve the defect of the defective grid area.
In the step, a defective grid area is used as an object of simulation optimization, the initial surface morphology of the defective grid area is re-determined by changing the depth of the grooves in the defective grid area, and CMP simulation of the defective grid area is performed under the initial surface morphology to obtain a simulation result. The improvement of the defects in the grid region means that the defects are reduced, that is, the number of defects is reduced, or the degree of defects is reduced, that is, fluctuation of the surface topography is reduced, compared with the CMP simulation of the chip in step S03.
In a specific implementation, the optimization can be performed according to the following steps:
firstly, setting a depth range and a step length of a groove;
setting the step length delta T, T being T0+ Δ T is the trench depth, T satisfies the condition, Tmin and Tmax are the process-defined minimum and maximum depth values of the trench, respectively.
And then, within the depth range of the groove, increasing the depth of the groove by taking the minimum depth of the groove as an initial value and the step length, respectively obtaining the initial appearance of the defective grid area under different depths of the groove according to the equivalent parameters and different depths of the groove, respectively carrying out CMP simulation on the defective grid area, and determining the defect to obtain an improved result from different CMP simulation results.
In the ECP copper embodiment, the initial profile of each trench with a different depth T is determined by using the formula (1) in step S02, CMP simulation is performed on the initial profile to obtain a CMP simulation result, the step is repeated to obtain the initial profiles of all the trench depths T and the simulation result after the CMP simulation, the simulation result is analyzed, and the final profile with the minimum fluctuation is selected as the result of improving the defect.
In step S05, the trench depth at the time of defect improvement is used as the optimized trench depth of the defect grid region in the etching process.
After the optimization of the defective grid area, the groove depth parameter of the defective grid area is re-determined according to the finally determined groove depth of the defective grid area, and when the post-process flow is improved, the groove etching depth of the whole layout is changed from single T0Adjusted to two different groove depths T0And T1Respectively corresponding to the non-defective area in the original process and the defective area in the original process.
That is, the optimized parameters may then be applied to the fabrication of integrated circuits, which may serve to reduce CMP defects and parasitics in the actual fabrication process.
In a specific manufacturing process, first, etching of the trench is performed, and the optimized trench depth is adopted in the defect region, and the initial trench depth is adopted in the region outside the defect region. It will be appreciated that the trench is the trench to be filled in the above described optimized method. Then, metal filling and CMP are performed. Since the trench etch depth is from a single T0Adjusted to two different groove depths T0And T1After filling, the defect of the defect grid area is improved when the CMP process is carried out, corresponding to the defect-free area in the original process and the defect area in the original process respectively.
To better understand the CMP process, a copper interconnect process is illustrated as an example. In the copper interconnection process, firstly, etching a groove is carried out, and the depth of the groove, namely the filled groove, is determined at the moment; then, filling copper, wherein a diffusion barrier layer and a copper seed layer are usually formed first during filling, and then copper is electroplated; thereafter, a CMP process is performed. After CMP, the desired copper interconnect layer is formed in the trench.
In the embodiment of the invention, the depth of the groove of the chip during CMP is adjusted to two different depths, and the depth of the groove is determined again in the area which is easy to have defects in the chip, and the defects of the defect grid area are improved under the depth of the groove, so the defects in the CMP process can be reduced, meanwhile, the area which needs to be filled with redundant metal under the same process condition is greatly reduced, the quantity of the redundant metal is reduced, and the problem of parasitic parameters caused by the filling of the redundant metal is greatly reduced.
The CMP optimization design method according to the embodiment of the present invention is described in detail above, and in addition, the present invention further provides an optimization system for improving CMP defects corresponding to the method, which is shown in fig. 2 and includes:
an equivalent parameter obtaining unit 110, configured to perform grid division on the layout and extract equivalent parameters of the grid;
a chip initial surface topography determining unit 120, configured to determine a chip initial surface topography after metal filling according to the equivalent parameters and the initial trench depth;
a defect grid area obtaining unit 130, configured to perform CMP simulation on the chip under the initial surface topography of the chip to obtain a defect grid area, where the defect grid area is a grid area where a defect of the CMP simulation is located;
the defect mesh area optimizing unit 140 is configured to optimize the defect mesh area, and specifically includes: adjusting the depth of the groove of the defective grid area, determining the initial surface appearance of the defective grid area according to the equivalent parameters and the adjusted depth of the groove, and performing CMP simulation on the defective grid area so as to improve the defect of the defective grid area;
and a defect area groove depth determining unit 150, configured to use the groove depth when the defect is improved as the groove depth after the defect grid area is optimized in the etching process.
Further, the defect mesh region optimizing unit 140 includes:
the parameter setting unit is used for setting the depth range and the step length of the groove;
and the simulation unit is used for increasing the depth of the groove by taking the minimum depth of the groove as an initial value and the step length within the depth range of the groove, respectively obtaining the initial morphology of the defective grid area under different depths of the groove according to the equivalent parameters and different depths of the groove, respectively carrying out CMP simulation on the defective grid area, and determining the defect improved result from different CMP simulation results.
Further, in the simulation unit, determining a result of improving the defect from different CMP simulation results includes:
and selecting the final shape fluctuation with the minimum value from different CMP simulation results as a result of improving the defects.
Further, the metal filling process is an ECP copper electroplating process.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (7)
1. An optimized method for improving CMP defects, comprising:
carrying out grid division on the layout, and extracting equivalent parameters of grids;
obtaining the initial surface morphology of the chip after metal filling according to the equivalent parameters and the initial groove depth;
performing CMP simulation on the chip under the initial surface morphology of the chip to obtain a defect grid area, wherein the defect grid area is a grid area where the defects of the CMP simulation are located;
setting a depth range and a step length of the groove;
within the range of the depth of the groove, the depth of the groove is increased by taking the minimum depth of the groove as an initial value and the step length, the initial appearances of the defective grid areas under different depths of the groove are respectively obtained according to the equivalent parameters and different depths of the groove, the CMP simulation of the defective grid areas is respectively carried out, and the improved result of the defect is determined from different CMP simulation results;
and taking the depth of the groove when the defect is improved as the depth of the groove after the defect grid area is optimized in the etching process.
2. The method of claim 1, wherein determining the improved defect results from different CMP simulation results comprises:
and selecting the final shape fluctuation with the minimum value from different CMP simulation results as a result of improving the defects.
3. The method of claim 1, wherein the metal filling process is an ECP copper plating process.
4. A method according to any one of claims 1-3, characterized by the further process steps of:
etching the groove, wherein the optimized groove depth is adopted in the defect area, and the initial groove depth is adopted in the area outside the defect grid area;
metal filling and CMP are performed.
5. An optimization system for improving CMP defects, comprising:
the equivalent parameter acquisition unit is used for carrying out grid division on the layout and extracting equivalent parameters of the grids;
the chip initial surface morphology determining unit is used for determining the initial surface morphology of the chip after metal filling according to the equivalent parameters and the initial groove depth;
the defect grid area acquisition unit is used for performing CMP simulation on the chip under the initial surface morphology of the chip to obtain a defect grid area, wherein the defect grid area is a grid area where the defects of the CMP simulation are located;
the parameter setting unit is used for setting the depth range and the step length of the groove;
the simulation unit is used for increasing the depth of the groove by taking the minimum depth of the groove as an initial value and the step length within the depth range of the groove, respectively obtaining the initial appearance of the defective grid area under different depths of the groove according to the equivalent parameters and different depths of the groove, respectively carrying out CMP simulation on the defective grid area, and determining the defect improved result from different CMP simulation results; and the defect grid area groove depth determining unit is used for taking the groove depth when the defect is improved as the groove depth after the defect grid area is optimized in the etching process.
6. The system of claim 5, wherein the determining, in the simulation unit, the result of the improvement in the defect from the different CMP simulation results comprises:
and selecting the final shape fluctuation with the minimum value from different CMP simulation results as a result of improving the defects.
7. The system of claim 6, wherein the metal filling process is an ECP copper plating process.
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| CN102222643A (en) * | 2011-06-24 | 2011-10-19 | 中国科学院微电子研究所 | Method for filling redundant metal in manufacturing process of integrated circuit and semiconductor device |
| CN102427046A (en) * | 2011-11-30 | 2012-04-25 | 中国科学院微电子研究所 | Electro-chemical deposition result determination method |
| CN103544331A (en) * | 2012-07-16 | 2014-01-29 | 复旦大学 | Dummy comprehensive optimization method based on CMP simulation model |
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| CN102222643A (en) * | 2011-06-24 | 2011-10-19 | 中国科学院微电子研究所 | Method for filling redundant metal in manufacturing process of integrated circuit and semiconductor device |
| CN102427046A (en) * | 2011-11-30 | 2012-04-25 | 中国科学院微电子研究所 | Electro-chemical deposition result determination method |
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