CN108875107B - Planarization simulation method and system for shallow channel isolation of FinFET device - Google Patents
Planarization simulation method and system for shallow channel isolation of FinFET device Download PDFInfo
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Abstract
The invention discloses a planarization simulation method for shallow channel isolation of a FinFET device, which comprises the following steps: carrying out grid division on a chip layout, and respectively extracting layout characteristic parameters in a grid; obtaining a chip deposition surface height model after oxide deposition to provide an initial surface morphology height of a chip, wherein the chip deposition surface height model is related to a layout characteristic parameter; obtaining the pattern density in the grid after the oxide deposition; obtaining the effective density of the pattern in the grid according to the pattern density and the characteristic correlation length in the deposited grid; obtaining contact pressure distribution in the grid on the surface of the chip; establishing a grinding removal rate model of the chip according to the effective density of the graph in the grid and the contact pressure distribution; and taking the initial surface morphology height of the chip as an initial value, and carrying out the surface morphology simulation of the chip according to the relationship between the morphology height of the chip and the grinding removal rate equation. The method can meet the requirements of shallow trench isolation planarization simulation of the FinFET device.
Description
Technical Field
The invention relates to the field of integrated circuit design and manufacture, in particular to a planarization simulation method and system for shallow channel isolation of a FinFET device.
Background
With the continuous development of integrated circuit technology, the requirement for integration level is higher and higher, and after a 16-nanometer process node is entered, a non-planar Fin Field Effect Transistor (FinFET) structure is generally adopted in the industry.
In the FinFET manufacturing process, shallow trench isolation is formed between fins (Fin), in the shallow trench isolation forming step, CMP (chemical mechanical planarization) needs to be performed after silicon nitride (SiN) and Oxide (Oxide) are deposited, and in the planarization process, SiN dishing is a common problem, which affects the height and the shape of the fins, and directly affects the device performance and the chip yield.
The CMP simulation can assist in improving the control precision of the CMP process and improving the yield, at present, the FinFET device CMP simulation is mainly aimed at the subsequent processes such as a copper process, and the simulation cannot be directly expanded to the planarization simulation of shallow channel isolation of the FinFET device.
Disclosure of Invention
The invention provides a method and a system for simulating shallow trench isolation planarization of a FinFET device, aiming at solving the defects in the traditional FinFET CMP simulation.
The invention provides a planarization simulation method for shallow channel isolation of a FinFET device, which comprises the following steps:
carrying out grid division on a chip layout, and respectively extracting layout characteristic parameters in a grid, wherein the layout characteristic parameters comprise equivalent line width, equivalent spacing and equivalent graph density;
obtaining a chip deposition surface height model after oxide deposition to provide an initial surface morphology height of a chip, wherein the chip deposition surface height model is related to a layout characteristic parameter;
obtaining the pattern density in the grid after the oxide deposition;
obtaining the effective density of the pattern in the grid according to the pattern density and the characteristic correlation length in the deposited grid;
obtaining contact pressure distribution in the grid on the surface of the chip;
establishing a grinding removal rate model of the chip according to the effective density of the graph in the grid and the contact pressure distribution;
and taking the initial surface morphology height of the chip as an initial value, and carrying out the surface morphology simulation of the chip according to the relationship between the morphology height of the chip and the grinding removal rate equation.
Optionally, the obtaining the effective density of the pattern in the grid according to the pattern density and the feature correlation length in the grid after deposition includes:
and sequentially carrying out smooth filtering processing and convolution operation on the graph density in the deposited grid to obtain the graph effective density in the grid under the influence of the characteristic correlation length.
Optionally, the obtaining the contact pressure distribution in the grid on the surface of the chip includes:
establishing a whole contact pressure equation set on the surface of the chip by utilizing a contact mechanics principle;
and obtaining the contact pressure distribution in the grid of the chip surface from the whole contact pressure equation set of the chip surface by using a fast Fourier transform and a conjugate gradient method.
Optionally, the establishing a grinding removal rate model of the chip according to the effective density of the pattern in the grid and the contact pressure distribution includes:
and respectively establishing grinding removal rate models inside and outside the grooves in the grids according to a Preston formula, the contact pressure and the grinding removal rate.
The invention also provides a planarization simulation system for the shallow trench isolation of the FinFET device, which comprises the following steps:
the layout dividing and parameter acquiring unit is used for carrying out grid division on the chip layout and respectively extracting layout characteristic parameters in grids, wherein the layout characteristic parameters comprise equivalent line width, equivalent spacing and equivalent graph density;
the chip deposition surface height acquisition unit is used for acquiring a chip deposition surface height model after oxide deposition so as to provide the initial surface morphology height of the chip, and the chip deposition surface height model is related to the layout characteristic parameters;
a pattern density obtaining unit after deposition, which is used for obtaining the pattern density in the grid after the oxide deposition;
the effective density obtaining unit is used for obtaining the effective density of the graph in the grid according to the graph density and the characteristic correlation length in the grid after deposition;
a contact pressure acquisition unit for acquiring a contact pressure distribution in the grid on the surface of the chip;
the grinding removal rate obtaining unit is used for establishing a grinding removal rate model of the chip according to the graph effective density and the contact pressure distribution in the grid;
and the appearance simulation unit is used for carrying out the surface appearance simulation of the chip according to the relation between the appearance height of the chip and the grinding removal rate equation by taking the initial surface appearance height of the chip as an initial value.
Optionally, in the effective density obtaining unit, the graph density in the deposited grid is sequentially subjected to smoothing filtering processing and convolution operation, so as to obtain the graph effective density in the grid under the influence of the characteristic correlation length.
Optionally, in the contact pressure obtaining unit, a system of integral contact pressure equations of the chip surface is established by using a contact mechanics principle; and obtaining the contact pressure distribution in the grid of the chip surface from the whole contact pressure equation set of the chip surface by using a fast Fourier transform and a conjugate gradient method.
Optionally, in the grinding removal rate obtaining unit, grinding removal rate models inside and outside the groove in the grid are respectively established according to the Preston formula, the contact pressure and the grinding removal rate.
In the planarization simulation method and system for shallow trench isolation of the FinFET device, provided by the embodiment of the invention, in the process of establishing a grinding removal rate equation, the graph effective density and the contact pressure distribution of a grid are used as variables, the effective density is the simulation density taking deposition characteristics and relevant length into consideration after filling, the influence of grinding pad deformation and peripheral graphs on the grid graph can be reflected better, and the contact pressure distribution is the pressure distribution of the grid, so that a grid-based shallow trench isolation CMP simulation model can be established through the pressure distribution, the effective density and the grinding removal rate equation in the grid, and the requirement of high-precision planarization simulation of shallow trench isolation of the FinFET device is met.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flow chart of a method for simulating planarization of shallow trench isolation of a FinFET device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a planarization simulation system for shallow trench isolation of a FinFET device according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, CMP simulation can assist in improving the control accuracy of the CMP process and improving the yield, and at present, CMP simulation of a FinFET device is mainly directed to a subsequent process such as a copper process, and such a simulation method cannot be directly extended to be applied to planarization simulation of shallow trench isolation of the FinFET device.
In order to better understand the technical solutions and effects of the present invention, the following detailed descriptions will be given with reference to specific examples.
Referring to fig. 1, in step S01, the chip layout is subjected to grid division, and layout characteristic parameters in the grid are respectively extracted, where the layout characteristic parameters include equivalent line width, equivalent pitch, and equivalent pattern density.
The chip layout grid division means that the whole chip layout is divided into a plurality of grid windows through grids with fixed sizes, so that the analysis of the whole chip is converted into the analysis of each grid, and a more precise model is favorably established.
The reasonable selection of the size of the grid is beneficial to the accurate extraction of the layout characteristic parameters, and can also influence the subsequent deposition and planarization simulation precision, in a specific embodiment, the grid with the proper size is selected to divide a chip layout according to a specific layout and process nodes, a D-by-D grid is provided as shown in a reference figure 2, a plurality of graphs are arranged in the grid, the layout characteristic parameters in the grid can be obtained by traversing the circumferences, areas and graph intervals of all the graphs and then establishing and solving a unitary quadratic equation, the layout characteristic parameters in the embodiment of the invention are geometric graph characteristic parameters which mainly comprise the equivalent line width, the equivalent interval and the equivalent graph density of the graphs, and the equivalent graph density is obtained by the ratio of the equivalent line width to the sum of the equivalent interval and the equivalent line width.
In step S02, a chip deposition surface height model after oxide deposition is obtained to provide an initial surface topography height of the chip, the chip deposition surface height model being related to the layout characteristic parameters.
In a specific embodiment, a proper chip deposition surface height model can be established according to different deposition modes and design requirements, and the surface topography height of the deposited chip is simulated. In some embodiments, firstly, according to the layout characteristic parameters, selecting a proper filling mode, wherein the filling mode comprises conformal filling, super filling and over filling, the conformal filling is suitable for areas with relatively large line width, the super filling is suitable for areas with small line width and relatively large space, the over filling is suitable for areas with small line width and relatively small space, and the deposition process can adopt a chemical vapor deposition method of oxide; then, a chip deposition surface height model in the filling mode is established, in this embodiment, the model may be established by layout characteristic parameters, and the initial surface topography height of the chip is provided by the model. In one particular embodiment, the die deposition surface height model is established by the following equation (1):
H＝aw+bs+cd1+p(1)
wherein H is the deposition surface height, w is the equivalent line width, s is the equivalent spacing, d1For equivalent pattern density, a, b, c, and p are coefficients that can be obtained by fitting experimental data.
Of course, the process parameters and design parameters, such as shallow trench depth between fins and non-uniformity of trench surface deposition, may be further taken into consideration to create a finer model of the height of the chip deposition surface.
In step S03, the pattern density in the grid after the oxide deposition is obtained.
In step S04, the effective density of the pattern in the grid is obtained according to the density of the pattern in the grid after deposition and the characteristic correlation length.
In the embodiment of the invention, the influence of deposition on the graph density is fully considered, and after the graph density in the deposited grid is obtained, the influence of planarization is further considered to obtain the graph effective density in the grid for a planarization model.
The density of the pattern in the deposited grid may be obtained by any suitable method, and in some embodiments, the density after deposition may be obtained, for example, by the geometric relationship of the pattern in the deposited grid, and may be obtained, for example, by equation (2):
d(x，y)＝0.5*(1+d1(x，y)) (2)
wherein d is1Is the equivalent pattern density within the grid and d is the pattern density within the grid after deposition.
And obtaining the pattern density in the grid after deposition, and fully considering the characteristic correlation length to obtain the effective pattern density in the grid. The characteristic correlation length is an important parameter for measuring the influence degree of local graphic characteristics on the whole deformation of the grinding pad, the response range of the whole deformation of the grinding pad can be determined by using the characteristic correlation length, and the characteristic correlation length can be obtained through experimental data fitting.
In a specific embodiment, the effective density of the graph in the grid can be obtained in the following way:
first, the pattern density of the deposited mesh is smoothed.
During the smoothing, gaussian filtering can be adopted, and the influence of the characteristic correlation length is considered during the gaussian filtering, and the specific calculation formula is as follows:
where d (x, y) is the pattern density in the grid after deposition, ρ (x, y) is the pattern effective density, and PL is the feature correlation length.
And then, carrying out convolution operation on the formula to realize discretization processing. Specifically, the method can be implemented by using Fast Fourier Transform (FFT), and the specific calculation formula is as follows:
in this way, the effective density of the pattern of the mesh based on the correlation length of the features can be obtained.
In step S05, a contact pressure distribution within the grid of the chip surface is obtained.
After deposition, the initial topography of the chip surface has large fluctuation, and the calculation of the contact pressure needs to be optimized from the integral pressure distribution angle of the chip, so that the contact pressure can be reflected more really, in the preferred embodiment of the invention, the contact pressure of the chip surface is solved accurately by a contact mechanics equation, and the method specifically comprises the following steps:
firstly, a whole contact pressure equation set of the chip surface is established by utilizing the contact mechanics principle.
The set of equations is specifically as follows:
wherein upsilon is Poisson's ratio, E is elastic modulus, g (x, y, t) is the distance between the polishing pad and the chip surface after deformation, h (x, y, t) is the distance between the initial polishing pad and the chip surface, c is the overall displacement of the polishing pad, and ICIs a contact area; f0(t) is the applied load at time t, and I is the total contact surface area.
And then, solving the whole contact pressure equation set of the chip surface by using a fast Fourier transform and a conjugate gradient method to obtain the global contact pressure distribution of the chip surface.
In step S06, a grinding removal rate equation of the chip is established based on the graph effective density and the contact pressure distribution within the grid.
After determining the effective pattern density and contact pressure distribution within the grid in the above steps, an intra-grid grinding Removal Rate (MRR) model may be established. It will be appreciated that the removal rate is inversely proportional to the pattern effective density and directly proportional to the contact pressure, and based on this relationship, a suitable formula can be used to model the removal rate.
In a particular embodiment, the removal rate of grinding may be the Preston equation associated with the pressure profile: MRR kPV, where k is the coefficient, P is the pressure, and V is the rotational speed. In a specific embodiment of the present invention, a grinding removal rate model inside and outside the trench in the grid is respectively established according to Preston's formula, contact pressure and grinding removal rate, which is specifically as follows:
wherein MRRup、MRRdownRespectively, trench inside and outside polish removal rate, MRR0The polishing rate of the blank wafer without pattern, H is the relative height between the inside and the outside of the trench, HConIs the critical contact relative height. P0For the lapping initial pressure, ρ is the effective density obtained in the above step S04, and P is the contact pressure obtained in the above step S05.
In step S07, the chip surface topography is simulated using the chip deposition surface topography height as an initial value according to the relationship between the chip topography height and the removal rate by grinding.
It can be known that the relationship between the profile height of the chip and the grinding removal rate equation is as follows:
s (x, y, t) is the profile height of any point on the surface of the chip during grinding time t, the initial surface profile height of the chip is obtained as an initial value, and a grinding removal rate model is established, so that the change of the surface profile of the chip can be obtained in simulation.
The simulation method can be applied to two stages of removing shallow channel isolation planarization Oxide (Oxide) of a FinFET device, in the first stage, Oxide of a single material is mainly removed, the influence of groove filling and overall pressure distribution on the appearance is large, the surface non-flatness is repaired at the stage, and then the surface of a graph is relatively flat.
In the second stage, silicon nitride (SiN) is used as a stop layer, Oxide residues are removed, disc defects and corrosion phenomena are serious due to the fact that the grinding rates of Oxide and SiN are different, and integral pressure distribution, effective density calculation and fine microscopic modeling of a grinding rate equation are of great importance to flatness simulation of a design graph. However, it should be noted that the unpatterned blank wafer polishing rates for the SiN and Oxide polishing were different, and the respective MRRs were selected in the simulation0。
The above describes in detail the planarization simulation method for shallow trench isolation of FinFET device in the embodiment of the present invention, and in addition, the present invention further provides a planarization simulation system for shallow trench isolation of FinFET device for implementing the above method, which is shown in fig. 2 and includes:
the layout dividing and parameter acquiring unit is used for carrying out grid division on the chip layout and respectively extracting layout characteristic parameters in grids, wherein the layout characteristic parameters comprise equivalent line width, equivalent spacing and equivalent graph density;
the chip deposition surface height acquisition unit is used for acquiring a chip deposition surface height model after oxide deposition so as to provide the initial surface morphology height of the chip, and the chip deposition surface height model is related to the layout characteristic parameters;
a pattern density obtaining unit after deposition, which is used for obtaining the pattern density in the grid after the oxide deposition;
the effective density obtaining unit is used for obtaining the effective density of the graph in the grid according to the graph density and the characteristic correlation length in the grid after deposition;
a contact pressure acquisition unit for acquiring a contact pressure distribution in the grid on the surface of the chip;
the grinding removal rate obtaining unit is used for establishing a grinding removal rate model of the chip according to the graph effective density and the contact pressure distribution in the grid;
and the appearance simulation unit is used for carrying out the surface appearance simulation of the chip according to the relation between the appearance height of the chip and the grinding removal rate equation by taking the initial surface appearance height of the chip as an initial value.
Further, in the effective density obtaining unit, the graph density in the deposited grid is sequentially subjected to smoothing filtering processing and convolution operation, and the graph effective density in the grid under the influence of the characteristic correlation length is obtained.
Further, in the contact pressure obtaining unit, a whole contact pressure equation set of the chip surface is established by utilizing a contact mechanics principle; and obtaining the contact pressure distribution in the grid of the chip surface from the whole contact pressure equation set of the chip surface by using a fast Fourier transform and a conjugate gradient method.
Further, in the grinding removal rate obtaining unit, according to the Preston formula, the contact pressure and the grinding removal rate, grinding removal rate models inside and outside the groove in the grid are respectively established.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, they are described in a relatively simple manner, and reference may be made to some descriptions of method embodiments for relevant points. The above-described system embodiments are merely illustrative, wherein the modules or units described as separate parts may or may not be physically separate, and the parts displayed as modules or units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Claims (8)
1. A planarization simulation method for shallow trench isolation of a FinFET device is characterized by comprising the following steps:
carrying out grid division on a chip layout, and respectively extracting layout characteristic parameters in a grid, wherein the layout characteristic parameters comprise equivalent line width, equivalent spacing and equivalent graph density;
obtaining a chip deposition surface height model after oxide deposition to provide an initial surface morphology height of a chip, wherein the chip deposition surface height model is related to a layout characteristic parameter;
obtaining the pattern density in the grid after the oxide deposition;
obtaining the effective density of the pattern in the grid according to the pattern density and the characteristic correlation length in the deposited grid;
obtaining contact pressure distribution in the grid on the surface of the chip;
establishing a grinding removal rate model of the chip according to the effective density of the graph in the grid and the contact pressure distribution;
and taking the initial surface morphology height of the chip as an initial value, and carrying out the surface morphology simulation of the chip according to the relationship between the morphology height of the chip and the grinding removal rate equation.
2. The method of claim 1, wherein obtaining the effective density of the pattern in the grid based on the density of the pattern in the grid after deposition and the correlation length of the features comprises:
and sequentially carrying out smoothing filtering processing and convolution operation on the graph density in the deposited grid to obtain the graph effective density in the grid under the influence of the characteristic correlation length, wherein Gaussian filtering processing is adopted during smoothing filtering processing, the characteristic correlation length is introduced during Gaussian filtering processing, and fast Fourier transform processing is adopted during convolution operation.
3. The method of claim 1, wherein obtaining the contact pressure distribution within the grid of the chip surface comprises:
establishing a whole contact pressure equation set on the surface of the chip by utilizing a contact mechanics principle;
and obtaining the contact pressure distribution in the grid of the chip surface from the whole contact pressure equation set of the chip surface by using a fast Fourier transform and a conjugate gradient method.
4. The method of claim 1, wherein said modeling the removal rate of the wafer based on the effective density and contact pressure distribution of the pattern within the grid comprises:
and respectively establishing grinding removal rate models inside and outside the grooves in the grids according to a Preston formula, the contact pressure and the grinding removal rate.
5. A planarization simulation system for shallow trench isolation of FinFET device, comprising:
the layout dividing and parameter acquiring unit is used for carrying out grid division on the chip layout and respectively extracting layout characteristic parameters in grids, wherein the layout characteristic parameters comprise equivalent line width, equivalent spacing and equivalent graph density;
the chip deposition surface height acquisition unit is used for acquiring a chip deposition surface height model after oxide deposition so as to provide the initial surface morphology height of the chip, and the chip deposition surface height model is related to the layout characteristic parameters;
a pattern density obtaining unit after deposition, which is used for obtaining the pattern density in the grid after the oxide deposition;
the effective density obtaining unit is used for obtaining the effective density of the graph in the grid according to the graph density and the characteristic correlation length in the grid after deposition;
a contact pressure acquisition unit for acquiring a contact pressure distribution in the grid on the surface of the chip;
the grinding removal rate obtaining unit is used for establishing a grinding removal rate model of the chip according to the graph effective density and the contact pressure distribution in the grid;
and the appearance simulation unit is used for carrying out the surface appearance simulation of the chip according to the relation between the appearance height of the chip and the grinding removal rate equation by taking the initial surface appearance height of the chip as an initial value.
6. The simulation system according to claim 5, wherein in the effective density obtaining unit, the pattern density in the deposited grid is sequentially subjected to smoothing filtering processing and convolution operation to obtain the pattern effective density in the grid under the influence of the characteristic correlation length, wherein the smoothing filtering processing is performed by adopting Gaussian filtering processing, the characteristic correlation length is introduced when the Gaussian filtering processing is performed, and the convolution operation is performed by adopting fast Fourier transform processing.
7. The simulation system according to claim 5, wherein in the contact pressure acquisition unit, a chip surface overall contact pressure equation set is established using a contact mechanics principle; and obtaining the contact pressure distribution in the grid of the chip surface from the whole contact pressure equation set of the chip surface by using a fast Fourier transform and a conjugate gradient method.
8. The simulation system according to claim 5, wherein the grinding removal rate obtaining unit is configured to build grinding removal rate models inside and outside the grooves in the grid according to the Preston's formula, the contact pressure, and the grinding removal rate, respectively.
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