CN108964654A - Single phase clock divider circuit and phase-locked loop circuit - Google Patents
Single phase clock divider circuit and phase-locked loop circuit Download PDFInfo
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- CN108964654A CN108964654A CN201710370989.9A CN201710370989A CN108964654A CN 108964654 A CN108964654 A CN 108964654A CN 201710370989 A CN201710370989 A CN 201710370989A CN 108964654 A CN108964654 A CN 108964654A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Abstract
A kind of single phase clock divider circuit and phase-locked loop circuit, the single phase clock divider circuit include: the first trigger and the second trigger and frequency dividing control unit；First trigger and the second trigger prime output unit each other；Output end of the output clock signal of second trigger as the single phase clock divider circuit；The frequency dividing control unit, including the 7th NMOS tube and the 8th NMOS tube；The grid end of 7th NMOS tube and the anti-phase output clock signal of first trigger couple；The source of 7th NMOS tube and the drain terminal of the 8th NMOS tube couple；The drain terminal and second trigger of 7th NMOS tube couple；The grid end of 8th NMOS tube and the control signal couple；The source and ground wire of 8th NMOS tube couple.Above-mentioned scheme, can simplify the structure of single phase clock divider circuit, and reduce power consumption.
Description
Technical field
The present invention relates to field of circuit technology, more particularly to a kind of single phase clock divider circuit and phase-locked loop circuit.
Background technique
Dual-modulus prescaler is an important functional module of phaselocked loop, and frequency range determines the work of whole system
Make speed, and its performance will affect the performance of whole system.In phase-locked loop frequency synthesizer, frequency divider is work in highest
One of module of frequency, the consumed other modules of energy ratio are more, therefore how research reduces the complexity of pre-divider design
Degree, increases speed, and reduces power consumption and has great importance.
Wherein, one of dual-modulus prescaler single phase clock divider circuit is made of single phase clock circuit (TSPC)
Trigger constitute comprising level Four phase inverter, and being triggered by rising edge, since it has the advantages that low in energy consumption obtained extensively
Application.
But existing single phase clock divider circuit, it there is a problem that structure is complicated and power consumption is big.
Summary of the invention
Technical problems to be solved of the embodiment of the present invention are how to simplify the structure of single phase clock divider circuit, and reduce
Power consumption.
To solve the above-mentioned problems, the embodiment of the present invention provides a kind of single phase clock divider circuit, comprising: the first triggering
Device and the second trigger and frequency dividing control unit；First trigger and the second trigger prime output unit each other；Described first
The anti-phase output clock signal of the input terminal of trigger and second trigger couples, the anti-phase output of first trigger
Clock signal and the frequency dividing control unit couple, the output clock signal of first trigger and second trigger
Input terminal coupling；The output clock signal of the input terminal of second trigger and first trigger couples, and described second
The input terminal of the anti-phase output clock signal of trigger and first trigger couples, the output clock of second trigger
Output end of the signal as the single phase clock divider circuit；The frequency dividing control unit, including the 7th NMOS tube and the 8th
NMOS tube；The grid end of 7th NMOS tube and the anti-phase output clock signal of first trigger couple；Described 7th
The drain terminal of the source of NMOS tube and the 8th NMOS tube couples；The drain terminal and the second trigger coupling of 7th NMOS tube
It connects；The grid end of 8th NMOS tube and the control signal couple；The source and ground wire of 8th NMOS tube couple.
Optionally, it is anti-to respectively include the first rank rp unit, second-order for first trigger and second trigger
Phase element, third rank rp unit and fourth order rp unit；The first rank rp unit, suitable for by prime output unit
Anti-phase output clock signal carries out reverse phase processing, obtains corresponding first rank output signal；The second-order rp unit, is suitable for
The first rank output signal is subjected to reverse phase processing, obtains corresponding second-order output signal；The third rank rp unit,
Suitable for the second-order output signal is carried out reverse phase processing, corresponding third rank output signal is obtained；The fourth order reverse phase
Unit, suitable for the third rank output signal is converted to the fourth order output signal；The fourth order output signal and institute
State third rank output signal inversion signal each other, and the output signal as corresponding trigger.
Optionally, the first rank rp unit includes the first PMOS tube, the second PMOS tube and the first NMOS tube；Described
The grid end of one PMOS tube and preset input clock signal couple；The source of first PMOS tube and preset supply coupling；
The source of the drain terminal of first PMOS tube and second PMOS tube couples；The grid end of second PMOS tube and described second
The anti-phase output clock signal of trigger couples；The drain terminal of second PMOS tube and the drain terminal of first NMOS tube couple,
And the output end as the first rank anti-phase output unit；The grid end of first NMOS tube is anti-with second trigger
Mutually output clock signal coupling；The source and ground wire of first NMOS tube couple.
Optionally, the second-order rp unit includes third PMOS tube, the second NMOS tube and third NMOS tube；Described
The grid end of three PMOS tube and the input clock signal couple；The source of the third PMOS tube and preset supply coupling；Institute
The drain terminal of the drain terminal and second NMOS tube of stating third PMOS tube couples, and the output as the second-order rp unit
End；The output end of the grid end of second NMOS tube and the first rank rp unit couples；The source of second NMOS tube
It is coupled with the drain terminal of the third NMOS tube；The grid end of the third NMOS tube and the input clock signal couple；Described
The source and ground wire of three NMOS tubes couple.
Optionally, the third rank rp unit includes the 4th PMOS tube, the 4th NMOS tube and the 5th NMOS tube；Described
The grid end of the grid end of four PMOS tube and the 4th NMOS tube is coupled with the output end of the second-order anti-phase output unit；Institute
State the 4th PMOS tube source and preset supply coupling；The drain terminal of 4th PMOS tube and the drain terminal coupling of the 4th NMOS tube
It connects, and the inverting clock signal output end as the output end of the third rank rp unit and corresponding trigger；Described 4th
The drain terminal of the source of NMOS tube and the 5th NMOS tube couples；The grid end of 5th NMOS tube and the input clock signal
Coupling；The source and ground wire of 5th NMOS tube couple.
Optionally, the fourth order rp unit includes the 5th PMOS tube and the 6th NMOS tube；5th PMOS tube
The grid end of grid end and the 6th NMOS tube is coupled with the output end of the third rank rp unit respectively；5th PMOS tube
Source and supply coupling；The drain terminal of 5th PMOS tube and the drain terminal of the 6th NMOS tube couple, and as described the
The clock signal output terminal of the output end of quadravalence rp unit and corresponding trigger；The source and ground wire coupling of 6th NMOS tube
It connects.
Optionally, the output end coupling of the second-order rp unit of the drain terminal and second trigger of the 7th NMOS tube
It connects.
The embodiment of the invention also provides a kind of phase-locked loop circuits, including above-mentioned single phase clock divider circuit.
Compared with prior art, technical solution of the present invention has the advantages that
Above-mentioned scheme is high level in control signal by using the frequency dividing control unit being made of two NMOS tubes
When with low level, the function of 3 or 4 frequency dividings of single phase clock frequency divider is realized respectively, due to point constituted using two NMOS tubes
Frequency control unit replaces the frequency dividing control unit being made of two OR-NOT circuits, it is possible to reduce single phase clock frequency divider is used
The number of device and reduce power consumption so as to simplify the structure of single phase clock frequency divider.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of single phase clock divider circuit；
Fig. 2 is a kind of circuit diagram of single phase clock divider circuit；
Fig. 3 is the structural schematic diagram of one of embodiment of the present invention single phase clock divider circuit；
Fig. 4 is the circuit diagram of one of embodiment of the present invention single phase clock divider circuit.
Specific embodiment
Referring to Fig. 1, a kind of 3/4 single phase clock divider circuit includes the first trigger being made of respectively TSPC circuit
101 and second trigger 102, the first nor gate G1 and the second nor gate G2.
Wherein, the clock signal input terminal CK of the first trigger 101 and the second trigger 102 respectively with input clock signal
Fin coupling, the first input end of the input terminal D of the first trigger 101 and the first nor gate G1 are anti-with the second trigger 102
Clock signal output end Qb coupling, the output end Q1 of the first trigger 101 is vacant, the inversion clock letter of the first trigger 101
The first input end coupling of number output end Qb1 and the second nor gate G2.
The second input terminal of first nor gate G1 and control signal MC coupling, the output end of the first nor gate G1 and second or
The second input terminal of NOT gate G2 couples, and the output end of the second nor gate G2 and the input terminal D of the second trigger are coupled.
Referring to fig. 2, the first trigger 101 and the second trigger 102 respectively include 4 rank rp units.Wherein, the first rank is anti-
Phase element includes the first PMOS tube MP1, the second PMOS tube MP2 and the first NMOS tube MN1；Second-order rp unit includes third
PMOS tube MP3, the second NMOS tube MN2 and third NMOS tube MN3；Third rank rp unit includes the 4th PMOS tube MP4, the 4th
NMOS tube MN4 and the 5th NMOS tube MN5；Fourth order rp unit includes the 5th PMOS tube MP5 and the 6th NMOS tube MP6.
In the first rank rp unit: the grid end of the first PMOS tube MP1 and preset input clock signal Fin coupling
It connects, the source of the first PMOS tube MP1 and preset power vd D are coupled, the drain terminal of the first PMOS tube MP1 and described the
The source of two PMOS tube MP2 couples；The grid end of the second PMOS tube MP2 and the coupling of the grid end of the first NMOS tube MN1 with work
For prime output unit trigger anti-phase output clock signal Qb or Qb1 coupling, the drain terminal of the second PMOS tube MP2 with
The drain terminal of the first NMOS tube MN1 couples, and the output end as the first rank rp unit；The first NMOS tube MN1's
Grid end and anti-phase output the clock signal Qb or Qb1 of the trigger as prime output unit are coupled；The first NMOS tube MN1
Source and ground wire GND couple.
In second-order rp unit: the grid end of the third PMOS tube MP3 and the input clock signal Fin are coupled；
The source and power vd D of the third PMOS tube MP3 couples；The drain terminal of the third PMOS tube MP3 and second NMOS tube
The drain terminal of MN2 couples, and the output end as second-order rp unit；The grid end of the second NMOS tube MN2 and the first rank are anti-
The output end of phase element couples；The drain terminal of the source of the second NMOS tube MN2 and the third NMOS tube MN3 couple；It is described
The grid end of third NMOS tube MN3 and the input clock signal Fin are coupled, the source and ground wire GND of the third NMOS tube MN3
Coupling.
In third rank rp unit: the grid end of the 4th PMOS tube MP4 and the grid end coupling of the 4th NMOS tube MN4
It connects, and the output end as second-order rp unit；The source of the 4th PMOS tube MP4 and the power vd D are coupled；It is described
The drain terminal of the drain terminal of 4th PMOS tube MP4 and the 4th NMOS tube MN4 couple, and as the output end of third rank rp unit and right
Answer the inverting clock signal output end of trigger；The source of the 4th NMOS tube MN4 and the drain terminal of the 5th NMOS tube MN5
Coupling；The grid end of the 5th NMOS tube MN5 and the input clock signal Fin are coupled；The source of 5th NMOS tube with
Ground wire GND coupling.
In fourth order rp unit: the grid end of the 5th PMOS tube MP5 and the grid end of the 6th NMOS tube MN6 with
The inverting clock signal output end of affiliated trigger couples；The source and power vd D of the 5th PMOS tube MP5 couples；It is described
The drain terminal of the drain terminal of 5th PMOS tube MP5 and the 6th NMOS tube MN6 couple；The source and ground of the 6th NMOS tube MN6
Line GND coupling.
It include the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 9th NMOS tube MN9 with continued reference to Fig. 2, the first nor gate G1
With the tenth NMOS tube MN10；Second nor gate G2 includes the 8th PMOS tube MP8, the 9th PMOS tube MP9, the 11st NMOS tube MN11
With the 12nd NMOS tube MN12.
Wherein, the grid end of the 6th PMOS tube MP6 and control signal MC coupling；The source and power vd D of 6th PMOS tube MP6
Coupling；The drain terminal of 6th PMOS tube MP6 and the source of the 7th PMOS tube MP7 couple；The grid end and the 9th of 7th PMOS tube MP7
The grid end of NMOS tube MN9 is coupled with the inverting clock signal output end Qb of the second trigger respectively；The drain terminal of 7th PMOS tube MP7
It is coupled respectively with the drain terminal of the drain terminal of the 9th NMOS tube MN9 and the tenth NMOS tube MN10, and as first nor gate
The output end of G1；The source of the 9th NMOS tube MN9 and the source of the tenth NMOS tube MN10 are coupled with ground wire GND, and the tenth
The grid end and control signal MC coupling of NMOS tube MN10.
The grid end of 8th PMOS tube MP8 and the inverting clock signal output end Qb1 of the first trigger are coupled, the 8th PMOS tube
The source and power vd D of MP8 couples, and the drain terminal of the 8th PMOS tube MP8 and the source of the 9th PMOS tube MP9 couple；9th PMOS
The grid end of pipe MP9 and the grid end of the tenth NMOS tube MN10 are coupled with the output end of the first nor gate G1 respectively, the 9th PMOS tube MP9
Drain terminal coupled respectively with the drain terminal of the drain terminal of the 11st NMOS tube MN11 and the 12nd NMOS tube MN12, and as described
The output end of second nor gate G2；The source of the 11st NMOS tube MN11 and the source of the 12nd NMOS tube MN12 with ground
Line GND coupling, the grid end of the 12nd NMOS tube MN12 and the inverting clock signal output end Qb1 of the first trigger are coupled.
The working principle of above-mentioned single phase clock divider circuit is as follows:
When control signal MC be equal to 1, as high level when, the first nor gate G1 output end output output signal perseverance be
Zero, so that the second nor gate G2 is equivalent to a phase inverter, to realize the function of 4 frequency dividings.
When control signal MC is equal to 0, as low level when, the output of the first nor gate G1 depends on the second trigger 102
Inverting clock signal output end Qb output signal level.Wherein, when the inverting clock signal of the second trigger 102 exports
Hold Qb output signal be zero, i.e., low level when, the first nor gate G1 export high level, at this time the second nor gate G2 output be 0,
Without waiting for the output valve of the first trigger；When the first nor gate G1 exports low level, the second nor gate G2 needs at this time
Its output valve is determined to the output valve of DFF1, to realize the function of 3 frequency dividings.
From the above description it can be seen that the TSPC fraction frequency device has used altogether 28 transistors, wherein first
Nor gate G1 and the second nor gate G2 respectively include 4 transistors, altogether 8 transistors.It can be seen that above-mentioned TSPC is divided
Transistor size used in device circuit is more, there is a problem that structure is complicated and power consumption is larger.
To solve the above problems, the technical solution of the embodiment of the present invention is by using the frequency dividing for including two NMOS tubes composition
Control unit realizes the function of 3 or 4 frequency dividings of single phase clock frequency divider when controlling signal is high level and low level respectively,
It, can since the frequency dividing control unit constituted using two NMOS tubes replaces the frequency dividing control unit being made of two OR-NOT circuits
To reduce the number of device used in single phase clock frequency divider, so as to simplify the structure of single phase clock frequency divider, and drop
Low-power consumption.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 3 shows the structural schematic diagram of one of embodiment of the present invention single phase clock divider circuit.Such as Fig. 3 institute
Show, the single phase clock divider circuit in the embodiment of the present invention, for realizing 3 frequency dividings or 4 frequency dividing function of input clock signal
Can, it can specifically include the first trigger 301, the second trigger 302 and frequency dividing control unit 303, and 301 He of the first trigger
Second trigger 302 prime output unit each other.
Wherein, the anti-phase output clock signal of the input terminal D of first trigger 301 and second trigger 302
Qb coupling, the anti-phase output clock signal Qb1 of first trigger 301 and the frequency dividing control unit 303 couple, and described the
The output clock signal Q1 of the first trigger of output clock signal Q1 301 of one trigger 301 is defeated with second trigger
Enter D is held to couple；The output clock signal Q1 of the input terminal D of second trigger 302 and first trigger 301 is coupled,
The input terminal D of the anti-phase output clock signal Qb of second trigger 302 and first trigger 301 is coupled, and described the
Output end Fout of the output clock signal Q of two triggers 302 as the single phase clock divider circuit.
The frequency dividing control unit 303, including two NMOS tubes, suitable for the control signal MC in input be high level when,
It controls first trigger 301 to be connected in series with second trigger 302, so that the frequency of output clock signal Q is
The one third of the frequency of input clock signal；When the control signal MC is low level, second trigger 302 is controlled
A clock cycle is skipped, so that the frequency of output clock signal Q is a quarter of the frequency of input clock signal.
Referring to fig. 4, the first trigger in the embodiment of the present invention and the second trigger respectively include the first rank rp unit,
Second-order rp unit, third rank rp unit and fourth order rp unit.Wherein, the first rank rp unit includes the first PMOS
Pipe MP1, the second PMOS tube MP2 and the first NMOS tube MN1；Second-order rp unit includes third PMOS tube MP3, the second NMOS tube
MN2 and third NMOS tube MN3；The 4th PMOS tube MP4 of third rank rp unit, the 4th NMOS tube MN4 and the 5th NMOS tube MN5；
Fourth order rp unit includes the 5th PMOS tube MP6 and the 6th NMOS tube MN6.First trigger 301 and the second trigger 302
Structure refers to the introduction in Fig. 2, is no longer being described in detail.
With continued reference to Fig. 4, one of embodiment of the present invention frequency dividing control unit includes the 7th NMOS tube MN7 and the 8th
NMOS tube MN8.Wherein, the anti-phase output clock signal of the grid end of the 7th NMOS tube MN7 and first trigger 301
Qb1 coupling, the source of the 7th NMOS tube MN7 and the drain terminal of the 8th NMOS tube MN8 couple, the 7th NMOS tube
The output end S22 of the second-order rp unit of the drain terminal of MN7 and second trigger 302 is coupled；The 8th NMOS tube MN8
Grid end and the control signal MC couple, the source of the 8th NMOS tube MN8 and ground wire GND coupling.
The circuit for referring to single phase clock frequency divider described in Fig. 3 and Fig. 4, N17 and N18 structure when controlling signal MC=0
At frequency dividing control unit opened from entire Circuit Interrupt so that the first trigger 301 and the second trigger 302 are connected in series, from
And realize the function of 4 frequency dividings；N17 and N18 when controlling signal MC is high level, i.e. MC=1, in frequency dividing control unit 303
It controls entire circuit and skips a clock cycle in the anti-phase output clock signal Qb=0 of the second trigger, to realize 3 points
The function of frequency.
The embodiment of the invention also provides a kind of phase-locked loop circuits, including single phase clock divider circuit, wherein when single-phase
The structure of clock divider circuit refers to the introduction of aforementioned relevant portion, repeats no more.
In conclusion using the single phase clock divider circuit in the embodiment of the present invention, by including two NMOS tube structures
At frequency dividing control unit, can control signal be high level and low level when, respectively realize single phase clock frequency divider 3 or
The function of 4 frequency dividings, compared with the frequency dividing control unit constituted using two OR-NOT circuits, it is possible to reduce single phase clock frequency divider
The number of used device so as to simplify the structure of single phase clock frequency divider, and reduces power consumption.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (8)
1. a kind of single phase clock divider circuit characterized by comprising the first trigger and the second trigger and frequency dividing control
Unit；First trigger and the second trigger prime output unit each other；
The anti-phase output clock signal of the input terminal of first trigger and second trigger couples, first triggering
The anti-phase output clock signal of device and the frequency dividing control unit couple, the output clock signal of first trigger with it is described
The input terminal of second trigger couples；The output clock signal coupling of the input terminal of second trigger and first trigger
It connects, the input terminal of the anti-phase output clock signal of second trigger and first trigger couples, second triggering
Output end of the output clock signal of device as the single phase clock divider circuit；
The frequency dividing control unit, including the 7th NMOS tube and the 8th NMOS tube；The grid end of 7th NMOS tube and described the
The anti-phase output clock signal of one trigger couples；The source of 7th NMOS tube and the drain terminal coupling of the 8th NMOS tube
It connects；The drain terminal and second trigger of 7th NMOS tube couple；The grid end of 8th NMOS tube and the control are believed
Number coupling；The source and ground wire of 8th NMOS tube couple.
2. single phase clock divider circuit according to claim 1, which is characterized in that first trigger and described
Two triggers respectively include the first rank rp unit, second-order rp unit, third rank rp unit and fourth order rp unit；
The first rank rp unit is obtained suitable for the anti-phase output clock signal of prime output unit is carried out reverse phase processing
Corresponding first rank output signal；
The second-order rp unit is suitable for the first rank output signal carrying out reverse phase processing, obtains corresponding second-order
Output signal；
The third rank rp unit is suitable for the second-order output signal carrying out reverse phase processing, obtains corresponding third rank
Output signal；
The fourth order rp unit, suitable for the third rank output signal is converted to the fourth order output signal；It is described
Fourth order output signal and the third rank output signal inversion signal, and the output signal as corresponding trigger each other.
3. single phase clock divider circuit according to claim 2, which is characterized in that the first rank rp unit includes
First PMOS tube, the second PMOS tube and the first NMOS tube；
The grid end of first PMOS tube and preset input clock signal couple；The source of first PMOS tube with it is preset
Supply coupling；The source of the drain terminal of first PMOS tube and second PMOS tube couples；
The grid end of second PMOS tube and the anti-phase output clock signal of second trigger couple；Second PMOS tube
Drain terminal and the drain terminal of first NMOS tube couple, and the output end as the first rank anti-phase output unit；
The grid end of first NMOS tube and the anti-phase output clock signal of second trigger couple；First NMOS tube
Source and ground wire couple.
4. single phase clock divider circuit according to claim 2, which is characterized in that the second-order rp unit includes
Third PMOS tube, the second NMOS tube and third NMOS tube；
The grid end of the third PMOS tube and the input clock signal couple；The source of the third PMOS tube and preset electricity
Source coupling；The drain terminal of the third PMOS tube and the drain terminal of second NMOS tube couple, and as the second-order reverse phase list
The output end of member；
The output end of the grid end of second NMOS tube and the first rank rp unit couples；The source of second NMOS tube
It is coupled with the drain terminal of the third NMOS tube；
The grid end of the third NMOS tube and the input clock signal couple；The source and ground wire coupling of the third NMOS tube
It connects.
5. single phase clock divider circuit according to claim 2, which is characterized in that the third rank rp unit includes
4th PMOS tube, the 4th NMOS tube and the 5th NMOS tube；
The grid end of 4th PMOS tube and the grid end of the 4th NMOS tube are defeated with the second-order anti-phase output unit
Outlet coupling；The source of 4th PMOS tube and preset supply coupling；The drain terminal and the 4th NMOS of 4th PMOS tube
The drain terminal of pipe couples, and the inverting clock signal output as the output end of the third rank rp unit and corresponding trigger
End；
The source of 4th NMOS tube and the drain terminal of the 5th NMOS tube couple；The grid end of 5th NMOS tube with it is described
Input clock signal coupling；The source and ground wire of 5th NMOS tube couple.
6. single phase clock divider circuit according to claim 2, which is characterized in that the fourth order rp unit includes
5th PMOS tube and the 6th NMOS tube；
The grid end output with the third rank rp unit respectively of the grid end and the 6th NMOS tube of 5th PMOS tube
End coupling；The source and supply coupling of 5th PMOS tube；The drain terminal of 5th PMOS tube and the 6th NMOS tube
Drain terminal coupling, and the clock signal output terminal as the output end of the fourth order rp unit and corresponding trigger；Described
The source and ground wire of six NMOS tubes couple.
7. single phase clock divider circuit according to claim 2, which is characterized in that the drain terminal of the 7th NMOS tube with
The output end of the second-order rp unit of second trigger couples.
8. a kind of phase-locked loop circuit, which is characterized in that including the described in any item single phase clock frequency divider electricity of claim 1-7
Road.
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| CN201710370989.9A CN108964654A (en) | 2017-05-23 | 2017-05-23 | Single phase clock divider circuit and phase-locked loop circuit |
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| CN201710370989.9A CN108964654A (en) | 2017-05-23 | 2017-05-23 | Single phase clock divider circuit and phase-locked loop circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11342927B1 (en) | 2021-06-28 | 2022-05-24 | Qualcomm Incorporated | Ring oscillator based frequency divider |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11342927B1 (en) | 2021-06-28 | 2022-05-24 | Qualcomm Incorporated | Ring oscillator based frequency divider |
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Application publication date: 20181207 |