CN108923660A - A kind of synchronous rectifier converter - Google Patents
A kind of synchronous rectifier converter Download PDFInfo
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- CN108923660A CN108923660A CN201810921202.8A CN201810921202A CN108923660A CN 108923660 A CN108923660 A CN 108923660A CN 201810921202 A CN201810921202 A CN 201810921202A CN 108923660 A CN108923660 A CN 108923660A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
- H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
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- Rectifiers (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present invention relates to a kind of synchronous rectifier converters; include power circuit and control circuit; power circuit include switch metal-oxide-semiconductor and sampling metal-oxide-semiconductor, control circuit include open comparator, adjusting control circuit, shutdown comparator, driving circuit and can overheat protector output line loss compensation circuit；Control circuit output drive signal GATE receives the sampled signal VDET of power circuit output to power circuit；Sample metal-oxide-semiconductor accurately sampling switch metal-oxide-semiconductor source and drain interpolar voltage signal VDET, adjusting control circuit generates adjustment signal according to the point of adjustment of setting, driving signal GATE current potential is adjusted in advance, the turn-off speed of switch metal-oxide-semiconductor is dramatically speeded up, and is significantly improved using the reliability of the power-supply system of synchronous rectifier converter；The double-direction control of adjusting control circuit subtly adjusts GATE current potential, so that the voltage of switch metal-oxide-semiconductor source and drain interpolar is stabilized in the section of a very little, preferably cooperates the work of prime chip.
Description
Technical field
The present invention relates to a kind of synchronous rectifier converters, belong to switch power technology field.
Background technique
Currently, inverse-excitation type switch power-supply system is due to, input and output voltage isolation, at low cost, volume simple with circuit
The advantages that small and be widely used, but when output voltage is lower, output electric current it is larger when, traditional inverse-excitation type switch power-supply
The loss of secondary commutation diode current flow and reverse recovery loss in system is big, and efficiency is lower.In order to reduce rectifier diode
Loss replaces diode as rectifier using the extremely low switch metal-oxide-semiconductor of conducting resistance value, and this synchronous rectification can be very
The transfer efficiency of entire power-supply system is improved well.
Such as Fig. 1, the circuit block diagram of synchronous rectifier converter 100 uses a high voltage metal-oxide-semiconductor N2 conduct in control circuit
Metal-oxide-semiconductor is sampled, the drain-source voltage of metal-oxide-semiconductor N2 detection switch metal-oxide-semiconductor N1 is sampled, to obtain voltage sampling signal VDET for opening
It opens comparator 101 and shutdown comparator 102 judges.Comparator 101 is opened to produce sampled signal VDET compared with first threshold V1
Raw open signal SR_on；It turns off comparator 102 and sampled signal VDET is generated into cut-off signals SR_ compared with second threshold V2
off.Driving circuit 103 receives open signal SR_on and cut-off signals SR_off, generates driving signal GATE control switch MOS
The conducting and closing of pipe N1.
But there are problems for synchronous rectifier converter：First, the structure that sampling metal-oxide-semiconductor is separated with switch metal-oxide-semiconductor,
It is difficult to ensure accurate detection of the sampling metal-oxide-semiconductor to voltage change between switch metal-oxide-semiconductor hourglass source electrode, then cannot achieve whole to synchronizing
Stream transformer more accurately controls；Second, when synchronous rectifier converter work is in continuous conduction mode, shutdown comparator is difficult to
The current potential of driving signal GATE is dragged down from high point promptly, there is straight-through situation between primary and secondary, lead to secondary negative electricity rheology
Greatly, excessive secondary negative current will cause the damage of system.Third, the power-supply system where synchronous rectifier converter work in weight
When load, biggish output electric current can cause certain loss of voltage on the output line, may make the voltage for being provided to load end
Beyond specification, and it is secondary do not have overheat protector function, cannot when operating ambient temperature is excessively high timely protection power source system.
Summary of the invention
The purpose of the present invention is overcoming the shortcomings of the prior art, a kind of synchronous rectifier converter is provided.
The purpose of the present invention is achieved through the following technical solutions：
A kind of synchronous rectifier converter, includes power circuit and control circuit, and feature is：
The power circuit includes switch metal-oxide-semiconductor and sampling metal-oxide-semiconductor, and the control circuit includes opening comparator, adjusting
Control circuit, shutdown comparator, driving circuit and can overheat protector output line loss compensation circuit；
The switch metal-oxide-semiconductor and the drain electrode for sampling metal-oxide-semiconductor are connected with high pressure port；
The grid of the switch metal-oxide-semiconductor is connected with driving circuit, receives the driving signal of its output, switchs the source of metal-oxide-semiconductor
Pole is connected with reference ground mouth；
The grid of the sampling metal-oxide-semiconductor is connected with supply port, and the source electrode connection for sampling metal-oxide-semiconductor is opened comparator, adjusted
Control circuit and shutdown comparator, export sampled signal to it；
The end A for opening comparator connects first threshold, and the end B is connected with the source electrode of sampling metal-oxide-semiconductor, receives sampling letter
Number, and open comparator and be connected with driving circuit, output open signal to driving circuit；
The adjusting controller is connected with the source electrode of sampling metal-oxide-semiconductor, receives sampled signal, and be connected with driving circuit, defeated
Pull up signal is adjusted out and adjusts pulldown signal to driving circuit；
The end B of the shutdown comparator connects second threshold, and the end A is connected with the source electrode of sampling metal-oxide-semiconductor, receives sampling letter
Number, and turn off comparator and be connected with driving circuit, output cut-off signals to driving circuit；
Comparator, adjusting control circuit and shutdown comparator are opened in the driving circuit connection, receive open ratio respectively
Compared with the open signal of device output, the adjusting pull up signal of adjusting control circuit output and adjust pulldown signal, shutdown comparator
The cut-off signals of output, and the grid of connection switch metal-oxide-semiconductor and can overheat protector output line loss compensation circuit, output driving letter
Number to switch metal-oxide-semiconductor grid and can overheat protector output line loss compensation circuit；
It is described can overheat protector output line loss compensation circuit connection switch metal-oxide-semiconductor grid and driving circuit, receive drive
The driving signal of dynamic circuit output, and be connected with compensation port.
Further, above-mentioned a kind of synchronous rectifier converter, wherein the switch metal-oxide-semiconductor is integrated in sampling metal-oxide-semiconductor
It is common substrate structure on same silicon wafer.
Further, a kind of above-mentioned synchronous rectifier converter, wherein sampling metal-oxide-semiconductor detection switch metal-oxide-semiconductor source and drain interpolar
Voltage signal, and export sampled signal to control circuit；Control circuit is generated open signal, is adjusted by processing sampled signal
It saves pull up signal, adjust pulldown signal and cut-off signals, adjustment is connected to the current potential of the driving signal of switch metal-oxide-semiconductor grid, control
Synchronous rectifier converter processed is opened and shut off.
Further, above-mentioned a kind of synchronous rectifier converter, wherein the adjusting control circuit includes upper and lower two sons electricity
Road, wherein upper sub-circuit includes the first PMOS tube, the second PMOS tube, the first NPN pipe, the 2nd NPN pipe, the 3rd NPN pipe, the 4th
NPN pipe, first resistor, second resistance, the first current source and the second current source, source electrode and the supply port phase of the first PMOS tube
Even, grid connects the collector of the drain electrode of itself, the grid of the second PMOS tube and the first NPN pipe；
The source electrode of second PMOS tube is connected with supply port, and grid connects the grid of the first PMOS tube, the first PMOS tube
Drain electrode and the first NPN pipe collector, drain electrode connection the 4th NPN pipe collector and output end Reg_off；
The collector of first NPN pipe connects the grid of the first PMOS tube, the drain electrode of the first PMOS tube and the second PMOS tube
Grid, emitter connect reference ground mouth, and base stage connects the collector and first of the base stage of the 2nd NPN pipe, the 2nd NPN pipe
One end of resistance；
The base stage of 2nd NPN pipe connects one end of the collector of itself, the base stage of the first NPN pipe and first resistor, hair
Emitter-base bandgap grading connects input terminal VDET；
One end of the base stage connection second resistance of 3rd NPN pipe and the second current source, collector connect second resistance
The base stage of the other end, the 4th NPN pipe, emitter connect reference ground mouth；
The base stage of 4th NPN pipe connects one end of the collector of the 3rd NPN pipe, second resistance, collector connection second
The drain electrode of PMOS tube and output end Reg_off, emitter connect input terminal VDET；
One end of first resistor connects base stage, the collector of the 2nd NPN pipe and the base stage of the first NPN pipe of the 2nd NPN pipe,
The other end of first resistor connects the first current source；
One end of second resistance connects the collector of the 3rd NPN pipe and the base stage of the 4th NPN pipe, the other end of second resistance
Connect the second current source；
One end of first current source connection first resistor；
Second current source connects one end of second resistance and the base stage of the 3rd NPN pipe；
Lower sub-circuit includes third PMOS tube, the 4th PMOS tube, the 5th NPN pipe, the 6th NPN pipe, the 7th NPN pipe, the 8th
NPN pipe, 3rd resistor, the 4th resistance, third current source and the 4th current source, source electrode and the supply port phase of third PMOS tube
Even, grid connects the collector of the drain electrode of itself, the grid of the 4th PMOS tube and the 5th NPN pipe；
The source electrode of 4th PMOS tube is connected with supply port, and grid connects the grid of third PMOS tube, third PMOS tube
Drain electrode and the 5th NPN pipe collector, drain electrode connection the 8th NPN pipe collector and output end Reg_on；
The collector of 5th NPN pipe connects the grid of third PMOS tube, the drain electrode of third PMOS tube and the 4th PMOS tube
Grid, emitter connect input terminal VDET, and base stage connects the collector of the 6th NPN pipe and one end of 3rd resistor；
One end of the base stage connection 3rd resistor of 6th NPN pipe and third current source, emitter connect reference ground mouth,
Its collector connects the other end of 3rd resistor and the base stage of the 5th NPN pipe；
The base stage of 7th NPN pipe connects one end of the collector of itself, the base stage of the 8th NPN pipe and the 4th resistance, hair
Emitter-base bandgap grading connects input terminal VDET；
The base stage of 8th NPN pipe connects collector, the base stage of the 7th NPN pipe and one end of the 4th resistance of the 7th NPN pipe,
Its collector connects drain electrode and the output end Reg_on of the 4th PMOS tube, and emitter connects reference ground mouth；
One end of 3rd resistor connects the collector of the 6th NPN pipe and the base stage of the 5th NPN pipe, the other end of 3rd resistor
Connect the base stage and third current source of the 6th NPN pipe；
One end of 4th resistance connects collector, the base stage of the 7th NPN pipe and the base stage of the 8th NPN pipe of the 7th NPN pipe,
The other end of 4th resistance connects the 4th current source；
Third current source connects one end of 3rd resistor and the base stage of the 6th NPN pipe；
4th current source connects one end of the 4th resistance.
Further, above-mentioned a kind of synchronous rectifier converter, wherein to upper sub-circuit, when input terminal VDET voltage is big
When the third threshold value V3 of setting, output end Reg_off is high potential, that is, meets following relationship：
VDET+I1*R1>0
VDET>-I1*R1
Output end Reg_off is high potential.
Wherein, R1 refers to first resistor, and I1 refers to that the first current source, VDET refer to the sampled signal of input terminal input；By-I1*R1
It is defined as third threshold value V3, and first resistor in upper sub-circuit and second resistance such as are at the resistance of resistance values size, first electric current
Source and the second current source such as are at the current source of same currents size；
For lower sub-circuit, when input terminal VDET voltage is less than the 4th threshold value V4 of setting, output end Reg_on is height
Current potential meets following relationship：
VDET+I4*R4<0
VDET<-I4*R4
Output end Reg_on is high potential；
Wherein, R4 refers to that the 4th resistance, I4 refer to that the 4th current source, VDET refer to the sampled signal of input terminal input；By-I4*R4
It is defined as the 4th threshold value V4, and 3rd resistor in lower sub-circuit and the 4th resistance such as are at the resistance of resistance values size, the third electric current
Source and the 4th current source such as are at the current source of same currents size.
Further, above-mentioned a kind of synchronous rectifier converter, wherein it is described can overheat protector output line loss compensation electricity
Road includes the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS tube, the 9th PMOS tube, third NMOS tube, the 4th
NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the 9th NPN pipe, first
Voltage source, the 5th current source, the 6th current source, the 7th current source and the first logic inverter；
The source electrode of 5th PMOS tube is connected with supply port, grid connect the drain electrode of itself, the 6th PMOS tube grid,
The drain electrode of third NMOS tube and the drain electrode of the 5th NMOS tube；
The grid of 6th PMOS tube connects the grid of the 5th PMOS tube, the drain electrode of the 5th PMOS tube, the leakage of third NMOS tube
The drain electrode of pole and the 5th NMOS tube, source electrode are connected with supply port, the drain electrode of drain electrode the 8th NMOS tube of connection, the 4th NMOS
The input terminal of the grid of pipe and the first logic inverter；
The grid of 7th PMOS tube connects the collector and the 5th current source of the base stage of the 9th NPN pipe, the 9th NPN pipe,
Source electrode connect the 6th current source, drain electrode connection the drain electrode of the 6th NMOS tube, the grid of the 6th NMOS tube, the 5th NMOS tube grid
The grid of pole and third NMOS tube；
The grid of 8th PMOS tube connects first voltage source, and source electrode connects the 6th current source, drain electrode connection the 7th
The drain electrode of NMOS tube, the grid of the 7th NMOS tube and the 8th NMOS tube grid；
The grid of 9th PMOS tube connects the output end of the first logic inverter, receives overheat protector signal OTP, and source electrode connects
Connect the 7th current source, the drain electrode of drain electrode the 9th NMOS tube of connection and output compensation port；
The leakage of the grid, the grid, the 6th NMOS tube of the 6th NMOS tube of grid the 5th NMOS tube of connection of third NMOS tube
The drain electrode of pole and the 7th PMOS tube, the drain electrode connection grid of the 5th PMOS tube, the drain electrode of the 5th PMOS tube, the 6th PMOS tube
The drain electrode of grid and the 5th NMOS tube, source electrode are connected with the drain electrode of the 4th NMOS tube；
The grid of 4th NMOS tube connects the drain electrode of the 6th PMOS tube, the drain electrode of the 8th NMOS tube and the first logic inverter
Input terminal, the source electrode of drain electrode connection third NMOS tube, source electrode are connected with reference ground mouth；
5th NMOS tube grid connection the grid of third NMOS tube, the drain electrode of the 6th NMOS tube, the 6th NMOS tube grid
The drain electrode of pole and the 7th PMOS tube, the drain electrode connection grid of the 5th PMOS tube, the drain electrode of the 5th PMOS tube, the 6th PMOS tube
The drain electrode of grid and third NMOS tube, source electrode are connected with reference ground mouth；
The grid of 6th NMOS tube connects the drain electrode of itself, the grid of the 5th NMOS tube, the grid of third NMOS tube and
The drain electrode of seven PMOS tube, source electrode are connected with reference ground mouth；
The grid of 7th NMOS tube connects the drain electrode of the drain electrode of itself, the grid of the 8th NMOS tube and the 8th PMOS tube,
Source electrode is connected with reference ground mouth；
The grid of 8th NMOS tube connects grid, the drain electrode of the 7th NMOS tube and the leakage of the 8th PMOS tube of the 7th NMOS tube
Pole, drain electrode connection the 6th PMOS tube drain electrode, the grid of the 4th NMOS tube and the input terminal of the first logic inverter, source electrode with
Reference ground mouth is connected；
The grid of 9th NMOS tube is connected with input terminal GATE, drain electrode connection output compensation port and the 9th PMOS tube
Drain electrode, source electrode are connected with reference ground mouth；
The base stage of 9th NPN pipe connects the grid of the collector of itself, the 5th current source and the 7th PMOS tube, emitter
It is connected with reference ground mouth；
First voltage source connects the grid of the 8th PMOS tube；
5th current source connects base stage, the collector of the 9th NPN pipe and the grid of the 7th PMOS tube of the 9th NPN pipe；
6th current source connects the source electrode of the 7th PMOS tube and the source electrode of the 8th PMOS tube；
7th current source connects the source electrode of the 9th PMOS tube；
The input terminal of first logic inverter connects the drain electrode of the 6th PMOS tube, the grid of the 4th NMOS tube, the 8th NMOS tube
Drain electrode, output end connect the 9th PMOS tube grid, transmission overheat protector signal OTP to the 9th PMOS tube grid.
Further, above-mentioned a kind of synchronous rectifier converter, wherein when input drive signal GATE is high, the 9th
NMOS transistor conduction has an electric current Icomp to flow into from compensation port, realizes output line loss compensation using electric current；
The grid of 7th PMOS tube connects the base stage and collector of the 9th NPN pipe, the grid connection first of the 8th PMOS tube
Voltage source, the base stage of the 9th NPN pipe and the knot pressure drop VBE of transmitting interpolar are negative temperature coefficient, when the operating ambient temperature of chip
When excessively high, at this time：
VBE<V1
Then overheat protector signal OTP is low；
Wherein, VBE refers to the base stage of the 9th NPN pipe and the knot pressure drop of transmitting interpolar, and V1 refers to first voltage source；
When overheat protector signal OTP is low, the 9th PMOS tube conducting, an electric current Icomp utilizes electricity from port outflow is compensated
Stream realizes overheat protector.
The present invention has significant advantages and beneficial effects compared with prior art, embodies in the following areas：
It is total 1. the switch metal-oxide-semiconductor and sampling metal-oxide-semiconductor in synchronous rectifier converter power circuit are integrated on same silicon wafer
Substrat structure；Control circuit output drive signal GATE receives the sampled signal VDET of power circuit output to power circuit；
Sampling metal-oxide-semiconductor can accurately sample the voltage signal VDET of switch metal-oxide-semiconductor source and drain interpolar；
2. point of adjustment of the adjusting control circuit of synchronous rectifier converter according to precise voltage sampled signal in setting shifts to an earlier date
Driving signal GATE current potential is adjusted, the turn-off speed for switching metal-oxide-semiconductor can be accelerated, using the power-supply system of synchronous rectifier converter
Reliability is significantly improved；The double-direction control of adjusting control circuit can subtly adjust GATE current potential simultaneously, so that switch
The voltage of metal-oxide-semiconductor source and drain interpolar is stabilized in the section of a very little, preferably cooperates the work of prime chip.
3. synchronous rectifier converter increase compensation the port COMP, can overheat protector output line compensation circuit utilize the end COMP
Output line loss compensation function can be achieved in mouth, improves and exports line loss difference under different loads to the shadow of output voltage bring consistency
It rings；Output line compensation circuit utilizes the port COMP when detecting that operating ambient temperature is excessively high with overheat protector function simultaneously
Overheat protector, timely protection power source system can be achieved.
Other features and advantages of the present invention will be illustrated in subsequent specification, also, partly be become from specification
It is clear that by implementing specific embodiment of the invention understanding.The objectives and other advantages of the invention can be by institute
Specifically noted structure is achieved and obtained in specification, claims and the attached drawing write.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1：The circuit block diagram of background technique synchronous rectifier converter；
Fig. 2：The circuit block diagram of synchronous rectifier converter of the present invention；
Fig. 3：The structural schematic diagram of adjusting control circuit of the invention；
Fig. 4：The working waveform figure of synchronous rectifier converter of the invention；
Fig. 5：It is of the invention can overheat protector output line loss compensation circuit structural schematic diagram；
Fig. 6：Synchronous rectifier converter of the invention realizes the working waveform figure of output line loss compensation and overheat protector function.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
It should be noted that：Similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.Meanwhile of the invention
In description, directional terminology and ordinal term etc. are only used for distinguishing description, are not understood to indicate or imply relative importance.
It include power circuit and control circuit as shown in Fig. 2, a kind of synchronous rectifier converter,
Power circuit includes switch metal-oxide-semiconductor N1 and sampling metal-oxide-semiconductor N2, and control circuit includes opening comparator 201, adjusting control
Circuit 202 processed, shutdown comparator 203, driving circuit 204 and can overheat protector output line loss compensation circuit 205；
Switch metal-oxide-semiconductor N1 and the drain electrode for sampling metal-oxide-semiconductor N2 are connected with high pressure port SW；
The grid of switch metal-oxide-semiconductor N1 is connected with driving circuit 204, receives the driving signal GATE of its output, switchs metal-oxide-semiconductor
The source electrode of N1 is connected with reference ground mouth GND；
The grid of sampling metal-oxide-semiconductor N2 is connected with supply port VCC, and comparator is opened in the source electrode connection of sampling metal-oxide-semiconductor N2
201, adjusting control circuit 202 and shutdown comparator 203, export sampled signal VDET to it；
The end A for opening comparator 201 connects first threshold V1, and the end B is connected with the source electrode of sampling metal-oxide-semiconductor N2, and reception is adopted
Sample signal VDET, and open comparator 201 and be connected with driving circuit 204, output open signal SR_on to driving circuit 204；
Adjusting controller 202 with sampling metal-oxide-semiconductor N2 source electrode be connected, reception sampled signal VDET, and with driving circuit 204
It is connected, output adjusts pull up signal Reg_on and adjusts pulldown signal Reg_off to driving circuit 204；
The end B for turning off comparator 203 connects second threshold V2, and the end A is connected with the source electrode of sampling metal-oxide-semiconductor N2, and reception is adopted
Sample signal VDET, and turn off comparator 203 and be connected with driving circuit 204, output cut-off signals SR_off to driving circuit 204；
Comparator 201, adjusting control circuit 202 and shutdown comparator 203 are opened in the connection of driving circuit 204, are connect respectively
Receive open comparator 201 export open signal SR_on, adjusting control circuit 202 export adjusting pull up signal Reg_on with
And adjust pulldown signal Reg_off, the cut-off signals SR_off that shutdown comparator 203 exports, and the grid of connection switch metal-oxide-semiconductor N1
Pole and can overheat protector output line loss compensation circuit 205, output drive signal GATE to switch metal-oxide-semiconductor N1 grid and can mistake
The output line loss compensation circuit 205 of temperature protection；
Can overheat protector output 205 connection switch metal-oxide-semiconductor N1 of line loss compensation circuit grid and driving circuit 204, connect
The driving signal GATE that driving circuit 204 exports is received, and is connected with compensation port COMP.
Switch metal-oxide-semiconductor N1 and sampling metal-oxide-semiconductor N2 are integrated on same silicon wafer, are common substrate structure.
The voltage signal of metal-oxide-semiconductor N2 detection switch metal-oxide-semiconductor N1 source and drain interpolar is sampled, and exports sampled signal VDET to control
Circuit；Control circuit is generated open signal SR_on, is adjusted under pull up signal Reg_on, adjusting by processing sampled signal VDET
Signal Reg_off and cut-off signals SR_off is drawn, adjustment is connected to the current potential of the driving signal GATE of switch metal-oxide-semiconductor N1 grid,
Control synchronous rectifier converter is opened and shut off.
As shown in figure 3, adjusting control circuit 202 includes upper and lower two sub-circuit, wherein upper sub-circuit includes the first PMOS tube
P1, the second PMOS tube P2, the first NPN pipe Q1, the 2nd NPN pipe Q2, the 3rd NPN pipe Q3, the 4th NPN pipe Q4, first resistor R1,
Two resistance R2, the first current source I1 and the second current source I2, the source electrode of the first PMOS tube P1 are connected with supply port VCC, grid
Pole connects the collector of the drain electrode of itself, the grid of the second PMOS tube P2 and the first NPN pipe Q1；
The source electrode of second PMOS tube P2 is connected with supply port VCC, and grid connects the grid of the first PMOS tube P1, first
The drain electrode of PMOS tube P1 and the collector of the first NPN pipe Q1, the collector and output end Reg_ of the 4th NPN pipe Q4 of drain electrode connection
off；
The collector of first NPN pipe Q1 connects the drain electrode and second of the grid, the first PMOS tube P1 of the first PMOS tube P1
The grid of PMOS tube P2, emitter connect reference ground mouth GND, and base stage connects the base stage of the 2nd NPN pipe Q2, the 2nd NPN
The collector of pipe Q2 and one end of first resistor R1；
The base stage of 2nd NPN pipe Q2 connects the one of the collector of itself, the base stage of the first NPN pipe Q1 and first resistor R1
End, emitter connect input terminal VDET；
One end of the base stage connection second resistance R2 of 3rd NPN pipe Q3 and the second current source I2, collector connection second
The base stage of the other end of resistance R2, the 4th NPN pipe Q4, emitter connect reference ground mouth GND；
The base stage of 4th NPN pipe Q4 connects one end of the collector of the 3rd NPN pipe Q3, second resistance R2, and collector connects
Drain electrode and the output end Reg_off of the second PMOS tube P2 are met, emitter connects input terminal VDET；
One end of first resistor R1 connects the base stage of the 2nd NPN pipe Q2, the collector of the 2nd NPN pipe Q2 and the first NPN pipe
The other end of the base stage of Q1, first resistor R1 connects the first current source I1；
One end of second resistance R2 connects the collector of the 3rd NPN pipe Q3 and the base stage of the 4th NPN pipe Q4, second resistance R2
The other end connect the second current source I2；
One end of first current source I1 connection first resistor R1；
One end of second current source I2 connection second resistance R2 and the base stage of the 3rd NPN pipe Q3；
Lower sub-circuit includes third PMOS tube P3, the 4th PMOS tube P4, the 5th NPN pipe Q5, the 6th NPN pipe Q6, the 7th NPN
Pipe Q7, the 8th NPN pipe Q8,3rd resistor R3, the 4th resistance R4, third current source I3 and the 4th current source I4, third PMOS tube
The source electrode of P3 is connected with supply port VCC, and grid connects the drain electrode of itself, the grid of the 4th PMOS tube P4 and the 5th NPN pipe
The collector of Q5；
The source electrode of 4th PMOS tube P4 is connected with supply port VCC, and grid connects the grid of third PMOS tube P3, third
The drain electrode of PMOS tube P3 and the collector of the 5th NPN pipe Q5, the collector and output end Reg_ of the 8th NPN pipe Q8 of drain electrode connection
on；
The drain electrode and the 4th of the grid, third PMOS tube P3 of the collector connection third PMOS tube P3 of 5th NPN pipe Q5
The grid of PMOS tube P4, emitter connect input terminal VDET, and base stage connects the collector and 3rd resistor of the 6th NPN pipe Q6
One end of R3；
One end of the base stage connection 3rd resistor R3 of 6th NPN pipe Q6 and third current source I3, emitter connection reference
Ground port GND, collector connect the other end of 3rd resistor R3 and the base stage of the 5th NPN pipe Q5；
The base stage of 7th NPN pipe Q7 connects the one of the collector of itself, the base stage of the 8th NPN pipe Q8 and the 4th resistance R4
End, emitter connect input terminal VDET；
The base stage of 8th NPN pipe Q8 connects the base stage and the 4th resistance of the collector of the 7th NPN pipe Q7, the 7th NPN pipe Q7
One end of R4, collector connect drain electrode and the output end Reg_on of the 4th PMOS tube P4, and emitter connects reference ground mouth
GND；
One end of 3rd resistor R3 connects the collector of the 6th NPN pipe Q6 and the base stage of the 5th NPN pipe Q5,3rd resistor R3
The other end connect the 6th NPN pipe Q6 base stage and third current source I3；
One end of 4th resistance R4 connects the collector of the 7th NPN pipe Q7, the base stage of the 7th NPN pipe Q7 and the 8th NPN pipe
The other end of the base stage of Q8, the 4th resistance R4 connects the 4th current source I4；
One end of third current source I3 connection 3rd resistor R3 and the base stage of the 6th NPN pipe Q6；
One end of the 4th resistance R4 of 4th current source I4 connection.
For upper sub-circuit, when input terminal VDET voltage is greater than the third threshold value V3 of setting, output end Reg_off is height
Current potential meets following relationship：
VDET+I1*R1>0
VDET>-I1*R1
Output end Reg_off is high potential.
Wherein, R1 refers to first resistor, and I1 refers to that the first current source, VDET refer to the sampled signal of input terminal input；By-I1*R1
It is defined as third threshold value V3, and first resistor R1 in upper sub-circuit and second resistance R2 such as is at the resistance of resistance values size, first
Current source I1 and the second current source I2 be etc. same currents size current source；
For lower sub-circuit, when input terminal VDET voltage is less than the 4th threshold value V4 of setting, output end Reg_on is height
Current potential meets following relationship：
VDET+I4*R4<0
VDET<-I4*R4
Output end Reg_on is high potential；
Wherein, R4 refers to that the 4th resistance, I4 refer to that the 4th current source, VDET refer to the sampled signal of input terminal input；By-I4*R4
It is defined as the 4th threshold value V4, and 3rd resistor R3 in lower sub-circuit and the 4th resistance R4 such as is at the resistance of resistance values size, the third
Current source I3 and the 4th current source I4 be etc. same currents size current source.
As shown in figure 4, the working waveform figure of synchronous rectifier converter of the present invention, specific works mechanism is as follows：
Sampling metal-oxide-semiconductor N2 accurately samples the voltage signal VDET of switch metal-oxide-semiconductor N1 source and drain interpolar, and is transferred to unlatching
Comparator 201, adjusting control circuit 202 and shutdown comparator 203.
At the corresponding t0 moment, when the voltage of sampled signal VDET deteriorates to less than first threshold V1, unlatching comparator 201 is exported
Open signal SR_on be height, at this time driving circuit 204 quickly draws high be connected to switch metal-oxide-semiconductor N1 grid driving signal GATE.
In corresponding t0~t1 period, after switch metal-oxide-semiconductor N1 conducting, secondary current Ids is flowed through through switching metal-oxide-semiconductor N1, is adopted at this time
The voltage of sample signal VDET is begun to ramp up.
At the corresponding t1 moment, when the voltage of sampled signal VDET rises to greater than third threshold value V3, adjusting control circuit 202 is defeated
Adjusting pulldown signal Reg_off out is height, and driving circuit 204 drags down the driving signal for being connected to switch metal-oxide-semiconductor N1 grid at this time
GATE。
Corresponding t1~t2 period, after the driving signal GATE for switching metal-oxide-semiconductor N1 is pulled low, the voltage of sampled signal VDET
Slowly decline, when the voltage of sampled signal VDET deteriorates to less than the 4th threshold value V4, in the adjusting that adjusting control circuit 202 exports
Drawing signal Reg_on is height, and driving circuit 204 draws high the driving signal GATE for being connected to switch metal-oxide-semiconductor N1 grid, sampling letter at this time
The slowly decline again of the voltage of number VDET.In the period, driving signal GATE is repeatedly dragged down and is drawn high, sampled signal VDET's
Voltage is maintained between third threshold value V3 and the 4th threshold value V4.The bi-directional control signal that adjusting control circuit generates：In adjusting
It draws signal Reg_on and adjusts pulldown signal Reg_off, can subtly adjust GATE current potential, so that switch metal-oxide-semiconductor source and drain interpolar
Voltage be stabilized in the section of a very little, preferably cooperate prime chip work.
The corresponding t2 moment then flows through switch metal-oxide-semiconductor N1's if synchronous rectifier converter works in continuous conduction mode
The mutation of secondary current Ids descending slope, the voltage of sampled signal VDET are also mutated rising, when the voltage of sampled signal VDET rises
To more than when second threshold V2, the cut-off signals SR_off that shutdown comparator 203 exports is height, and driving circuit 204 is quick at this time
Drag down the driving signal GATE for being connected to switch metal-oxide-semiconductor N1 grid.Since driving signal GATE passes through the adjustment in t1~t2 period, this
When driving signal GATE current potential it is lower, driving circuit 204 receives promptly draw after high cut-off signals SR_off
Low driving signal GATE, secondary current Ids is not reversed at this time or reverse current very little, improves the reliability of system work.
As shown in figure 5, can overheat protector output line loss compensation circuit 205 include the 5th PMOS tube P5, the 6th PMOS tube
P6, the 7th PMOS tube P7, the 8th PMOS tube P8, the 9th PMOS tube P9, third NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS
Pipe N5, the 6th NMOS tube N6, the 7th NMOS tube N7, the 8th NMOS tube N8, the 9th NMOS tube N9, the 9th NPN pipe Q9, first voltage
Source V1, the 5th current source I5, the 6th current source I6, the 7th current source I7 and the first logic inverter M1；
The source electrode of 5th PMOS tube P5 is connected with supply port VCC, and grid connects the drain electrode of itself, the 6th PMOS tube P6
Grid, the drain electrode of third NMOS tube N3 and the drain electrode of the 5th NMOS tube N5；
The grid of 6th PMOS tube P6 connects the grid of the 5th PMOS tube P5, the drain electrode of the 5th PMOS tube P5, the 3rd NMOS
The drain electrode of pipe N3 and the drain electrode of the 5th NMOS tube N5, source electrode are connected with supply port VCC, the 8th NMOS tube N8 of drain electrode connection
Drain electrode, the grid of the 4th NMOS tube N4 and the input terminal of the first logic inverter M1；
The grid of 7th PMOS tube P7 connects the collector and the 5th electric current of the base stage of the 9th NPN pipe Q9, the 9th NPN pipe Q9
Source I5, source electrode connect the 6th current source I6, the grid of the drain drain electrode, the 6th NMOS tube N6 that connect the 6th NMOS tube N6,
The grid of 5th NMOS tube N5 and the grid of third NMOS tube N3；
The grid of 8th PMOS tube P8 connects first voltage source V1, and source electrode connects the 6th current source I6, drain electrode connection
Drain electrode, the grid of the 7th NMOS tube N7 and the grid of the 8th NMOS tube N8 of 7th NMOS tube N7；
The grid of 9th PMOS tube P9 connects the output end of the first logic inverter M1, receives overheat protector signal OTP, source
Pole connects the 7th current source I7, the drain electrode of the 9th NMOS tube N9 of drain electrode connection and output compensation port COMP；
The grid of third NMOS tube N3 connects grid, the 6th NMOS of the grid of the 5th NMOS tube N5, the 6th NMOS tube N6
The drain electrode of pipe N6 and the drain electrode of the 7th PMOS tube P7, the leakage of the grid, the 5th PMOS tube P5 of the 5th PMOS tube P5 of drain electrode connection
The drain electrode of pole, the grid of the 6th PMOS tube P6 and the 5th NMOS tube N5, source electrode are connected with the drain electrode of the 4th NMOS tube N4；
The grid of 4th NMOS tube N4 connects the drain electrode and the first logic of the drain electrode of the 6th PMOS tube P6, the 8th NMOS tube N8
The input terminal of NOT gate M1, the source electrode of drain electrode connection third NMOS tube N3, source electrode are connected with reference ground mouth GND；
The grid of the grid connection third NMOS tube N3 of 5th NMOS tube N5, the drain electrode of the 6th NMOS tube N6, the 6th NMOS
The drain electrode of the grid of pipe N6 and the 7th PMOS tube P7, the leakage of the grid, the 5th PMOS tube P5 of the 5th PMOS tube P5 of drain electrode connection
The drain electrode of pole, the grid of the 6th PMOS tube P6 and third NMOS tube N3, source electrode are connected with reference ground mouth GND；
The grid of 6th NMOS tube N6 connect the drain electrode of itself, the grid of the 5th NMOS tube N5, third NMOS tube N3 grid
The drain electrode of pole and the 7th PMOS tube P7, source electrode are connected with reference ground mouth GND；
The grid of 7th NMOS tube N7 connects the leakage of the drain electrode of itself, the grid of the 8th NMOS tube N8 and the 8th PMOS tube P8
Pole, source electrode are connected with reference ground mouth GND；
The grid of 8th NMOS tube N8 connects drain electrode and the 8th PMOS of the grid, the 7th NMOS tube N7 of the 7th NMOS tube N7
The drain electrode of pipe P8, drain electrode connect the drain electrode of the 6th PMOS tube P6, the grid of the 4th NMOS tube N4 and the first logic inverter M1
Input terminal, source electrode are connected with reference ground mouth GND；
The grid of 9th NMOS tube N9 is connected with input terminal GATE, drain electrode connection output compensation port COMP and the 9th
The drain electrode of PMOS tube P9, source electrode are connected with reference ground mouth GND；
The base stage of 9th NPN pipe Q9 connects the grid of the collector of itself, the 5th current source I5 and the 7th PMOS tube P7,
Emitter is connected with reference ground mouth GND；
The grid of the 8th PMOS tube P8 of first voltage source V1 connection；
5th current source I5) connect the base stage of the 9th NPN pipe Q9, the collector and the 7th PMOS tube P7 of the 9th NPN pipe Q9
Grid；
The source electrode of the 7th PMOS tube P7 of 6th current source I6 connection and the source electrode of the 8th PMOS tube P8；
The source electrode of the 9th PMOS tube P9 of 7th current source I7 connection；
The input terminal of first logic inverter M1 connects the drain electrode of the 6th PMOS tube P6, the grid of the 4th NMOS tube N4, the 8th
The drain electrode of NMOS tube N8, output end connect the grid of the 9th PMOS tube P9, transmission overheat protector signal OTP to the 9th PMOS tube
The grid of P9.
When input drive signal GATE is high, the 9th NMOS tube N9 conducting has an electric current Icomp from compensation port COMP
It flows into, realizes output line loss compensation using electric current；
The grid of 7th PMOS tube P7 connects the base stage and collector of the 9th NPN pipe Q9, and the grid of the 8th PMOS tube P8 connects
First voltage source V1 is met, the base stage of the 9th NPN pipe Q9 and the knot pressure drop VBE of transmitting interpolar are negative temperature coefficient, when the work of chip
Make environment temperature it is excessively high when, at this time：
VBE<V1
Then overheat protector signal OTP is low；
Wherein, VBE refers to the base stage of the 9th NPN pipe Q9 and the knot pressure drop of transmitting interpolar, and V1 refers to first voltage source；
When overheat protector signal OTP be it is low, the 9th PMOS tube P9 conducting, an electric current Icomp from compensation port COMP outflow,
Overheat protector is realized using electric current.
As shown in fig. 6, synchronous rectifier converter of the present invention realizes output line loss compensation and the work that overheat protector function is realized
Make waveform diagram, specific works mechanism is as follows：
Can overheat protector output line loss compensation circuit 205, receive driving circuit 204 input driving signal GATE,
GATE is switched on and off the difference of duration, can reflect the weight loaded at this time, at this time can be corresponding in the compensation port COMP
Electric current Icomp flow into, the electric current be average current.
Corresponding t0~t1 period judges light load at this time, compensates at this time according to the duration that is switched on and off of GATE
The port COMP flows into electric current Icomp1, and output end voltage Vout (solid line) is fine-tuning to Vo1, then the voltage of line end is basically stable at electricity
Press Vo nearby (dotted line).
In corresponding t1~t2 period, according to the duration that is switched on and off of GATE, judgement is loaded at this time relative to t0~t1
Period aggravates, and compensates the port COMP at this time and flows into electric current Icomp2, output end voltage Vout (solid line) is fine-tuning to Vo2, then line end
Voltage be basically stable at voltage Vo nearby (dotted line).
In corresponding t2~t3 period, according to the duration that is switched on and off of GATE, judgement is loaded at this time relative to t1~t2
Period further aggravates, and compensates the port COMP at this time and flows into electric current Icomp3, output end voltage Vout (solid line) is fine-tuning to
Vo3, then the voltage of line end is basically stable at voltage Vo nearby (dotted line).
The corresponding t3 moment, can the output line loss compensation circuit 205 of overheat protector detect that the operating temperature of chip is excessively high, this
When the compensation port COMP flow out electric current Icomp4, output end voltage Vout (solid line) is lowered to Vo4, the output power of power-supply system
Reduce, overheat protector is then realized in temperature decline.
In conclusion control circuit output drive signal GATE of the invention is to power circuit, and it is defeated to receive power circuit
Sampled signal VDET out；The sampling metal-oxide-semiconductor of synchronous rectifier converter can accurately sample the electricity of switch metal-oxide-semiconductor source and drain interpolar
Signal VDET is pressed, adjusting control circuit generates adjustment signal according to the point of adjustment of setting, driving signal GATE current potential is adjusted in advance,
The turn-off speed of switch metal-oxide-semiconductor is dramatically speeded up, and is significantly improved using the reliability of the power-supply system of synchronous rectifier converter；
The double-direction control of adjusting control circuit can subtly adjust GATE current potential, so that the voltage of switch metal-oxide-semiconductor source and drain interpolar is steady
It is scheduled in the section of a very little, preferably cooperates the work of prime chip；Meanwhile synchronous rectifier converter of the present invention increases benefit
Port COMP is repaid, it can be achieved that having the output line loss compensation function of overheat protector.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.It should be noted that：Similar label and letter exist
Similar terms are indicated in following attached drawing, therefore, once being defined in a certain Xiang Yi attached drawing, are then not required in subsequent attached drawing
It is further defined and explained.
The above is only a specific embodiment of the present invention, but scope of protection of the present invention is not limited thereto, any to be familiar with
Those skilled in the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all cover
Within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to protection scope described in claim.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
Claims (7)
1. a kind of synchronous rectifier converter includes power circuit and control circuit, it is characterised in that：
The power circuit includes switch metal-oxide-semiconductor (N1) and sampling metal-oxide-semiconductor (N2), and the control circuit includes opening comparator
(201), adjusting control circuit (202), shutdown comparator (203), driving circuit (204) and can overheat protector output line loss
Compensation circuit (205)；
Switch metal-oxide-semiconductor (N1) and the drain electrode for sampling metal-oxide-semiconductor (N2) are connected with high pressure port (SW)；
The grid of switch metal-oxide-semiconductor (N1) is connected with driving circuit (204), receives the driving signal (GATE) of its output, opens
The source electrode for closing metal-oxide-semiconductor (N1) is connected with reference ground mouth (GND)；
The grid of sampling metal-oxide-semiconductor (N2) is connected with supply port (VCC), and ratio is opened in the source electrode connection of sampling metal-oxide-semiconductor (N2)
Compared with device (201), adjusting control circuit (202) and shutdown comparator (203), sampled signal (VDET) is exported to it；
The end A for opening comparator (201) connects first threshold (V1), and the end B is connected with the source electrode of sampling metal-oxide-semiconductor (N2),
It receives sampled signal (VDET), and opens comparator (201) and be connected with driving circuit (204), output open signal (SR_on) is extremely
Driving circuit (204)；
The adjusting controller (202) with sampling metal-oxide-semiconductor (N2) source electrode be connected, reception sampled signal (VDET), and with driving
Circuit (204) is connected, and output adjusts pull up signal (Reg_on) and adjusts pulldown signal (Reg_off) to driving circuit
(204)；
The end B of shutdown comparator (203) connects second threshold (V2), and the end A is connected with the source electrode of sampling metal-oxide-semiconductor (N2),
It receives sampled signal (VDET), and turns off comparator (203) and be connected with driving circuit (204), export cut-off signals (SR_off)
To driving circuit (204)；
Comparator (201), adjusting control circuit (202) and shutdown comparator are opened in driving circuit (204) connection
(203), the tune of the open signal (SR_on) for opening comparator (201) output, adjusting control circuit (202) output is received respectively
It saves pull up signal (Reg_on) and adjusts the cut-off signals (SR_ of pulldown signal (Reg_off), shutdown comparator (203) output
Off), and the grid of connection switch metal-oxide-semiconductor (N1) and can overheat protector output line loss compensation circuit (205), output driving letter
Number (GATE) to switch metal-oxide-semiconductor (N1) grid and can overheat protector output line loss compensation circuit (205)；
It is described can overheat protector output line loss compensation circuit (205) connection switch metal-oxide-semiconductor (N1) grid and driving circuit
(204), the driving signal (GATE) of driving circuit (204) output is received, and is connected with compensation port (COMP).
2. a kind of synchronous rectifier converter according to claim 1, it is characterised in that：The switch metal-oxide-semiconductor (N1) with adopt
Sample metal-oxide-semiconductor (N2) is integrated on same silicon wafer, is common substrate structure.
3. a kind of synchronous rectifier converter according to claim 1 or 2, it is characterised in that：Sampling metal-oxide-semiconductor (N2) detection is opened
The voltage signal of metal-oxide-semiconductor (N1) source and drain interpolar is closed, and exports sampled signal (VDET) to control circuit；Control circuit passes through processing
Sampled signal (VDET) generates open signal (SR_on), adjusts pull up signal (Reg_on), adjusts pulldown signal (Reg_off)
And cut-off signals (SR_off), adjustment are connected to the current potential of the driving signal (GATE) of switch metal-oxide-semiconductor (N1) grid, control synchronizes
Rectifier converter is opened and shut off.
4. a kind of synchronous rectifier converter according to claim 1, it is characterised in that：The adjusting control circuit (202)
Include upper and lower two sub-circuit, wherein upper sub-circuit includes the first PMOS tube (P1), the second PMOS tube (P2), the first NPN pipe
(Q1), the 2nd NPN manages (Q2), the 3rd NPN pipe (Q3), the 4th NPN pipe (Q4), first resistor (R1), second resistance (R2), first
The source electrode of current source (I1) and the second current source (I2), the first PMOS tube (P1) is connected with supply port (VCC), grid connection
The drain electrode of itself, the grid of the second PMOS tube (P2) and the first NPN manage the collector of (Q1)；
The source electrode of second PMOS tube (P2) is connected with supply port (VCC), and grid connects the grid of the first PMOS tube (P1), the
The collector of the drain electrode of one PMOS tube (P1) and the first NPN pipe (Q1), drain electrode the 4th NPN of the connection pipe collector of (Q4) and defeated
Outlet Reg_off；
First NPN manages the drain electrode and second of the grid, the first PMOS tube (P1) of the collector connection the first PMOS tube (P1) of (Q1)
The grid of PMOS tube (P2), emitter connect reference ground mouth (GND), and base stage connects the base stage of the 2nd NPN pipe (Q2), the
Two NPN manage the collector of (Q2) and one end of first resistor (R1)；
The base stage of 2nd NPN pipe (Q2) connects the one of the collector of itself, the base stage of the first NPN pipe (Q1) and first resistor (R1)
End, emitter connect input terminal VDET；
3rd NPN manages one end and the second current source (I2) of base stage connection second resistance (R2) of (Q3), collector connection the
The other end, the 4th NPN of two resistance (R2) manage the base stage of (Q4), and emitter connects reference ground mouth (GND)；
The base stage that 4th NPN manages (Q4) connects one end of the collector of the 3rd NPN pipe (Q3), second resistance (R2), collector
Drain electrode and the output end Reg_off of the second PMOS tube (P2) are connected, emitter connects input terminal VDET；
One end of first resistor (R1) connects the collector and the first NPN of the base stage of the 2nd NPN pipe (Q2), the 2nd NPN pipe (Q2)
The base stage of (Q1) is managed, the other end of first resistor (R1) connects the first current source (I1)；
One end of second resistance (R2) connects the collector of the 3rd NPN pipe (Q3) and the base stage of the 4th NPN pipe (Q4), second resistance
(R2) the other end connects the second current source (I2)；
First current source (I1) connects the one end of first resistor (R1)；
Second current source (I2) connects the one end of second resistance (R2) and the base stage of the 3rd NPN pipe (Q3)；
Lower sub-circuit includes third PMOS tube (P3), the 4th PMOS tube (P4), the 5th NPN pipe (Q5), the 6th NPN pipe (Q6), the
Seven NPN manage (Q7), the 8th NPN pipe (Q8), 3rd resistor (R3), the 4th resistance (R4), third current source (I3) and the 4th electric current
The source electrode in source (I4), third PMOS tube (P3) is connected with supply port (VCC), and grid connects the drain electrode of itself, the 4th PMOS
Manage the grid of (P4) and the collector of the 5th NPN pipe (Q5)；
The source electrode of 4th PMOS tube (P4) is connected with supply port (VCC), and grid connects the grid of third PMOS tube (P3), the
The collector of the drain electrode of three PMOS tube (P3) and the 5th NPN pipe (Q5), drain electrode the 8th NPN of the connection pipe collector of (Q8) and defeated
Outlet Reg_on；
5th NPN manages the drain electrode and the 4th of the grid, third PMOS tube (P3) of collector connection third PMOS tube (P3) of (Q5)
The grid of PMOS tube (P4), emitter connect input terminal VDET, and base stage connects the collector and third of the 6th NPN pipe (Q6)
One end of resistance (R3)；
6th NPN manages one end and the third current source (I3) of base stage connection 3rd resistor (R3) of (Q6), emitter connection ginseng
Ground port (GND) is examined, collector connects the other end of 3rd resistor (R3) and the base stage of the 5th NPN pipe (Q5)；
The base stage of 7th NPN pipe (Q7) connects the one of the collector of itself, the base stage of the 8th NPN pipe (Q8) and the 4th resistance (R4)
End, emitter connect input terminal VDET；
The base stage that 8th NPN manages (Q8) connects the collector of the 7th NPN pipe (Q7), the base stage of the 7th NPN pipe (Q7) and the 4th electricity
The one end of (R4) is hindered, collector connects drain electrode and the output end Reg_on of the 4th PMOS tube (P4), emitter connection reference
Ground port (GND)；
One end of 3rd resistor (R3) connects the collector of the 6th NPN pipe (Q6) and the base stage of the 5th NPN pipe (Q5), 3rd resistor
(R3) the other end connects the base stage and third current source (I3) of the 6th NPN pipe (Q6)；
One end of 4th resistance (R4) connects the base stage and the 8th NPN of the collector of the 7th NPN pipe (Q7), the 7th NPN pipe (Q7)
The base stage of (Q8) is managed, the other end of the 4th resistance (R4) connects the 4th current source (I4)；
Third current source (I3) connects the one end of 3rd resistor (R3) and the base stage of the 6th NPN pipe (Q6)；
4th current source (I4) connects one end of the 4th resistance (R4).
5. a kind of synchronous rectifier converter according to claim 4, it is characterised in that：For upper sub-circuit, work as input terminal
When VDET voltage is greater than the third threshold value V3 of setting, output end Reg_off is high potential, that is, meets following relationship：
VDET+I1*R1>0
VDET>-I1*R1
Output end Reg_off is high potential.
Wherein, R1 refers to first resistor, and I1 refers to that the first current source, VDET refer to the sampled signal of input terminal input；- I1*R1 is defined
First resistor (R1) and second resistance (R2) for third threshold value V3, and in upper sub-circuit they the resistance of resistance values size such as are, first
Current source (I1) and the second current source (I2) such as are at the current source of same currents size；
For lower sub-circuit, when input terminal VDET voltage is less than the 4th threshold value V4 of setting, output end Reg_on is high potential,
Meet following relationship：
VDET+I4*R4<0
VDET<-I4*R4
Output end Reg_on is high potential；
Wherein, R4 refers to that the 4th resistance, I4 refer to that the 4th current source, VDET refer to the sampled signal of input terminal input；- I4*R4 is defined
3rd resistor (R3) and the 4th resistance (R4) for the 4th threshold value V4, and in lower sub-circuit such as are at the resistance of resistance values size, the third
Current source (I3) and the 4th current source (I4) such as are at the current source of same currents size.
6. a kind of synchronous rectifier converter according to claim 1, it is characterised in that：It is described can overheat protector output line
Damaging compensation circuit (205) includes the 5th PMOS tube (P5), the 6th PMOS tube (P6), the 7th PMOS tube (P7), the 8th PMOS tube
(P8), the 9th PMOS tube (P9), third NMOS tube (N3), the 4th NMOS tube (N4), the 5th NMOS tube (N5), the 6th NMOS tube
(N6), the 7th NMOS tube (N7), the 8th NMOS tube (N8), the 9th NMOS tube (N9), the 9th NPN manage (Q9), first voltage source
(V1), the 5th current source (I5), the 6th current source (I6), the 7th current source (I7) and the first logic inverter (M1)；
The source electrode of 5th PMOS tube (P5) is connected with supply port (VCC), and grid connects the drain electrode of itself, the 6th PMOS tube
(P6) drain electrode of grid, third NMOS tube (N3) and the drain electrode of the 5th NMOS tube (N5)；
The grid of 6th PMOS tube (P6) connects the grid of the 5th PMOS tube (P5), the drain electrode of the 5th PMOS tube (P5), third
The drain electrode of the drain electrode of NMOS tube (N3) and the 5th NMOS tube (N5), source electrode are connected with supply port (VCC), drain electrode connection the
The drain electrode of eight NMOS tubes (N8), the grid of the 4th NMOS tube (N4) and the first logic inverter (M1) input terminal；
The grid of 7th PMOS tube (P7) connects the base stage of the 9th NPN pipe (Q9), the collector of the 9th NPN pipe (Q9) and the 5th electricity
Stream source (I5), source electrode connect the 6th current source (I6), the drain electrode of drain electrode the 6th NMOS tube (N6) of connection, the 6th NMOS tube
(N6) grid, the grid of the 5th NMOS tube (N5) and the grid of third NMOS tube (N3)；
The grid of 8th PMOS tube (P8) connects first voltage source (V1), and source electrode connects the 6th current source (I6), and drain electrode connects
Connect drain electrode, the grid of the 7th NMOS tube (N7) and the grid of the 8th NMOS tube (N8) of the 7th NMOS tube (N7)；
The output end of the grid connection the first logic inverter (M1) of 9th PMOS tube (P9), receives overheat protector signal OTP, source
Pole connects the 7th current source (I7), the drain electrode and output compensation port (COMP) of drain electrode the 9th NMOS tube (N9) of connection；
The grid of third NMOS tube (N3) connects the grid of the 5th NMOS tube (N5), the grid of the 6th NMOS tube (N6), the 6th
The drain electrode of the drain electrode of NMOS tube (N6) and the 7th PMOS tube (P7), the grid of drain electrode the 5th PMOS tube (P5) of connection, the 5th
The drain electrode of PMOS tube (P5), the drain electrode of the grid of the 6th PMOS tube (P6) and the 5th NMOS tube (N5), source electrode and the 4th NMOS
The drain electrode for managing (N4) is connected；
The grid of 4th NMOS tube (N4) connects the drain electrode of the 6th PMOS tube (P6), the drain electrode and first of the 8th NMOS tube (N8) is patrolled
Collect the input terminal of NOT gate (M1), the source electrode of drain electrode connection third NMOS tube (N3), source electrode and reference ground mouth (GND) phase
Even；
The grid of 5th NMOS tube (N5) connects the grid of third NMOS tube (N3), the drain electrode of the 6th NMOS tube (N6), the 6th
The drain electrode of the grid of NMOS tube (N6) and the 7th PMOS tube (P7), the grid of drain electrode the 5th PMOS tube (P5) of connection, the 5th
The drain electrode of PMOS tube (P5), the drain electrode of the grid of the 6th PMOS tube (P6) and third NMOS tube (N3), source electrode and reference ground
Mouth (GND) is connected；
The grid of 6th NMOS tube (N6) connects the drain electrode of itself, the grid of the 5th NMOS tube (N5), third NMOS tube (N3)
The drain electrode of grid and the 7th PMOS tube (P7), source electrode are connected with reference ground mouth (GND)；
The grid of 7th NMOS tube (N7) connects the drain electrode of itself, the grid of the 8th NMOS tube (N8) and the 8th PMOS tube (P8)
Drain electrode, source electrode are connected with reference ground mouth (GND)；
The grid of 8th NMOS tube (N8) connects the drain electrode and the 8th of the grid, the 7th NMOS tube (N7) of the 7th NMOS tube (N7)
The drain electrode of PMOS tube (P8), the drain electrode of drain electrode the 6th PMOS tube (P6) of connection, the grid and first of the 4th NMOS tube (N4) are patrolled
The input terminal of NOT gate (M1) is collected, source electrode is connected with reference ground mouth (GND)；
The grid of 9th NMOS tube (N9) is connected with input terminal GATE, drain electrode connection output compensation port (COMP) and the 9th
The drain electrode of PMOS tube (P9), source electrode are connected with reference ground mouth (GND)；
The base stage of 9th NPN pipe (Q9) connects the grid of the collector of itself, the 5th current source (I5) and the 7th PMOS tube (P7),
Its emitter is connected with reference ground mouth (GND)；
First voltage source (V1) connects the grid of the 8th PMOS tube (P8)；
5th current source (I5) connects the collector and the 7th PMOS tube of the base stage of the 9th NPN pipe (Q9), the 9th NPN pipe (Q9)
(P7) grid；
6th current source (I6) connects the source electrode of the 7th PMOS tube (P7) and the source electrode of the 8th PMOS tube (P8)；
7th current source (I7) connects the source electrode of the 9th PMOS tube (P9)；
The input terminal of first logic inverter (M1) connects the drain electrode of the 6th PMOS tube (P6), the grid of the 4th NMOS tube (N4), the
The drain electrode of eight NMOS tubes (N8), output end connect the grid of the 9th PMOS tube (P9), transmit overheat protector signal OTP to the 9th
The grid of PMOS tube (P9).
7. a kind of synchronous rectifier converter according to claim 6, it is characterised in that：Input drive signal GATE is height
When, the conducting of the 9th NMOS tube (N9) has an electric current Icomp to flow into from compensation port (COMP), realizes output line loss using electric current
Compensation；
The grid of 7th PMOS tube (P7) connects the base stage and collector of the 9th NPN pipe (Q9), the grid of the 8th PMOS tube (P8)
It connects first voltage source (V1), it is negative temperature coefficient that the 9th NPN, which manages the base stage of (Q9) and the knot pressure drop VBE of transmitting interpolar, works as core
When the operating ambient temperature of piece is excessively high, at this time：
VBE<V1
Then overheat protector signal OTP is low；
Wherein, VBE refers to the base stage of the 9th NPN pipe (Q9) and the knot pressure drop of transmitting interpolar, and V1 refers to first voltage source；
When overheat protector signal OTP be it is low, the 9th PMOS tube (P9) conducting, an electric current Icomp from compensation port (COMP) outflow,
Overheat protector is realized using electric current.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110492724A (en) * | 2019-09-16 | 2019-11-22 | 安徽省东科半导体有限公司 | A kind of power tube drive circuit and driving method |
| CN110855131A (en) * | 2019-12-09 | 2020-02-28 | 成都芯源系统有限公司 | Drive circuit of synchronous rectifier |
| CN111865088A (en) * | 2020-07-09 | 2020-10-30 | 无锡芯朋微电子股份有限公司 | Control circuit for synchronous rectification |
| CN112886802A (en) * | 2021-01-15 | 2021-06-01 | 深圳市群芯科创电子有限公司 | Secondary side synchronous rectification circuit with thermal protection function and electronic equipment |
| CN116979946A (en) * | 2023-07-28 | 2023-10-31 | 北京中科格励微科技有限公司 | Control circuit of adjustable pull-up resistor |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010028570A1 (en) * | 2000-02-25 | 2001-10-11 | Mullett Charles E. | Converter output regulation via channel resistance modulation of synchronous rectifiers |
| CN101345480A (en) * | 2007-12-03 | 2009-01-14 | 崇贸科技股份有限公司 | Synchronization adjustment circuit of off-line power converter |
| CN103236795A (en) * | 2013-05-10 | 2013-08-07 | 矽力杰半导体技术(杭州)有限公司 | Synchronous rectification control circuit and method |
| CN106100379A (en) * | 2016-07-20 | 2016-11-09 | 无锡芯朋微电子股份有限公司 | Synchronous rectifying controller |
| CN107425732A (en) * | 2017-09-12 | 2017-12-01 | 广州金升阳科技有限公司 | A kind of synchronous rectifier opens control method and circuit |
| CN107508473A (en) * | 2017-07-13 | 2017-12-22 | 苏州博创集成电路设计有限公司 | Synchronous rectifier converter |
| TW201804285A (en) * | 2016-07-26 | 2018-02-01 | 廣東歐珀移動通信有限公司 | Adapter and charging control method |
-
2018
- 2018-08-14 CN CN201810921202.8A patent/CN108923660B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010028570A1 (en) * | 2000-02-25 | 2001-10-11 | Mullett Charles E. | Converter output regulation via channel resistance modulation of synchronous rectifiers |
| CN101345480A (en) * | 2007-12-03 | 2009-01-14 | 崇贸科技股份有限公司 | Synchronization adjustment circuit of off-line power converter |
| CN103236795A (en) * | 2013-05-10 | 2013-08-07 | 矽力杰半导体技术(杭州)有限公司 | Synchronous rectification control circuit and method |
| CN106100379A (en) * | 2016-07-20 | 2016-11-09 | 无锡芯朋微电子股份有限公司 | Synchronous rectifying controller |
| TW201804285A (en) * | 2016-07-26 | 2018-02-01 | 廣東歐珀移動通信有限公司 | Adapter and charging control method |
| CN107508473A (en) * | 2017-07-13 | 2017-12-22 | 苏州博创集成电路设计有限公司 | Synchronous rectifier converter |
| CN107425732A (en) * | 2017-09-12 | 2017-12-01 | 广州金升阳科技有限公司 | A kind of synchronous rectifier opens control method and circuit |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110492724A (en) * | 2019-09-16 | 2019-11-22 | 安徽省东科半导体有限公司 | A kind of power tube drive circuit and driving method |
| CN110492724B (en) * | 2019-09-16 | 2024-03-29 | 东科半导体(安徽)股份有限公司 | Power tube driving circuit and driving method |
| CN110855131A (en) * | 2019-12-09 | 2020-02-28 | 成都芯源系统有限公司 | Drive circuit of synchronous rectifier |
| CN110855131B (en) * | 2019-12-09 | 2021-10-15 | 成都芯源系统有限公司 | Drive circuit of synchronous rectifier |
| CN111865088A (en) * | 2020-07-09 | 2020-10-30 | 无锡芯朋微电子股份有限公司 | Control circuit for synchronous rectification |
| CN112886802A (en) * | 2021-01-15 | 2021-06-01 | 深圳市群芯科创电子有限公司 | Secondary side synchronous rectification circuit with thermal protection function and electronic equipment |
| CN116979946A (en) * | 2023-07-28 | 2023-10-31 | 北京中科格励微科技有限公司 | Control circuit of adjustable pull-up resistor |
| CN116979946B (en) * | 2023-07-28 | 2024-03-05 | 北京中科格励微科技有限公司 | Control circuit of adjustable pull-up resistor |
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| CN108923660B (en) | 2020-01-24 |
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