CN107508473A - Synchronous rectifier converter - Google Patents
Synchronous rectifier converter Download PDFInfo
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- CN107508473A CN107508473A CN201710570771.8A CN201710570771A CN107508473A CN 107508473 A CN107508473 A CN 107508473A CN 201710570771 A CN201710570771 A CN 201710570771A CN 107508473 A CN107508473 A CN 107508473A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
Abstract
The present invention relates to synchronous rectifier converter, including power circuit and control circuit, power circuit includes switch metal-oxide-semiconductor and sampling metal-oxide-semiconductor, and control circuit includes opening controller, shut-off controller and PWM control drive circuits；Control circuit output drive signal GATE is to power circuit, and the sampled signal VDET of receiving power circuit output, switch metal-oxide-semiconductor and sampling metal-oxide-semiconductor in power circuit are all integrated on same silicon chip, sampling metal-oxide-semiconductor can accurately sample the positive/negative voltage signal of switch metal-oxide-semiconductor source and drain interpolar, realize that what synchronous rectifier converter was switched on and off is precisely controlled.Switch metal-oxide-semiconductor provides high current leakage path for sampling metal-oxide-semiconductor, alleviates its resistance to pressure pressure.
Description
Technical field
The present invention relates to a kind of synchronous rectifier converter, belongs to switch power technology field.
Background technology
At present, inverse-excitation type switch power-supply system is due to circuit is simple, input and output voltage is isolated, cost is low, volume
The advantages that small and be widely used, but when output current is larger, output voltage is relatively low, traditional inverse-excitation type switch power-supply
Secondary commutation diode on-state loss and reverse recovery loss in system is big, less efficient.In order to reduce commutation diode
Loss, using the extremely low switch metal-oxide-semiconductor of on-state resistance, to substitute diode, as rectifier, this synchronous rectification can be very
The conversion efficiency of whole power-supply system is improved well.
Such as the circuit block diagram that Fig. 1 is existing synchronous rectifier converter 100, a high withstand voltage metal-oxide-semiconductor is used in control circuit
N2 is used for as sampling metal-oxide-semiconductor, sampling metal-oxide-semiconductor N2 detection switch metal-oxide-semiconductors N1 drain-source voltage so as to obtain low pressure sampled signal
Open comparator 101 and shut-off comparator 102 judges.Open comparator 101 and low pressure sampled signal is opened into threshold value with fixed
Vth_on, which compares, produces open signal SR_ON；Comparator 102 is turned off by low pressure sampled signal and fixed shut-off threshold value Vth_off
Compare and produce cut-off signals SR_OFF.Synchronous rectifier converter sets sample port VDET to export high pressure sampled signal to most short pass
Disconnected time circuit 103, for most short shut-off control.PWM control drive circuits 104 receive open signal SR_ON and cut-off signals
SR_OFF, produce drive signal GATE controlling switch metal-oxide-semiconductors N1 switch.
The judgement that synchronous rectifier converter is switched on and off needs the electricity being accurate between the hourglass source electrode of detection switch metal-oxide-semiconductor
Buckling.But high withstand voltage metal-oxide-semiconductor and control circuit are integrated on same silicon chip, problems can be brought：First, high withstand voltage
The structure such as metal-oxide-semiconductor and its protection ring can take larger area, be unfavorable for reducing control circuit entire area to improve integrated level；
Second, the structure that sampling metal-oxide-semiconductor separates with switching metal-oxide-semiconductor, it is difficult to ensure to sample metal-oxide-semiconductor to electricity between switch metal-oxide-semiconductor hourglass source electrode
The accurate detection of buckling, it can not then realize and synchronous rectifier converter is more accurately controlled；3rd, existing synchronous rectification
Converter is needed to set sample port (VDET) output high pressure sampled signal to be used for most short shut-off control so that synchronous rectification is changed
The application of device is complicated, then adds cost.
The content of the invention
The purpose of the present invention is to overcome the shortcomings of the prior art, there is provided a kind of with high integration, high reliability
Synchronous rectifier converter.
The purpose of the present invention is achieved through the following technical solutions：
Synchronous rectifier converter, including power circuit and control circuit, feature be：
The power circuit includes switch metal-oxide-semiconductor and sampling metal-oxide-semiconductor, and the control circuit includes opening controller, shut-off
Controller and PWM control drive circuits；
The drain electrode of the switch metal-oxide-semiconductor and sampling metal-oxide-semiconductor is connected with high pressure port；
The grid of the switch metal-oxide-semiconductor is connected with PWM control drive circuits, receives the drive signal GATE of its output, opens
The source electrode for closing metal-oxide-semiconductor is connected with reference ground port GND；
The grid of the sampling metal-oxide-semiconductor is connected with supply port VCC, samples source electrode and opening controller and the pass of metal-oxide-semiconductor
Disconnected controller is connected, and sampled signal VDET is exported to it；
The opening controller receives the sampled signal VDET of sampling metal-oxide-semiconductor output, and opening controller drives with PWM controls
Circuit is connected, and receives the modulated pwm signal PWM of PWM control drive circuit outputs, and opening controller is connected with shut-off controller,
Receive shut-off controller output adaptive open signal VDET_on, and export open enable signal MOS_ON_EN to turn off control
Device processed, output open signal SR_ON to PWM control drive circuits；
The shut-off controller receives the sampled signal VDET of sampling metal-oxide-semiconductor output, turns off controller and opening controller
It is connected, to its output adaptive open signal VDET_on, shut-off controller is connected with PWM control drive circuits, receives its output
Modulated pwm signal PWM, and export cut-off signals SR_OFF to PWM control drive circuit；
The PWM control drive circuits are connected with opening controller, shut-off controller, receive open signal SR_ON and pass
Break signal SR_OFF, output modulated pwm signal PWM to opening controller and shut-off controller, and with switching the grid of metal-oxide-semiconductor
It is connected, to its output drive signal GATE.
Further, above-mentioned synchronous rectifier converter, wherein, the switch metal-oxide-semiconductor is integrated in same with sampling metal-oxide-semiconductor
It is common substrate structure on silicon chip.
Further, above-mentioned synchronous rectifier converter, wherein, sampling metal-oxide-semiconductor detection switch metal-oxide-semiconductor source and drain interpolar is just
Pressure and negative pressure signal, and sampled signal VDET is exported to control circuit；Control circuit is opened by handling sampled signal VDET, generation
Signal SR_ON and cut-off signals SR_OFF are opened, control synchronous rectifier converter is switched on and off.
Further, above-mentioned synchronous rectifier converter, wherein, the opening controller includes the first electric capacity, the second electricity
Appearance, the 3rd NMOS tube, the 4th NMOS tube, the first logic gate inverter, the second gate d type flip flop, the 3rd gate and door,
One comparator, the second comparator, the 3rd comparator and the 4th comparator；
The A ends of the drain electrode of one end of first electric capacity and the 3rd NMOS tube, the first internal current source and the second comparator are connected；
The A ends of the drain electrode of one end of second electric capacity and the 4th NMOS tube, the second internal current source and the 4th comparator are connected；
The grid of 3rd NMOS tube and the output OUT terminal and the 3rd gate and input one end phase of door of first comparator
Connect, and connect and open enable signal SR_ON_EN ends；
The grid of 4th NMOS tube is connected with the output OUT terminal of the 3rd comparator；
The input connection modulated pwm signal PWM ends of first logic gate inverter, output end trigger with the second gate D
The clearing CLR ends of device are connected；
The D ends and set SET ends of second gate d type flip flop are connected to be connected with VCC ends, along triggering the 4th comparator of termination
Output OUT terminal, outputEnd is connected with the 3rd gate with input one end of door, exportsEnd exports the most short turn-off time
Signal Toffmin is to the 3rd gate and input one end of door；
3rd gate and the input and the output OUT terminal of first comparator and the grid phase of the 3rd NMOS tube of door
Even, receive and open enable signal SR_ON_EN, the output of its another input and the second gate d type flip flopEnd is connected, and connects
Most short turn-off time signal Toffmin is received, it exports termination open signal SR_ON ends；
The A ends of first comparator connect adaptive open signal VDET_on ends, and its B end connection reference ground, it exports OUT
Hold and be connected with the grid of the 3rd NMOS tube, the 3rd gate with an input of door, and connect and open enable signal SR_ON_EN ends；
The A ends of second comparator are connected with drain electrode, the first electric capacity and the first internal current source of the 3rd NMOS tube, its B end
Internal reference voltage Vref ends are connected, it exports OUT terminal and is connected with the Ctrl ends of the 4th comparator, the most short turn-off time letter of output
Number two Toffmin2 are to the Ctrl ends of the 4th comparator；
The A ends connection sampled signal VDET ends of 3rd comparator, its B end connection reference ground, it exports OUT terminal and the 4th
The grid of NMOS tube is connected；
The A ends of 4th comparator are connected with one end of the second electric capacity, the drain electrode of the 4th NMOS tube and the second internal current source,
Its B end connection internal reference voltage Vref ends, its Ctrl end are connected with the output OUT terminal of the second comparator, receive most short shut-off
The Toffmin2 of time signal two, its export OUT terminal connect the second gate d type flip flop along triggering end.
Further, above-mentioned synchronous rectifier converter, wherein, first comparator is by adaptive open signal VDET_on
Compared with ground reference, enable signal SR_ON_EN is opened when adaptive open signal VDET_on is less than zero as height；3rd
Comparator, the 4th comparator, the second internal current source Source2, the 4th NMOS tube, the second electric capacity and internal reference voltage are used for
Judge that sampled signal VDET is more than the duration of null part, when the duration reaching setting required time, the second logic
Door d type flip flop is triggered along triggering end, produces most short turn-off time signal Toffmin, and modulated pwm signal PWM is used for most short
Turn-off time signal Toffmin clearing；The duration not up to setting for being more than null part as sampled signal VDET is taken
Between when, first comparator, the second comparator, the first internal current source Source1, the 3rd NMOS tube, the first electric capacity be used for judge
Enable signal SR_ON_EN is opened as high effective duration, when the duration reaching setting required time, is produced most
The short Toffmin2 of turn-off time signal two now produces most short turn-off time signal Toffmin to the Ctrl ends of the 4th comparator；
When it is high effective simultaneously to open enable signal SR_ON_EN and most short turn-off time signal Toffmin, opening controller output
Open signal SR_ON.
Further, above-mentioned synchronous rectifier converter, wherein, the shut-off controller is opened including first switch, second
Pass, the 3rd electric capacity, first resistor, second resistance, the 4th logic gate inverter, the 5th logic gate inverter, the 6th gate are anti-
Phase device, the 7th gate NAND gate, the 8th gate nor gate, the 9th logic gate inverter, the tenth gate and door, first prolong
Slow unit, the second delay cell and the 5th comparator；
One end of first switch is connected with the 3rd internal current source, the other end and second switch, the 3rd electric capacity and the 5th
The voltage control anode of internal current source is connected, and its control terminal is connected with the tenth gate with the output end of door, receives pull-up letter
Number Raise_up；
One end of second switch is connected with the 4th internal current source, the other end and first switch, the 3rd electric capacity and the 5th
The voltage control anode of internal current source is connected, and its control terminal is connected with the output end of the 8th gate nor gate, receives drop-down
Signal Pull_down；
3rd electric capacity is connected with the voltage control anode of first switch, second switch and the 5th internal current source；
One end of first resistor is connected with the 5th internal current source, and is connected to and adapts to open signal VDET_on ends, and its is another
End is connected with the A ends of second resistance, the 5th comparator, output adaptive cut-off signals VDET_off to the A ends of the 5th comparator；
One end of second resistance is connected with sampled signal VDET ends, the other end and first resistor, the A ends phase of the 5th comparator
Even, output adaptive cut-off signals VDET_off to the A ends of the 5th comparator；
The input termination of 4th logic gate inverter opens enable signal SR_ON_EN ends, output the 8th gate of termination or
One end of NOT gate；
The input termination modulated pwm signal PWM ends of 5th logic gate inverter, output the 6th logic gate inverter of termination
Input and the 7th gate NAND gate input；
The output end and the 7th gate NAND gate of input the 5th logic gate inverter of termination of 6th logic gate inverter
Input, its export termination the first delay cell input；
The input of 7th gate NAND gate connects the output end of the first delay cell, the 5th logic gate inverter respectively
The input of output end and the 6th logic gate inverter, it exports one end of the 8th gate nor gate of termination；
The input of 8th gate nor gate connect respectively the 4th logic gate inverter output end and the 7th gate with
The output end of NOT gate, it exports the control terminal of termination second switch, output pulldown signal Pull_down to second switch control
End；
The input of 9th logic gate inverter and modulated pwm signal PWM ends, the input of the 5th logic gate inverter
It is connected with the tenth gate with the input of door, its output end is connected with the input of the second delay cell；
The input of tenth gate and door connects output end and the modulated pwm signal PWM ends of the second delay cell respectively,
It exports the control terminal of termination first switch, output pull-up signal Raise_up to first switch control terminal；
The A ends of 5th comparator are connected with first resistor and second resistance, receive adaptive cut-off signals VDET_off, its
B ends are connected with reference ground, and its output end is connected with cut-off signals SR_OFF ends.
Further, above-mentioned synchronous rectifier converter, wherein, the 5th internal current source is VCCS, is led to
The magnitude of voltage at its voltage control both ends is overregulated, to adjust electric current I, meets following relation：
VDET_on=I* (R1+R2)+VDET
VDET_off=I*R2+VDET
Wherein, R1 refers to first resistor, and R2 refers to second resistance, and VDET refers to sampled signal, and VDET_on, which refers to adaptive open, to be believed
Number, VDET_off refers to adaptive cut-off signals.
Further, above-mentioned synchronous rectifier converter, wherein, pass through the 3rd internal current source and the 4th internal current
Source, first switch, second switch and the 3rd electric capacity realize control voltage Vctrl adjustment, and control voltage Vctrl refers in the 5th
The magnitude of voltage at portion current source voltage control both ends；
When it is high to pull up signal Raise_up, the 3rd internal current source charges to the 3rd electric capacity, control voltage Vctrl liters
Height, electric current I become big；When pulldown signal Pull_down is high, the 4th internal current source is discharged the 3rd electric capacity, control voltage
Vctrl is reduced, and electric current I diminishes.
Further, above-mentioned synchronous rectifier converter, wherein, pull-up signal Raise_up generation mechanism is：Pass through
9th logic gate inverter, the tenth gate and door and the second delay cell produce to be triggered by modulated pwm signal PWM rising edges
Fixed pulse width time Delay2, set time Delay2 is the high effective time as pull-up signal Raise_up.
Further, above-mentioned synchronous rectifier converter, wherein, pulldown signal Pull_down generation mechanism is：Pass through
4th logic gate inverter, the 5th logic gate inverter, the 6th logic gate inverter, the 7th gate NAND gate, the 8th logic
Door nor gate and the first delay cell are realized to being opened in modulated pwm signal PWM trailing edges triggering set time Delay1 pulsewidth
Enable signal SR_ON_EN is the detection of high effective time；Enable signal SR_ON_EN will be opened in set time Delay1 pulsewidth
Effective duration, it is the high effective time as pulldown signal Pull_down；Opened between when clamped in Delay1 pulsewidths
When enable signal SR_ON_EN is always low, then pulldown signal Pull_down is low.
The present invention has the advantages of notable and beneficial effect compared with prior art, embodies in the following areas：
1. the power circuit of synchronous rectifier converter of the present invention realizes switch metal-oxide-semiconductor and sampling metal-oxide-semiconductor in same silicon chip
Integrated, switch metal-oxide-semiconductor and the structure that sampling metal-oxide-semiconductor is common substrate, control circuit are free of high withstand voltage device；
2. switch metal-oxide-semiconductor can provide high current leakage path, and the switch with high withstand voltage ability for sampling metal-oxide-semiconductor
Metal-oxide-semiconductor also alleviates the resistance to pressure pressure of sampling metal-oxide-semiconductor；
3. sampling metal-oxide-semiconductor can more precisely detect the malleation and negative pressure signal of switch metal-oxide-semiconductor source and drain interpolar, detection
The accurate malleation signal arrived, without setting sample port VDET to can be realized as accurately most short shut-off control；The essence detected
True negative pressure signal, it is possible to achieve adaptively be switched on and off controlling, then accomplish accurately to open synchronous rectifier converter and
Shut-off control；
4. control circuit by handle sampling metal-oxide-semiconductor export accurate sampled signal, can realize simplify and accurately most
Short turn-off time control, can then realize and accurately be switched on and off controlling, improve the reliable operation of synchronous rectifier converter
Property, applied to switch power supply system.
Brief description of the drawings
Fig. 1：The circuit block diagram of background technology synchronous rectifier converter；
Fig. 2：The circuit block diagram of synchronous rectifier converter of the present invention；
Fig. 3：The structural representation of the opening controller of the present invention；
Fig. 4：The working waveform figure of the opening controller of the present invention；
Fig. 5：The structural representation of the shut-off controller of the present invention；
Fig. 6：The working waveform figure of the shut-off controller of the present invention；
Fig. 7：Another working waveform figure of the shut-off controller of the present invention；
Fig. 8：The working waveform figure of synchronous rectifier converter of the present invention.
Embodiment
In order to which technical characteristic, purpose and the effect of the present invention is more clearly understood, now compares accompanying drawing and describe in detail
Specific embodiment.
As shown in Fig. 2 synchronous rectifier converter 200, including power circuit and control circuit,
Power circuit includes switch metal-oxide-semiconductor N1 and sampling metal-oxide-semiconductor N2, and the control circuit includes opening controller 201, closed
Disconnected controller 202 and PWM control drive circuit 203；
Switch metal-oxide-semiconductor N1 and sampling metal-oxide-semiconductor N2 drain electrode are connected with high pressure port SW；
Switch metal-oxide-semiconductor N1 grid is connected with PWM control drive circuits 203, receives the drive signal GATE of its output, opens
The source electrode for closing metal-oxide-semiconductor N1 is connected with reference ground port GND；
Sampling metal-oxide-semiconductor N2 grid is connected with supply port VCC, sampling metal-oxide-semiconductor N2 source electrode and opening controller 201 and
Turn off controller 202 to be connected, sampled signal VDET is exported to it；
Opening controller 201 receives the sampled signal VDET of sampling metal-oxide-semiconductor N2 outputs, and opening controller 201 and PWM is controlled
Drive circuit 203 is connected, and receives the modulated pwm signal PWM that PWM control drive circuits 203 export, opening controller 201 is with closing
Disconnected controller 202 is connected, and receives the adaptive open signal VDET_on that shut-off controller 202 exports, and exports the enabled letter of unlatching
Number MOS_ON_EN is to turning off controller 202, output open signal SR_ON to PWM control drive circuits 203；
The sampled signal VDET that controller 202 receives the N2 outputs of sampling metal-oxide-semiconductor is turned off, shut-off controller 202 is controlled with opening
Device 201 processed is connected, to its output adaptive open signal VDET_on, the shut-off controller 202 and PWM control phases of drive circuit 203
Even, the modulated pwm signal PWM of its output is received, and exports cut-off signals SR_OFF to PWM control drive circuits 203；
PWM controls drive circuit 203 to be connected with opening controller 201, shut-off controller 202, receives open signal SR_ON
With cut-off signals SR_OFF, output modulated pwm signal PWM to opening controller 201 and shut-off controller 202, and with switch
Metal-oxide-semiconductor N1 grid is connected, to its output drive signal GATE.
Switch metal-oxide-semiconductor N1 is integrated on same silicon chip with sampling metal-oxide-semiconductor N2, is common substrate structure.
The malleation and negative pressure signal of metal-oxide-semiconductor N2 detection switch metal-oxide-semiconductor N1 source and drain interpolars are sampled, and exports sampled signal VDET
To control circuit；Control circuit produces open signal SR_ON and cut-off signals SR_OFF, control by handling sampled signal VDET
Synchronous rectifier converter processed is switched on and off.
As shown in figure 3, opening controller 201 includes the first electric capacity C1, the second electric capacity C2, the 3rd NMOS tube N3, the 4th
NMOS tube N4, the first logic gate inverter I1, the second gate d type flip flop I2, the 3rd gate and door I3, first comparator
A1, the second comparator A2, the 3rd comparator A3 and the 4th comparator A4；
First electric capacity C1 one end is compared with the 3rd NMOS tube N3 drain electrode, the first internal current source Source1 and second
Device A2 A ends are connected；
Second electric capacity C2 one end is compared with the 4th NMOS tube N4 drain electrode, the second internal current source Source2 and the 4th
Device A4 A ends are connected；
3rd NMOS tube N3 grid and first comparator A1 output OUT terminal and the 3rd gate and door I3 input one
End is connected, and connects and open enable signal SR_ON_EN ends；
4th NMOS tube N4 grid is connected with the 3rd comparator A3 output OUT terminal；
First logic gate inverter I1 input connection modulated pwm signal PWM ends, output end are touched with the second gate D
Hair device I2 clearing CLR ends are connected；
Second gate d type flip flop I2 D ends and set SET ends is connected to be connected with VCC ends, is compared along triggering termination the 4th
Device A4 output OUT terminal, outputEnd is connected with the 3rd gate with door I3 input one end, exportsEnd exports most short pass
Disconnected time signal Toffmin is to the 3rd gate and door I3 input one end；
3rd gate and door I3 an input and first comparator A1 output OUT terminal and the 3rd NMOS tube N3 grid
Extremely it is connected, receives and open enable signal SR_ON_EN, its another input and the second gate d type flip flop I2 outputHold phase
Even, most short turn-off time signal Toffmin is received, it exports termination open signal SR_ON ends；
First comparator A1 A ends connect adaptive open signal VDET_on ends, and its B end connection reference ground, it is exported
OUT terminal and the 3rd NMOS tube N3 grid, the 3rd gate are connected with a door I3 input, and connect and open enable signal SR_
ON_EN ends；
Second comparator A2 A ends and the 3rd NMOS tube N3 drain electrode, the first electric capacity C1 and the first internal current source
Source1 is connected, and its B end connection internal reference voltage Vref ends, it exports the Ctrl ends phase of OUT terminal and the 4th comparator A4
Even, the most short Toffmin2 of turn-off time signal two is exported to the 4th comparator A4 Ctrl ends；
3rd comparator A3 A ends connection sampled signal VDET ends, its B end connection reference ground, it exports OUT terminal and second
NMOS tube N4 grid is connected；
4th comparator A4 A ends and the second electric capacity C2 one end, the 4th NMOS tube N4 drain electrode and the second internal current
Source Source2 is connected, its B end connection internal reference voltage Vref ends, its Ctrl end and the second comparator A2 output OUT terminal phase
Even, the most short Toffmin2 of turn-off time signal two is received, it exports the edge triggering that OUT terminal connects the second gate d type flip flop I2
End.
The operation principle of opening controller 201 is：First comparator A1 is by adaptive open signal VDET_on and reference ground
Current potential compares, and enable signal SR_ON_EN is opened when adaptive open signal VDET_on is less than zero as height；3rd comparator
A3, the 4th comparator A4, the second internal current source Source2, the 4th NMOS tube N4, the second electric capacity C2 and internal reference voltage are used
In judging duration of the sampled signal VDET more than null part, when the duration reaching setting required time, second patrols
Being triggered along triggering end for door d type flip flop I2 is collected, produces most short turn-off time signal Toffmin, modulated pwm signal PWM is used for
Most short turn-off time signal Toffmin clearing；The duration for being more than null part as sampled signal VDET not up to sets institute
When taking time, first comparator A1, the second comparator A2, the first internal current source Source1, the 3rd NMOS tube N3, the second electricity
Hold C2 and be used to judge to open enable signal SR_ON_EN for high effective duration, taken when the duration reaches setting
Between when, the most short Toffmin2 of turn-off time signal two is produced to the 4th comparator A4 Ctrl ends, when now producing most short shut-off
Between signal Toffmin；When it is high effective simultaneously to open enable signal SR_ON_EN and most short turn-off time signal Toffmin,
Opening controller output open signal SR_ON.
As shown in figure 4, the working waveform figure of opening controller 201 of the present invention, the sampled signal of sampling metal-oxide-semiconductor N2 outputs
The characteristics of VDET is：Part of the waveform more than VCC is chopped between switch metal-oxide-semiconductor N1 hourglass source electrode, the part less than VCC, bag
Negative pressure signal is included to be retained.Complete waveform should be including the dotted portion more than VCC between switching metal-oxide-semiconductor N1 hourglass source electrode.
By handling sampled signal VDET, it is possible to achieve simplify and the accurate most short turn-off time controls, then can
Realize and accurately open control.Specifically, such as Fig. 4, at the t1 moment, made by the part for being more than zero to sampled signal VDET waveforms
Time timing, when meeting setting required time, most short cut-off signals Toffmin is height；At the t2 moment, letter is opened when adaptive
When number VDET_on is less than zero, enable signal SR_ON_EN is opened as height, as most short cut-off signals Toffmin and opens enabled letter
Number SR_ON_EN is simultaneously height, then open signal SR_ON is height；At the t3 moment, modulated pwm signal PWM will most short cut-off signals
Toffmin is reset；At the t4 moment, by making time timing to part of the sampled signal VDET waveforms more than zero, when between institute's timing
When not meeting setting required time, open signal SR_ON is now judged for high duration, when meeting the requirements the duration
Between when, the most short Toffmin2 of turn-off time signal two is height, and most short cut-off signals Toffmin also uprises, now open signal SR_
ON is also height.
As shown in figure 5, shut-off controller 202 includes first switch W1, second switch W2, the 3rd electric capacity C3, first resistor
R1, second resistance R2, the 4th logic gate inverter I4, the 5th logic gate inverter I5, the 6th logic gate inverter I6, the 7th patrol
Collect door NAND gate I7, the 8th gate nor gate I8, the 9th logic gate inverter I9, the tenth gate and door I10, the first delay
Cells D elay1, the second delay cell Delay2 and the 5th comparator A5；
First switch W1 one end is connected with the 3rd internal current source Source3, the other end and second switch W2, the 3rd electricity
The voltage control anode for holding C3 and the 5th internal current source Source5 is connected, and its control terminal is with the tenth gate with door I10's
Output end is connected, and receives pull-up signal Raise_up；
Second switch W2 one end is connected with the 4th internal current source Source4, the other end and first switch W1, the 3rd electricity
The voltage control anode for holding C3 and the 5th internal current source Source5 is connected, its control terminal and the 8th gate nor gate I8
Output end be connected, receive pulldown signal Pull_down；
3rd electric capacity C3 and first switch W1, second switch W2 and the 5th internal current source Source5 voltage control just
End is connected；
First resistor R1 one end is connected with the 5th internal current source Source5, and is connected to and adapts to open signal VDET_on
End, its other end is connected with second resistance R2, the 5th comparator A5 A ends, output adaptive cut-off signals VDET_off to the
Five comparator A5 A ends；
Second resistance R2 one end is connected with sampled signal VDET ends, the other end and first resistor R1, the 5th comparator A5
A ends be connected, output adaptive cut-off signals VDET_off to the 5th comparator A5 A ends；
4th logic gate inverter I4 input termination opens enable signal SR_ON_EN ends, output the 8th gate of termination
Nor gate I8 one end；
5th logic gate inverter I5 input termination modulated pwm signal PWM ends, output the 6th gate of termination are anti-phase
The input of device I6 input and the 7th gate NAND gate I7；
6th logic gate inverter I6 input termination the 5th logic gate inverter I5 output end and the 7th gate with
NOT gate I7 input, it exports the first delay cell Delay1 of termination input；
7th gate NAND gate I7 input connects the first delay cell Delay1 output end, the 5th gate respectively
The input of phase inverter I5 output end and the 6th logic gate inverter I6, it exports the one of the 8th gate nor gate I8 of termination
End；
8th gate nor gate I8 input connects the 4th logic gate inverter I4 output end and the 7th logic respectively
Door NAND gate I7 output end, it exports termination second switch W2 control terminal, and output pulldown signal Pull_down to second is opened
Close W2 control terminal；
9th logic gate inverter I9 input and modulated pwm signal PWM ends, the 5th logic gate inverter I5 it is defeated
Enter end and the tenth gate is connected with door I10 input, its output end is connected with the second delay cell Delay2 input；
Tenth gate and door I10 input connect the second delay cell Delay2 output end and modulation pulsewidth letter respectively
Number PWM ends, it exports termination first switch W1 control terminal, output pull-up signal Raise_up to first switch W1 control
End；
5th comparator A5 A ends are connected with first resistor R1 and second resistance R2, receive adaptive cut-off signals VDET_
Off, its B end are connected with reference ground, and its output end is connected with cut-off signals SR_OFF ends.
Turn off the operation principle of controller 202：Synchronous rectifier converter is opened in each work period, synchronization from main regulation
With shut-off threshold value, the 5th internal current source Source5 is VCCS, and the voltage at both ends is controlled by adjusting its voltage
Value, to adjust electric current I, meets following relation：
VDET_on=I* (R1+R2)+VDET
VDET_off=I*R2+VDET
Wherein, R1 refers to first resistor, and R2 refers to second resistance, and VDET refers to sampled signal, and VDET_on, which refers to adaptive open, to be believed
Number, VDET_off refers to adaptive cut-off signals.
Pass through the 3rd internal current source Source3 and the 4th internal current source Source4, first switch W1, second switch
W2 and the first electric capacity C1 realizes control voltage Vctrl adjustment, and control voltage Vctrl refers to the 5th internal current source Source5
Voltage controls the magnitude of voltage at both ends；
When it is high to pull up signal Raise_up, the 3rd internal current source Source3 charges to the 3rd electric capacity C3, control electricity
Vctrl rises are pressed, electric current I becomes big；When pulldown signal Pull_down is high, the 4th internal current source Source4 is to the 3rd electricity
Hold C3 electric discharges, control voltage Vctrl is reduced, and electric current I diminishes.
Pull-up signal Raise_up generation mechanism is：Pass through the 9th logic gate inverter I9, the tenth gate and door I10
The fixed pulse width time Delay2 triggered by modulated pwm signal PWM rising edges is produced with the second delay cell Delay2, it is fixed
Time Delay2 is the high effective time as pull-up signal Raise_up.
Pulldown signal Pull_down generation mechanism is：Pass through the 4th logic gate inverter I4, the 5th logic gate inverter
I5, the 6th logic gate inverter I6, the 7th gate NAND gate I7, the 8th gate nor gate I8 and the first delay cell
Delay1 is realized to opening enable signal SR_ON_EN in modulated pwm signal PWM trailing edges triggering set time Delay1 pulsewidth
For the detection of high effective time；The effective durations of enable signal SR_ON_EN will be opened in set time Delay1 pulsewidth,
It it is the high effective time as pulldown signal Pull_down；Enable signal SR_ON_ is opened between when clamped in Delay1 pulsewidths
When EN is always low, then pulldown signal Pull_down is low.
As shown in fig. 6, the work wave of present invention shut-off controller 202.By handling modulated pwm signal PWM and unlatching
Enable signal SR_ON_EN, pull-up signal Raise_up and pulldown signal Pull_down that regulation is switched on and off threshold value are produced,
Realization adaptively is switched on and off controlling, and then synchronous rectifier converter is accurately switched on and off to control.
Specifically, at the t1 moment, fixed pulse width time Delay2 is produced by modulated pwm signal PWM rising edge, thus
The pull-up signal Raise_up of set time Delay2 is produced, now electric current I becomes big；At the t2 moment, by modulated pwm signal PWM
Trailing edge produce fixed pulse width time Delay1；At the t3 moment, detection unlatching enable signal in set time Delay1 pulsewidth
SR_ON_EN is high effective duration, thus produces the pulldown signal Pull_down of corresponding effective time, now electric current I
Diminish；Distinguishingly, at the t4 moment, fixed pulse width time Delay1, it is not detected by and opens enable signal SR_ON_EN to be high effectively,
Then pulldown signal Pull_down is low that now electric current I is kept constant.
As shown in fig. 7, another work wave of present invention shut-off controller 202.In sampled signal VDET, signal is being pulled up
Raise_up, pulldown signal Pull_down regulation under, change electric current I, produce adaptive open signal VDET_on and adaptive
Answer cut-off signals VDET_off.At the t1 moment, when adaptive cut-off signals VDET_off is more than zero, cut-off signals SR_OFF is
It is high.
As shown in figure 8, the working waveform figure of synchronous rectifier converter 200 of the present invention, at the t1 moment, open signal SR_ON
For height, change drive signal GATE as height, then driving switch metal-oxide-semiconductor N1 is turned on；At the t2 moment, when cut-off signals SR_OFF is
Height, change drive signal GATE to be low, then driving switch metal-oxide-semiconductor N1 is closed.
In summary, the power circuit of synchronous rectifier converter of the present invention realizes switch metal-oxide-semiconductor and sampling metal-oxide-semiconductor same
Silicon chip integrates, and control circuit is free of high withstand voltage device.Compared to the circuit structure of existing synchronous rectifier converter, MOS is switched
Pipe can provide high current leakage path for sampling metal-oxide-semiconductor, and the switch metal-oxide-semiconductor with high withstand voltage ability also alleviates sampling
The resistance to pressure pressure of metal-oxide-semiconductor.Meanwhile sampling metal-oxide-semiconductor can be accurately detected the malleation and negative pressure letter of switch metal-oxide-semiconductor source and drain interpolar
Number, the accurate malleation signal detected, without setting sample port VDET to can be realized as accurately most short shut-off control；Detection
The precise negative pressure signal arrived, it is possible to achieve adaptively be switched on and off controlling, then accomplish to synchronous rectifier converter accurately
It is switched on and off controlling.
It should be noted that：The preferred embodiment of the present invention is the foregoing is only, is not limited to the power of the present invention
Sharp scope；Simultaneously more than description, should can understand and implement for the special personage of correlative technology field, thus it is other without departing from
The equivalent change or modification completed under disclosed spirit, should be included in claim.
Claims (10)
1. synchronous rectifier converter, including power circuit and control circuit, it is characterised in that：
The power circuit includes switch metal-oxide-semiconductor (N1) and sampling metal-oxide-semiconductor (N2), and the control circuit includes opening controller
(201) controller (202) and PWM control drive circuits (203), are turned off；
The drain electrode of the switch metal-oxide-semiconductor (N1) and sampling metal-oxide-semiconductor (N2) is connected with high pressure port (SW)；
The grid of the switch metal-oxide-semiconductor (N1) is connected with PWM control drive circuits (203), receives the drive signal of its output
(GATE) source electrode for, switching metal-oxide-semiconductor (N1) is connected with reference ground port (GND)；
The grid of the sampling metal-oxide-semiconductor (N2) is connected with supply port (VCC), and the source electrode of sampling metal-oxide-semiconductor (N2) controls with opening
Device (201) is connected with shut-off controller (202), and sampled signal (VDET) is exported to it；
The opening controller (201) receives the sampled signal (VDET) of sampling metal-oxide-semiconductor (N2) output, opening controller (201)
It is connected with PWM control drive circuits (203), receives the modulated pwm signal (PWM) of PWM control drive circuits (203) output, open
Open controller (201) with shut-off controller (202) to be connected, receive the adaptive open signal of shut-off controller (202) output
(VDET_on), and unlatching enable signal (MOS_ON_EN) is exported to controller (202) is turned off, export open signal (SR_ON)
To PWM control drive circuits (203)；
The shut-off controller (202) receives the sampled signal (VDET) of sampling metal-oxide-semiconductor (N2) output, shut-off controller (202)
It is connected with opening controller (201), to its output adaptive open signal (VDET_on), shut-off controller (202) is controlled with PWM
Drive circuit (203) processed is connected, and receives the modulated pwm signal (PWM) of its output, and exports cut-off signals (SR_OFF) to PWM
Control drive circuit (203)；
The PWM control drive circuits (203) are connected with opening controller (201), shut-off controller (202), receive and open letter
Number (SR_ON) and cut-off signals (SR_OFF), output modulated pwm signal (PWM) to opening controller (201) and shut-off control
Device (202), and be connected with the grid of switch metal-oxide-semiconductor (N1), to its output drive signal (GATE).
2. synchronous rectifier converter according to claim 1, it is characterised in that：The switch metal-oxide-semiconductor (N1) and sampling MOS
Pipe (N2) is integrated on same silicon chip, is common substrate structure.
3. synchronous rectifier converter according to claim 1, it is characterised in that：Sample metal-oxide-semiconductor (N2) detection switch metal-oxide-semiconductor
(N1) malleation and negative pressure signal of source and drain interpolar, and sampled signal (VDET) is exported to control circuit；Control circuit passes through processing
Sampled signal (VDET), produces open signal (SR_ON) and cut-off signals (SR_OFF), and control synchronous rectifier converter is opened
Open and turn off.
4. synchronous rectifier converter according to claim 1, it is characterised in that：The opening controller (201) includes the
One electric capacity (C1), the second electric capacity (C2), the 3rd NMOS tube (N3), the 4th NMOS tube (N4), the first logic gate inverter (I1),
Two gate d type flip flops (I2), the 3rd gate are compared with door (I3), first comparator (A1), the second comparator (A2), the 3rd
Device (A3) and the 4th comparator (A4)；
Drain electrode, the first internal current source (Source1) and the second ratio of one end of first electric capacity (C1) and the 3rd NMOS tube (N3)
A ends compared with device (A2) are connected；
Drain electrode, the second internal current source (Source2) and the 4th ratio of one end of second electric capacity (C2) and the 4th NMOS tube (N4)
A ends compared with device (A4) are connected；
The grid of 3rd NMOS tube (N3) and the output OUT terminal of first comparator (A1) and the 3rd gate and the input of door (I3)
One end is connected, and connects and open enable signal SR_ON_EN ends；
The grid of 4th NMOS tube (N4) is connected with the output OUT terminal of the 3rd comparator (A3)；
The input connection modulated pwm signal PWM ends of first logic gate inverter (I1), output end trigger with the second gate D
The clearing CLR ends of device (I2) are connected；
The D ends and set SET ends of second gate d type flip flop (I2) are connected to be connected with VCC ends, along triggering the 4th comparator of termination
(A4) output OUT terminal, outputEnd is connected with the 3rd gate with input one end of door (I3), exportsEnd output is most short
Turn-off time signal Toffmin is to input one end of the 3rd gate and door (I3)；
One input of the 3rd gate and door (I3) and the output OUT terminal of first comparator (A1) and the 3rd NMOS tube (N3)
Grid is connected, and receives and opens enable signal SR_ON_EN, the output of its another input and the second gate d type flip flop (I2)
End is connected, and receives most short turn-off time signal Toffmin, and it exports termination open signal SR_ON ends；
The A ends of first comparator (A1) connect adaptive open signal VDET_on ends, and its B end connection reference ground, it exports OUT
Hold and be connected with the grid of the 3rd NMOS tube (N3), the 3rd gate with an input of door (I3), and connect and open enable signal SR_
ON_EN ends；
The A ends of second comparator (A2) and drain electrode, the first electric capacity (C1) and the first internal current source of the 3rd NMOS tube (N3)
(Source1) it is connected, its B end connection internal reference voltage Vref ends, it exports the Ctrl ends of OUT terminal and the 4th comparator (A4)
It is connected, exports the most short Toffmin2 of turn-off time signal two to the Ctrl ends of the 4th comparator (A4)；
The A ends connection sampled signal VDET ends of 3rd comparator (A3), its B end connection reference ground, it exports OUT terminal and the 4th
The grid of NMOS tube (N4) is connected；
The A ends of 4th comparator (A4) and one end of the second electric capacity (C2), the drain electrode of the 4th NMOS tube (N4) and the second inside electricity
Stream source (Source2) is connected, its B end connection internal reference voltage Vref ends, its Ctrl end and the output of the second comparator (A2)
OUT terminal is connected, and receives the most short Toffmin2 of turn-off time signal two, and it exports OUT terminal and connects the second gate d type flip flop (I2)
Along triggering end.
5. synchronous rectifier converter according to claim 4, it is characterised in that：First comparator (A1) will be opened adaptively
Signal VDET_on opens enable signal SR_ON_ compared with ground reference when adaptive open signal VDET_on is less than zero
EN is height；3rd comparator (A3), the 4th comparator (A4), the second internal current source (Source2), the 4th NMOS tube (N4),
Second electric capacity (C2) and internal reference voltage are used for the duration for judging that sampled signal VDET is more than null part, when this continues
Between when reaching the time required to setting, second gate d type flip flop (I2's) is triggered along triggering end, produces most short turn-off time letter
Number Toffmin, modulated pwm signal PWM are used for most short turn-off time signal Toffmin clearing；When sampled signal VDET is more than
When the duration of null part not up to sets required time, first comparator (A1), the second comparator (A2), the first inside electricity
Stream source (Source1), the 3rd NMOS tube (N3), the second electric capacity (C2) are used to judge to open enable signal SR_ON_EN to be high effectively
Duration, when the time required to the duration reaching setting, produce the most short Toffmin2 of turn-off time signal two to the
The Ctrl ends of four comparators (A4), now produce most short turn-off time signal Toffmin；When open enable signal SR_ON_EN and
When most short turn-off time signal Toffmin is high effective simultaneously, opening controller output open signal SR_ON.
6. synchronous rectifier converter according to claim 1, it is characterised in that：The shut-off controller (202) includes the
One switch (W1), second switch (W2), the 3rd electric capacity (C3), first resistor (R1), second resistance (R2), the 4th gate are anti-phase
Device (I4), the 5th logic gate inverter (I5), the 6th logic gate inverter (I6), the 7th gate NAND gate (I7), the 8th patrol
Volume door nor gate (I8), the 9th logic gate inverter (I9), the tenth gate and door (I10), the first delay cell (Delay1),
Second delay cell (Delay2) and the 5th comparator (A5)；
One end of first switch (W1) is connected with the 3rd internal current source (Source3), the other end and second switch (W2), the 3rd
Electric capacity (C3) and the voltage of the 5th internal current source (Source5) control anode are connected, its control terminal and the tenth gate with
The output end of door (I10) is connected, and receives pull-up signal Raise_up；
One end of second switch (W2) is connected with the 4th internal current source (Source4), the other end and first switch (W1), the 3rd
Electric capacity (C3) and the voltage of the 5th internal current source (Source5) control anode are connected, its control terminal and the 8th gate or
The output end of NOT gate (I8) is connected, and receives pulldown signal Pull_down；
3rd electric capacity (C3) and the voltage control of first switch (W1), second switch (W2) and the 5th internal current source (Source5)
Anode processed is connected；
One end of first resistor (R1) is connected with the 5th internal current source (Source5), and is connected to and adapts to open signal VDET_on
End, its other end are connected with the A ends of second resistance (R2), the 5th comparator (A5), output adaptive cut-off signals VDET_off
To the A ends of the 5th comparator (A5)；
One end of second resistance (R2) is connected with sampled signal VDET ends, the other end and first resistor (R1), the 5th comparator
(A5) A ends are connected, output adaptive cut-off signals VDET_off to the A ends of the 5th comparator (A5)；
The input termination of 4th logic gate inverter (I4) opens enable signal SR_ON_EN ends, output the 8th gate of termination or
One end of NOT gate (I8)；
The input termination modulated pwm signal PWM ends of 5th logic gate inverter (I5), output the 6th logic gate inverter of termination
(I6) input and the input of the 7th gate NAND gate (I7)；
The input of 6th logic gate inverter (I6) terminate the 5th logic gate inverter (I5) output end and the 7th gate with
The input of NOT gate (I7), it exports the input of the first delay cell of termination (Delay1)；
The input of 7th gate NAND gate (I7) connects the first delay cell (Delay1) output end, the 5th gate respectively
The input of the output end of phase inverter (I5) and the 6th logic gate inverter (I6), it exports the 8th gate nor gate of termination
(I8) one end；
The input of 8th gate nor gate (I8) connects the output end and the 7th logic of the 4th logic gate inverter (I4) respectively
The output end of door NAND gate (I7), it exports the control terminal of termination second switch (W2), output pulldown signal Pull_down to the
The control terminal of two switches (W2)；
The input of 9th logic gate inverter (I9) and modulated pwm signal PWM ends, the 5th logic gate inverter (I5) it is defeated
Enter end and the tenth gate is connected with the input of door (I10), the input of its output end and the second delay cell (Delay2)
It is connected；
The input of tenth gate and door (I10) connects the output end and modulation pulsewidth letter of the second delay cell (Delay2) respectively
Number PWM ends, it exports the control terminal of termination first switch (W1), output pull-up signal Raise_up to first switch (W1) control
End processed；
The A ends of 5th comparator (A5) are connected with first resistor (R1) and second resistance (R2), receive adaptive cut-off signals
VDET_off, its B end are connected with reference ground, and its output end is connected with cut-off signals SR_OFF ends.
7. synchronous rectifier converter according to claim 6, it is characterised in that：5th internal current source (Source5) is
VCCS, the magnitude of voltage at both ends is controlled by adjusting its voltage, to adjust electric current I, meets following relation：
VDET_on=I* (R1+R2)+VDET
VDET_off=I*R2+VDET
Wherein, R1 refers to first resistor, and R2 refers to second resistance, and VDET refers to sampled signal, and VDET_on refers to adaptive open signal,
VDET_off refers to adaptive cut-off signals.
8. synchronous rectifier converter according to claim 6, it is characterised in that：Pass through the 3rd internal current source
And the 4th internal current source (Source4), first switch (W1), second switch (W2) and the 3rd electric capacity (C3) (Source3)
Control voltage Vctrl adjustment is realized, control voltage Vctrl refers to the 5th internal current source (Source5) voltage control both ends
Magnitude of voltage；
When it is high to pull up signal Raise_up, the 3rd internal current source (Source3) charges to the 3rd electric capacity (C3), control electricity
Vctrl rises are pressed, electric current I becomes big；When pulldown signal Pull_down is high, the 4th internal current source (Source4) is to the 3rd
Electric capacity (C3) is discharged, and control voltage Vctrl is reduced, and electric current I diminishes.
9. synchronous rectifier converter according to claim 6, it is characterised in that：Pull up signal Raise_up generation mechanism
For：Produced by the 9th logic gate inverter (I9), the tenth gate and door (I10) and the second delay cell (Delay2) by adjusting
The fixed pulse width time Delay2 of pulse width signal PWM rising edges triggering processed, set time Delay2 is as pull-up signal Raise_
Up is the high effective time.
10. synchronous rectifier converter according to claim 6, it is characterised in that：Pulldown signal Pull_down generation machine
It is made as：Pass through the 4th logic gate inverter (I4), the 5th logic gate inverter (I5), the 6th logic gate inverter (I6), the 7th
Gate NAND gate (I7), the 8th gate nor gate (I8) and the first delay cell (Delay1) are realized to modulated pwm signal
The detection that enable signal SR_ON_EN is high effective time is opened in PWM trailing edges triggering set time Delay1 pulsewidth；Will be solid
The effective durations of enable signal SR_ON_EN are opened in Delay1 pulsewidths of fixing time, are as pulldown signal Pull_down
The high effective time；When to open enable signal SR_ON_EN in Delay1 pulsewidths between when clamped be always low, then pulldown signal
Pull_down is low.
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| TWI786781B (en) * | 2021-07-21 | 2022-12-11 | 大陸商艾科微電子（深圳）有限公司 | Synchronous rectifier controller and control method thereof |
| CN113364304A (en) * | 2021-08-10 | 2021-09-07 | 深圳市力生美半导体股份有限公司 | Synchronous rectification sampling control circuit, method and chip |
| CN114465452A (en) * | 2022-02-17 | 2022-05-10 | 无锡市晶源微电子有限公司 | Closing point control circuit of synchronous rectifier tube grid drive signal |
| CN115065245A (en) * | 2022-08-04 | 2022-09-16 | 成都利普芯微电子有限公司 | Synchronous rectification control circuit, chip and switching power supply |
| CN115065245B (en) * | 2022-08-04 | 2022-12-16 | 深圳利普芯微电子有限公司 | Synchronous rectification control circuit, chip and switching power supply |
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| CN107508473B (en) | 2019-08-23 |
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