CN204089601U - resonant switching converter and control circuit thereof - Google Patents
resonant switching converter and control circuit thereof Download PDFInfo
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- CN204089601U CN204089601U CN201420613809.7U CN201420613809U CN204089601U CN 204089601 U CN204089601 U CN 204089601U CN 201420613809 U CN201420613809 U CN 201420613809U CN 204089601 U CN204089601 U CN 204089601U
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Abstract
The utility model relates to a resonance switch converter and control circuit thereof. The resonant switching converter comprises an upper side switching tube, a lower side switching tube, a resonant tank circuit and a control circuit. The control circuit comprises a slope sampling circuit and a control circuit, wherein the slope sampling circuit generates a slope signal representing the voltage slope at the common end of the upper side switching tube and the lower side switching tube; the slope judging circuit is used for judging whether the slope signal is effective and generating a slope judging signal; a clock generation circuit that generates a clock signal; and a conduction time control circuit for adjusting the dead time between the upper side switch tube and the lower side switch tube according to the slope judgment signal and the slope signal. Compared with the prior art, the dead time automatic adjustment can be flexibly realized, so that zero voltage switching-on of the upper side switch tube and the lower side switch tube is ensured, and the system efficiency is improved.
Description
Technical field
Embodiment of the present utility model relates to electronic circuit, particularly relates to resonance switch convertor.
Background technology
In resonance switch convertor, under the effect of resonant groove path, the electric current flowing through switching tube becomes sine wave, makes switching tube at a time open-minded, thus realizes no-voltage or Zero Current Switch.
For semibridge system LLC resonant circuit, usually before opening, drop to zero by the voltage on switching tube by the suitable switching frequency of design and Dead Time, and be conducting time negative at electric current.Before switching tube conducting, electric current flows through from diode in the body of switching tube, and now opening switching tube, can to realize no-voltage open-minded.If but Dead Time is excessive, then the electric current of semibridge system LLC resonant circuit can vibrate zero passage, causes capacitance switch.When but Dead Time is too small, along with the inductance value of magnetizing inductance device floats or diminishing along with load current, the switching frequency of semibridge system LLC resonant circuit increases, exciting current reduces, make the voltage on switching tube can not drop to zero before switching tube is opened, thus it is open-minded to realize no-voltage, be unfavorable for improving system effectiveness.
Utility model content
For solving the problems of the technologies described above, the utility model provides a kind of resonance switch convertor and control circuit thereof.
According to a kind of control circuit for resonance switch convertor of the utility model embodiment, described resonance switch convertor comprises the switching circuit with side switch pipe and side switch pipe and the resonant groove path being coupled to switching circuit, described control circuit comprises: slope sample circuit, change in voltage according to the common port place of side switch pipe and side switch pipe produces slope signal, to characterize the voltage slope at the common port place of side switch pipe and side switch pipe; Capacitive mode decision circuitry, the on off state according to representing the current sampling signal and side switch pipe and side switch pipe that flow through resonant groove path electric current judges whether switching circuit is operated in capacitive state, and produces mode signal; Slope decision circuitry, produce slope according to slope signal and judge that signal is to judge that whether slope signal is effective, wherein close at side switch pipe and have no progeny, judge that when detecting that slope signal reduces slope signal is effective, and have no progeny in side switch pipe pass, judge that when detecting that slope signal increases slope signal is effective; Clock generating circuit, clocking, wherein said control circuit controls the shutoff moment of side switch pipe and the shutoff moment of side switch pipe according to clock signal; And turn-on instant control circuit, judge that signal and slope signal regulate the Dead Time between side switch pipe and side switch pipe according to mode signal, slope, wherein when slope signal is effective, control the turn-on instant of side switch pipe according to the comparative result of slope signal and the first slope threshold value, and control the turn-on instant of side switch pipe according to the comparative result of slope signal and the second slope threshold value.
According to embodiment of the present utility model, wherein when slope signal is invalid, control the turn-on instant of side switch pipe according to the comparative result of current sampling signal and the first current threshold, and control the turn-on instant of side switch pipe according to the comparative result of current sampling signal and the second current threshold.
According to embodiment of the present utility model, wherein slope sample circuit also comprises: the first capacitor, and have first end and the second end, wherein first end is coupled to the common port of side switch pipe and side switch pipe, the second end output voltage gradient signal; First resistor, has first end and the second end, and wherein first end is coupled to the second end of the first capacitor, and the second end is coupled to systematically; And voltage control circuit, coupled in parallel is at the two ends of the first resistor, and wherein when the conducting of side switch pipe, voltage control circuit controls slope signal and keeps high level, and when downside switching tube conducting, voltage control circuit controls slope signal and keeps low level.
According to embodiment of the present utility model, wherein voltage control circuit also comprises: the first current source, and wherein when the conducting of side switch pipe, the first current source provides charging current, until the conducting of side switch pipe for the first resistor; And second current source, wherein when downside switching tube conducting, the second current source provides discharging current, until the conducting of side switch pipe for the first resistor.
According to embodiment of the present utility model, wherein when side switch pipe turns off, the absolute value flowing through the electric current at the first capacitor two ends is greater than the charging current that the first current source provides, when downside switching tube turns off, the absolute value flowing through the electric current at the first capacitor two ends is greater than the discharging current that the second current source provides.
According to embodiment of the present utility model, wherein slope decision circuitry also comprises: the first comparator, there is first input end, the second input and output, wherein first input end receives slope signal, second input receives the 3rd slope threshold value, and output exports the first comparison signal according to the comparative result of slope signal and the 3rd slope threshold value; Second comparator, there is first input end, the second input and output, wherein first input end receives slope signal, and the second input receives the 4th slope threshold value, and output exports the second comparison signal according to the comparative result of slope signal and the 4th slope threshold value; And first logical circuit, produce slope according to the first comparison signal, the second comparison signal and clock signal and judge signal, wherein after the rising edge of clock signal, produce slope according to the first comparison signal and judge that signal is to judge that whether slope signal is effective, and after the trailing edge of clock signal, produce slope according to the second comparison signal and judge that signal is to judge that whether slope signal effective.
According to embodiment of the present utility model, wherein turn-on instant control circuit comprises: the 3rd comparator, has first input end, the second input and output, and wherein first input end receives slope signal, second input receives the first slope threshold value, and output exports the 3rd comparison signal; 4th comparator, have first input end, the second input and output, wherein first input end received current sampled signal, the second input receives the first current threshold, and output exports the 4th comparison signal; 5th comparator, has first input end, the second input and output, and wherein first input end receives slope signal, and the second input receives the second slope threshold value, and output exports the 5th comparison signal; 6th comparator, have first input end, the second input and output, wherein first input end received current sampled signal, the second input receives the second current threshold, and output exports the 6th comparison signal; Second logical circuit, there is first input end, the second input and output, wherein first input end receiving mode signal, the second input receive time-out signal, when mode signal indicator cock circuit working is in capacitive state, timeout signal exports at its output by the second logical circuit; 3rd logical circuit, there is first input end, the second input and output, wherein first input end receiving mode signal, second input receives maximum dead-time signal, when mode signal indicator cock circuit working is in non-capacitive state, maximum dead-time signal exports at its output by the second logical circuit; First OR circuit, there is first input end, the second input, the 3rd input, four-input terminal and output, wherein first input end is coupled to the output of the 3rd comparator, second input is coupled to the output of the 4th comparator, 3rd input is coupled to the output of the second logical circuit, four-input terminal is coupled to the output of the 3rd logical circuit, and output exports the first reset signal to control the turn-on instant of side switch pipe; And second OR circuit, there is first input end, the second input, the 3rd input, four-input terminal and output, wherein first input end is coupled to the output of the 5th comparator, second input is coupled to the output of the 6th comparator, 3rd input is coupled to the output of the second logical circuit, four-input terminal is coupled to the output of the 3rd logical circuit, and output exports the second reset signal to control the turn-on instant of side switch pipe.
According to a kind of resonance switch convertor of the utility model embodiment, comprising: switching circuit, comprise side switch pipe and the side switch pipe of coupled in series; Resonant groove path, be coupled in side switch pipe and side switch pipe common port and systematically between; Current sampling circuit, according to the electric current generation current sampled signal flowing through resonant groove path; And foregoing control circuit.
According to a kind of resonance switch convertor of the utility model embodiment, comprising: side switch pipe, have first end, the second end and control end, wherein first end receives input voltage; Side switch pipe, has first end, the second end and control end, and wherein first end is coupled to the second end of side switch pipe, and the second end is coupled to systematically; Resonant groove path, be coupled in side switch pipe and side switch pipe common port and systematically between; Current sampling circuit, according to the electric current generation current sampled signal flowing through resonant groove path; Slope sample circuit, the change in voltage according to the common port place of side switch pipe and side switch pipe produces slope signal, to characterize the voltage slope at the common port place of side switch pipe and side switch pipe; Slope decision circuitry, produce slope according to slope signal and judge that signal is to judge that whether slope signal is effective, wherein close at side switch pipe and have no progeny, judge that when detecting that slope signal reduces slope signal is effective, and have no progeny in side switch pipe pass, judge that when detecting that slope signal increases slope signal is effective; Clock generating circuit, clocking, wherein said control circuit controls the shutoff moment of side switch pipe and the shutoff moment of side switch pipe according to clock signal; And turn-on instant control circuit, judge that signal, current sampling signal and slope signal adjust the Dead Time between side switch pipe and side switch pipe automatically according to slope; Wherein when slope signal is effective, control the turn-on instant of side switch pipe according to the comparative result of slope signal and the first slope threshold value, and control the turn-on instant of side switch pipe according to the comparative result of slope signal and the second slope threshold value; And when slope signal is invalid, control the turn-on instant of side switch pipe according to the comparative result of current sampling signal and the first current threshold, and control the turn-on instant of side switch pipe according to the comparative result of current sampling signal and the second current threshold.
According to embodiment of the present utility model, wherein slope decision circuitry also comprises: the first comparator, there is first input end, the second input and output, wherein first input end receives slope signal, second input receives the 3rd slope threshold value, and output exports the first comparison signal according to the comparative result of slope signal and the 3rd slope threshold value; Second comparator, there is first input end, the second input and output, wherein first input end receives slope signal, and the second input receives the 4th slope threshold value, and output exports the second comparison signal according to the comparative result of slope signal and the 4th slope threshold value; And first logical circuit, produce slope according to the first comparison signal, the second comparison signal and clock signal and judge signal, wherein after the rising edge of clock signal, produce slope according to the first comparison signal and judge that signal is to judge that whether slope signal is effective, and after the trailing edge of clock signal, produce slope according to the second comparison signal and judge that signal is to judge that whether slope signal effective.
According to embodiment of the present utility model, close at side switch pipe and have no progeny, if slope signal is judged as effectively, then when slope signal is less than the first slope threshold value, control the conducting of side switch pipe; And have no progeny in side switch pipe pass, if slope signal is judged as effectively, then when slope signal is greater than the second slope threshold value, control the conducting of side switch pipe.
In embodiment of the present utility model, according to the Dead Time between slope signal automatic regulating switch pipe, thus the no-voltage that can realize switching tube flexibly, is reliably open-minded.
Accompanying drawing explanation
Fig. 1 is the circuit block diagram of the resonance switch convertor 100 according to the utility model embodiment;
Fig. 2 is the circuit diagram of the resonance switch convertor 100 according to the utility model embodiment;
Fig. 3 is the circuit diagram of the Dead Time Circuit tuning 16 in resonance switch convertor 100 according to Fig. 2 of the utility model embodiment;
Fig. 4 is the circuit diagram of the clock generating circuit 18 in resonance switch convertor 100 according to Fig. 2 of the utility model embodiment;
Fig. 5 is the circuit diagram of the capacitive mode decision circuitry 15 in resonance switch convertor 100 according to Fig. 2 of the utility model embodiment;
Fig. 6 is the circuit diagram of the slope sample circuit 13 in resonance switch convertor 100 according to Fig. 2 of the utility model one embodiment;
Fig. 7 for according to Fig. 2 of the utility model embodiment resonance switch convertor 100 adjust the oscillogram of Dead Time when slope signal VHB is effective; And
Fig. 8 for according to Fig. 2 of the utility model embodiment resonance switch convertor 100 adjust the oscillogram of Dead Time when slope signal VHB is invalid.
Describe the specific embodiment of the present invention in detail below with reference to the accompanying drawings.Run through the identical Reference numeral of institute's drawings attached and represent identical or similar parts or feature.
Embodiment
To specific embodiment of the utility model be described in detail below, it should be noted that the embodiments described herein is only for illustrating, is not limited to the utility model.In the following description, in order to provide thorough understanding of the present utility model, a large amount of specific detail has been set forth.But, those of ordinary skill in the art be it is evident that: these specific detail need not be adopted to carry out the utility model.In other instances, in order to avoid obscuring the utility model, do not specifically describe known circuit, material or method.
In whole specification, " embodiment ", " embodiment ", " example " or mentioning of " example " are meaned: the special characteristic, structure or the characteristic that describe in conjunction with this embodiment or example are comprised at least one embodiment of the utility model.Therefore, the phrase " in one embodiment " occurred in each place of whole specification, " in an embodiment ", " example " or " example " differ to establish a capital and refer to same embodiment or example.In addition, can with any combination suitably and or sub-portfolio by specific feature, structure or property combination in one or more embodiment or example.In addition, it should be understood by one skilled in the art that the accompanying drawing provided at this is all for illustrative purposes, and accompanying drawing is not necessarily drawn in proportion.Should be appreciated that when claim " element " " be connected to " or " coupling " to another element time, it can be directly connected or coupled to another element or can there is intermediary element.On the contrary, when claim element " be directly connected to " or " being directly coupled to " another element time, there is not intermediary element.Identical Reference numeral indicates identical element.Term "and/or" used herein comprises any and all combinations of one or more relevant project listed.
Fig. 1 is the circuit block diagram of the resonance switch convertor 100 according to the utility model embodiment.Resonance switch convertor 100 comprises: switching circuit 11, resonant groove path 12, slope sample circuit 13, current sampling circuit 14, capacitive mode decision circuitry 15, Dead Time Circuit tuning 16, ON-OFF control circuit 17 and clock generating circuit 18.Switching circuit 11 receives input voltage VIN, and provides output voltage VO by resonant groove path 12.Switching circuit 11 is coupled to resonant groove path 12 by end points SW, and wherein switching circuit 11 comprises at least two switching tubes, and end points SW is the common port of at least two switching tubes.
Slope sample circuit 13 is coupled to end points SW, and the change in voltage according to end points SW place produces slope signal VHB.Current sampling circuit 14 is according to the electric current generation current sampled signal Vcs flowing through resonant groove path 12.Clock generating circuit 18 clocking CLK.Capacitive mode decision circuitry 15 produces mode signal Cap_mode according to current sampling signal Vcs.Capacitive mode decision circuitry 15 judges by current sampling signal Vcs the current polarity flowing through resonant groove path 12, and whether is operated in capacitive state signal Cap_mode to generate the model in conjunction with the condition adjudgement switching circuit 11 of at least two switching tubes in switching circuit 11.In one embodiment, when switching circuit 11 is operated in capacitive state, mode signal Cap_mode controls resonance switch convertor 100 and is operated in capacitive protected mode.Dead Time Circuit tuning 16 receives slope signal VHB and mode signal Cap_mode, and produce dead zone function signal ADT, thus the Dead Time that can adjust automatically in switching circuit 11 between two switching tubes, open-minded with the no-voltage realizing at least two switching tubes in switching circuit 11.Wherein said " Dead Time " refers to from the switching tube of switching circuit 11 and turns off time interval between another switching tube conducting.ON-OFF control circuit 17 produces according to clock signal clk and dead zone function signal ADT and is used for the control signal HG of a switching tube and the control signal LG for another switching tube in control switch circuit 11 in control switch circuit 11.In one embodiment, ON-OFF control circuit 17 according to the shutoff moment of at least two switching tubes in clock signal clk control switch circuit 11, according to the turn-on instant of at least two switching tubes in dead zone function signal ADT control switch circuit 11.
In the embodiment shown in fig. 1, resonance switch convertor 100 according to the change in voltage at end points SW place and flow through resonant groove path 12 electric current automatic adjustment switch circuit 11 in Dead Time between at least two switching tubes, thus it is open-minded to ensure can to realize no-voltage at full-load range interior resonance switch converters 100.
Fig. 2 is the circuit diagram of the resonance switch convertor 100 according to the utility model embodiment.Resonance switch convertor 100 comprises the switching circuit be made up of side switch pipe S1 and side switch pipe S2, the resonant groove path be made up of capacitor Cr, resonant inductance Lr and magnetizing inductance Lm, the output circuit that is made up of transformer T, rectifier diode D1, rectifier diode D2, output capacitor Co, and wherein resonant groove path is coupled to the public point SW of side switch pipe S1 and side switch pipe S2.In one embodiment, the former limit winding of transformer T comprises magnetizing inductance Lm, and resonant inductance Lr can be independently inductor.Side switch pipe S1 and side switch pipe S2 can be any controllable semiconductor switch device, such as mos field effect transistor (MOSFET), igbt (IGBT) etc.Although the embodiment shown in Fig. 2 adopts semibridge system LLC topological structure, those skilled in the art are known, and resonance switch convertor 100 also can adopt other suitable topological structures, such as full-bridge type LLC converter, asymmetrical half-bridge resonance switch convertor etc.
Slope sample circuit 13 is coupled to the public point SW of side switch pipe S1 and side switch pipe S2, and produces slope signal VHB according to the change in voltage at end points SW place.In the embodiment shown in Figure 2, slope sample circuit 13 comprises capacitor Cd, resistor Rd and voltage control circuit 20.Voltage control circuit 20 is coupled in the two ends of resistor Rd, remains unchanged for controlling slope signal VHB when side switch pipe S1 or the S2 conducting of side switch pipe.One end of capacitor Cd is coupled to end points SW, and the other end Nd1 of capacitor Cd is coupled to systematically by resistor Rd, and end points Nd1 provides slope signal VHB as the output of slope sample circuit 13.It will be understood by those skilled in the art that resistor Rd also can be substituted by other suitable elements, such as, in the equivalent resistance of circuit, the integrated circuit equivalent resistance etc. of triode.The electric current I d flowing through capacitor Cd changes along with the change in voltage at end points SW place, such as when the voltage at end points SW place reduces, the electric current I d flowing through capacitor Cd is negative, thus electric current I d discharges to capacitor Cd, slope signal VHB is decreased to minimum value under the control of electric current I d and voltage control circuit 20, until when the voltage at end points SW place is constant, electric current I d is zero, and slope signal VHB increases until side switch pipe S2 conducting gradually under the control of voltage control circuit 20; When the voltage at end points SW place increases, the electric current I d flowing through capacitor Cd is just, thus electric current I d charges to capacitor Cd, slope signal VHB increases to maximum under the control of electric current I d and voltage control circuit 20, until when the voltage at end points SW place is constant, electric current I d is zero, and slope signal VHB reduces until side switch pipe S1 conducting gradually under the control of voltage control circuit 20.When the S1 conducting of side switch pipe, voltage control circuit 20 controls slope signal VHB and keeps its maximum, namely high level; When downside switching tube S2 conducting, voltage control circuit 20 controls slope signal VHB and keeps its minimum value, namely low level.Fig. 6 is the circuit diagram of the slope sample circuit 13 according to the utility model one embodiment.
Current sampling circuit 14 is according to the electric current I r generation current sampled signal Vcs flowing through resonant groove path.In the embodiment shown in Figure 2, current sampling circuit 14 comprises resistor Rs and differential amplifier Am1.Those skilled in the art are known, and current sampling circuit 14 also can comprise other suitable current sampling circuits.
Dead Time Circuit tuning 16 comprises slope decision circuitry 161, turn-on instant control circuit 162 and dead band generative circuit 163.Slope decision circuitry 161 produces slope according to slope signal VHB and judges signal SL, to judge that whether slope signal VHB is effective.In one embodiment, close in the Preset Time of having no progeny at side switch pipe S1, when detecting that slope signal VHB reduces, slope decision circuitry 161 judges that slope signal VHB is effective, otherwise when the reduction of slope signal VHB not detected, slope decision circuitry 161 judges that slope signal VHB is invalid.In one embodiment, close in the Preset Time of having no progeny at side switch pipe S2, when detecting that slope signal VHB increases, slope decision circuitry 161 judges that slope signal VHB is effective, otherwise when the increase of slope signal VHB not detected, slope decision circuitry 161 judges that slope signal VHB is invalid.
Turn-on instant control circuit 162 receives slope and judges signal SL, mode signal Cap_mode, slope signal VHB, and current sampling signal Vcs or fixed delay signal Tdfx, and produce reset signal Rs1 and reset signal Rs2, wherein reset signal Rs1 is for controlling the turn-on instant of side switch pipe S2, namely for controlling the Dead Time turning off side switch pipe S2 conducting from side switch pipe S1, reset signal Rs2 is for controlling the turn-on instant of side switch pipe S1, namely for controlling the Dead Time turning off side switch pipe S1 conducting from side switch pipe S2.In one embodiment, when mode signal Cap_mode indicates resonance switch convertor 100 to be operated in capacitive state, turn-on instant control circuit 162 terminates Dead Time according to slope signal VHB, timeout signal Tmout, control the turn-on instant of side switch pipe S1 and the turn-on instant of side switch pipe S2, such as produce reset signal Rs1 to control the turn-on instant of side switch pipe S2 according to slope signal VHB and timeout signal Tmout, produce reset signal Rs2 to control the turn-on instant of side switch pipe S1 according to slope signal VHB and timeout signal Tmout.It is 10ms that timeout signal Tmout such as can represent time-out time, and when Dead Time equals time-out time, conducting side switch pipe S1 or side switch pipe S2 forced by turn-on instant control circuit 162.When slope decision circuitry 161 judges that slope signal VHB is invalid, slope signal VHB can not reflect the change in voltage at end points SW place, turn-on instant control circuit 162 terminates Dead Time according to current sampling signal Vcs or fixed delay signal Tdfx, control the turn-on instant of side switch pipe S1 and the turn-on instant of side switch pipe S2, such as produce reset signal Rs1 to control the turn-on instant of side switch pipe S2 according to current sampling signal Vcs or fixed delay signal Tdfx, and produce reset signal Rs2 to control the turn-on instant of side switch pipe S1 according to current sampling signal Vcs or fixed delay signal Tdfx.It is 0.5us that fixed delay signal Tdfx such as can represent default turn on delay time.When slope decision circuitry 161 judges that slope signal VHB is effective, turn-on instant control circuit 162 terminates Dead Time according to slope signal VHB and maximum dead-time signal Tdmax, control the turn-on instant of side switch pipe S1 and the turn-on instant of side switch pipe S2, such as produce reset signal Rs1 to control the turn-on instant of side switch pipe S2 according to slope signal VHB and maximum dead-time signal Tdmax, produce reset signal Rs2 to control the turn-on instant of side switch pipe S1 according to slope signal VHB and maximum dead-time signal Tdmax.It is 2us that maximum dead-time signal Tdmax such as can represent maximum Dead Time, and when Dead Time equals maximum Dead Time, conducting side switch pipe S1 or side switch pipe S2 forced by turn-on instant control circuit 162.
Dead band generative circuit 163 receives reset signal Rs1 and reset signal Rs2, and produces dead zone function signal ADT.In one embodiment, when side switch pipe S1 turns off, dead zone function signal ADT becomes the first state (such as low level), timing circuit starts timing, until when reset signal Rs1 is effective, dead zone function signal ADT becomes the second state (such as high level) with conducting side switch pipe S2.In one embodiment, when downside switching tube S2 turns off, dead zone function signal ADT becomes the first state (such as low level), timing circuit starts timing, until when reset signal Rs2 is effective, dead zone function signal ADT becomes the second state (such as high level) with conducting side switch pipe S1.Wherein, timing circuit such as can be used for producing timeout signal Tmout, fixed delay signal Tdfx, maximum dead-time signal Tdmax.
In the embodiment shown in Figure 2, when slope sample circuit 13 can not export effective slope signal VHB, such as during capacitor Cd fault, Dead Time Circuit tuning 16 can according to the fixed delay signal Tdfx controlling dead error time, or to realize no-voltage open-minded with approximate to adjust Dead Time automatically according to current sampling signal Vcs.
Clock generating circuit 18 clocking CLK and clock signal clk N, wherein clock signal clk and clock signal clk N are contrary in phase place.Fig. 4 is the circuit diagram of the clock generating circuit 18 according to the utility model one embodiment.ON-OFF control circuit 17 produces the control signal HG for controlling side switch pipe S1 according to clock signal clk and dead zone function signal ADT, and produces the control signal LG for controlling side switch pipe S2 according to clock signal clk N and dead zone function signal ADT.In one embodiment, when clock signal clk is in trailing edge, dead zone function signal ADT becomes the first state (such as low level), control signal HG becomes low level to turn off side switch pipe S1, until dead zone function signal ADT becomes the second state (such as high level), control signal LG becomes high level with conducting side switch pipe S2; When clock signal clk is in rising edge, dead zone function signal ADT becomes the first state (such as low level), control signal LG becomes low level to turn off side switch pipe S2, until dead zone function signal ADT becomes the second state (such as high level), control signal HG becomes high level with conducting side switch pipe S1.In the embodiment shown in Figure 2, ON-OFF control circuit 17 comprises AND circuit 171 and AND circuit 172.AND circuit 171 produces control signal HG according to clock signal clk and dead zone function signal ADT.AND circuit 172 produces control signal LG according to clock signal clk N and dead zone function signal ADT.Control signal HG is coupled to the control end of side switch pipe S1 to control conducting and the shutoff of side switch pipe S1 by drive circuit Dr1.Control signal LG is coupled to the control end of side switch pipe S2 to control conducting and the shutoff of side switch pipe S2 by drive circuit Dr2.
Fig. 3 is the circuit diagram of the Dead Time Circuit tuning 16 in resonance switch convertor 100 according to Fig. 2 of the utility model embodiment.Close at side switch pipe S1 and have no progeny, according to the comparative result of slope signal VHB and slope threshold value Vx0, slope decision circuitry 161 judges that whether slope signal VHB is effective; And have no progeny in side switch pipe S2 pass, according to the comparative result of slope signal VHB and slope threshold value Vx1, slope decision circuitry 161 judges that whether slope signal VHB is effective.In one embodiment, close in the Preset Time of having no progeny at side switch pipe S1, when detecting that slope signal VHB is less than slope threshold value Vx0, slope decision circuitry 161 judges that slope signal VHB is effective, otherwise judges that slope signal VHB is invalid; Close in the Preset Time of having no progeny at side switch pipe S2, when detecting that slope signal is greater than slope threshold value Vx1, slope decision circuitry 161 judges that slope signal VHB is effective, otherwise judges that slope signal VHB is invalid.In the embodiment shown in fig. 3, slope decision circuitry 161 comprises comparator 311, AND circuit 312, comparator 314, AND circuit 315 and OR-NOT circuit 317.The in-phase input end of comparator 311 receives slope signal VHB, and the inverting input of comparator 311 receives slope threshold value Vx1, and the output of comparator 311 is coupled to an input of D AND circuit 312.Another input receive clock signal CLK of AND circuit 312.The in-phase input end of comparator 314 receives slope threshold value Vx0, and the inverting input of comparator 314 receives slope signal VHB, and the output of comparator 314 is coupled to an input of AND circuit 315.An input of OR-NOT circuit 317 is coupled to the output of AND circuit 312, and another input of OR-NOT circuit 317 is coupled to the output of AND circuit 315, and the output of OR-NOT circuit 317 provides slope to judge signal SL.When slope signal VHB is greater than slope threshold value Vx1, and when clock signal clk is high level, slope decision circuitry 161 judges that slope signal VHB is effective, and slope judges that signal SL maintains low level.When slope signal VHB is less than slope threshold value Vx0, and when clock signal clk N is high level, slope decision circuitry 161 judges that slope signal VHB is effective, and slope judges that signal SL maintains low level.
When slope signal VHB is effective, turn-on instant control circuit 162 produces reset signal Rs1 to adjust the Dead Time that side switch pipe S1 turns off side switch pipe S2 conducting according to the comparative result of slope signal VHB and slope threshold value Vd1, produces reset signal Rs2 to adjust the Dead Time that side switch pipe S2 turns off side switch pipe S1 conducting according to the comparative result of slope signal VHB and slope threshold value Vd2.Such as, side switch pipe S1 closes and has no progeny, after detecting that slope signal VHB is effectively, when slope signal VHB is greater than slope threshold value Vd1, and side switch pipe S2 conducting under the control of reset signal Rs1; Side switch pipe S2 closes and has no progeny, after detecting that slope signal VHB is effectively, when slope signal VHB is less than slope threshold value Vd2, and side switch pipe S1 conducting under the control of reset signal Rs2.When slope signal VHB is invalid, turn-on instant control circuit 162 produces reset signal Rs1 to adjust the Dead Time that side switch pipe S1 turns off side switch pipe S2 conducting according to the comparative result of current sampling signal Vcs and current threshold Vth1, produces reset signal Rs2 to adjust the Dead Time that side switch pipe S2 turns off side switch pipe S1 conducting according to the comparative result of current sampling signal Vcs and current threshold Vth2.Such as, side switch pipe S1 close have no progeny, when slope signal VHB is invalid, when current sampling signal Vcs be reduced to be less than current threshold Vth1 time, side switch pipe S2 conducting under the control of reset signal Rs1; Side switch pipe S2 close have no progeny, when slope signal VHB is invalid, when current sampling signal Vcs increase to be greater than current threshold Vth2 time, side switch pipe S1 conducting under the control of reset signal Rs2.In other embodiments, when slope signal VHB is invalid, turn-on instant control circuit 162 also can produce reset signal Rs1 to control the turn-on instant of side switch pipe S2 according to fixed delay signal Tdfx, and produces reset signal Rs2 to control the turn-on instant of side switch pipe S1 according to fixed delay signal Tdfx.In the embodiment shown in fig. 3, turn-on instant control circuit 162 comprises comparator 321, comparator 322, comparator 326, comparator 327, AND circuit 323, AND circuit 328, OR circuit 329, OR circuit 320, logical circuit 3211 and logical circuit 3212.The in-phase input end of comparator 321 receives slope signal VHB, and inverting input receives slope threshold value Vd1, and an input of OR circuit 329 is coupled to the output of comparator 321 by logical circuit 3211.When slope decision circuitry 161 judges that slope signal VHB is effective, slope judges that signal SL is low level, and when slope signal VHB is greater than slope threshold value Vd1, reset signal Rs1 becomes high level, and controls side switch pipe S2 conducting by dead band generative circuit 163.The in-phase input end received current threshold value Vth1 of comparator 322, inverting input received current sampled signal Vcs, the output of comparator 322 is coupled to an input of OR circuit 329 by AND circuit 323.Slope judges that signal SL is coupled to another input of AND circuit 323.When slope decision circuitry 161 judges that slope signal VHB is invalid, slope judges that signal SL is high level, when current sampling signal Vcs is less than current threshold Vth1, reset signal Rs1 becomes high level, and controls side switch pipe S2 conducting by dead band generative circuit 163.The in-phase input end of comparator 326 receives slope threshold value Vd2, and the inverting input of comparator 326 receives slope signal VHB, and an input of OR circuit 320 is coupled to the output of comparator 326 by logical circuit 3212.When slope decision circuitry 161 judges that slope signal VHB is effective, slope judges that signal SL is low level, and when slope signal VHB is less than slope threshold value Vd2, reset signal Rs2 becomes high level, and controls side switch pipe S1 conducting by dead band generative circuit 163.The in-phase input end received current sampled signal Vcs of comparator 327, inverting input received current threshold value Vth2, the output of comparator 327 is coupled to an input of OR circuit 320 by AND circuit 328.Slope judges that signal SL is coupled to another input of AND circuit 328.When slope decision circuitry 161 judges that slope signal VHB is invalid, slope judges that signal SL is high level, when current sampling signal Vcs is greater than current threshold Vth2, reset signal Rs2 becomes high level, and controls side switch pipe S1 conducting by dead band generative circuit 163.In the embodiment shown in fig. 3, turn-on instant control circuit 162 also comprises logical circuit 324 and logical circuit 325.An input receiving mode signal Cap_mode of logical circuit 324, another input receives maximum dead-time signal Tdmax, and output is coupled to an input of OR circuit 329 and an input of OR circuit 320.An input receiving mode signal Cap_mode of logical circuit 325, another input receive time-out signal Tmout, output is coupled to an input of OR circuit 329 and an input of OR circuit 320.When mode signal Cap_mode indicates resonance switch convertor 100 to be operated in capacitive state, logical circuit 324 output low level is to OR circuit 329 OR circuit 320, maximum dead-time signal Tdmax is inoperative to Dead Time, and timeout signal Tmout is passed to OR circuit 329 and OR circuit 320 to control the maximum Dead Time between side switch pipe S1 and side switch pipe S2 by logical circuit 325.When mode signal Cap_mode indicates resonance switch convertor 100 to be operated in perceptual state, logical circuit 325 output low level is to OR circuit 329 and OR circuit 320, timeout signal Tmout is inoperative to Dead Time, and maximum dead-time signal Tdmax is passed to OR circuit 329 and OR circuit 320 to control the maximum Dead Time between side switch pipe S1 and side switch pipe S2 by logical circuit 324.
Dead band generative circuit 163 closes at side switch pipe S1 has no progeny, and produces dead zone function signal ADT to control the turn-on instant of side switch pipe S2 according to reset signal Rs1; Close at side switch pipe S2 and have no progeny, produce dead zone function signal ADT to control the turn-on instant of side switch pipe S1 according to reset signal Rs2.In the embodiment shown in fig. 3, dead band generative circuit 163 comprises rest-set flip-flop 331, rest-set flip-flop 332 and OR-NOT circuit 334.The set end S receive clock signal CLKN of rest-set flip-flop 331, reset terminal R receives reset signal Rs1, and output Q exports dead zone function signal ADT by OR-NOT circuit 334.When clock signal CLKN becomes high level, side switch pipe S1 turns off, rest-set flip-flop 331 set, and dead zone function signal ADT becomes low level; When reset signal Rs1 is high level, rest-set flip-flop 331 resets, and dead zone function signal ADT becomes high level, side switch pipe S2 conducting.The set end S receive clock signal CLK of rest-set flip-flop 332, reset terminal R receives reset signal Rs2, and output Q exports dead zone function signal ADT by OR-NOT circuit 334.When clock signal clk becomes high level, side switch pipe S2 turns off, rest-set flip-flop 332 set, and dead zone function signal ADT becomes low level; When reset signal Rs2 is high level, rest-set flip-flop 332 set, dead zone function signal ADT becomes high level, side switch pipe S1 conducting.
Fig. 4 is the circuit diagram of the clock generating circuit 18 in resonance switch convertor 100 according to Fig. 2 of the utility model embodiment.In one embodiment, clock generating circuit 18 suspends vibration in the Dead Time of side switch pipe S1 and side switch pipe S2, thus make control signal HG substantially identical with the high level width of control signal LG, namely the ON time of side switch pipe S1 is substantially identical with the ON time of side switch pipe S2.In the embodiment shown in fig. 4, clock generating circuit 18 comprises current source IS3, current source IS4, switch S 5, switch S 6, switch S 7, capacitor Ct, comparator 41, comparator 42 and rest-set flip-flop 43.Current source IS3, switch S 5, current source IS4 and switch S 6 be coupled in series in voltage vcc and systematically between.One end of current source IS3 is coupled to voltage vcc, and the other end of current source IS3 is coupled to one end of capacitor Ct by switch S 7, the other end of capacitor Ct is coupled to systematically.One end of current source IS4 is coupled to one end of capacitor Ct by switch S 7, the other end of current source IS4 is coupled to systematically.Switch S 5 and current source IS3 coupled in series, charge to capacitor Ct according to clock signal clk to control current source IS3.Switch S 6 and current source IS4 coupled in series, discharge to capacitor Ct according to clock signal clk N to control current source IS4, and capacitor Ct two ends produce voltage Vct.In one embodiment, switch S 7 conducting and shutoff under the control of dead zone function signal ADT.When side switch pipe S1 and side switch pipe S2 all turns off, switch S 7 turns off, and the voltage Vct at capacitor Ct two ends keeps until a conducting in side switch pipe S1 and side switch pipe S2; When a conducting in side switch pipe S1 and side switch pipe S2, switch S 7 conducting, current source IS3 charges to capacitor Ct when clock signal clk is high level, and current source IS4 discharges to capacitor Ct when clock signal clk is low level.The in-phase input end of comparator 41 receives compare threshold Vc2, and inverting input is coupled to capacitor Ct with receiver voltage Vct, and output is coupled to the set input S of rest-set flip-flop 43.When voltage Vct is less than compare threshold Vc2, rest-set flip-flop 43 set exports the clock signal clk of high level and low level clock signal clk N.The in-phase input end of comparator 42 is coupled to capacitor Ct with receiver voltage Vct, and inverting input receives compare threshold Vc1, and output is coupled to the RESET input R of rest-set flip-flop 43.When voltage Vct is greater than compare threshold Vc1, rest-set flip-flop 43 resets the clock signal clk of output low level and the clock signal clk N of high level.Wherein compare threshold Vc2 is less than compare threshold Vc1, such as Vc2=0.9V, Vc1=3.9V
Fig. 5 is the circuit diagram of the capacitive mode decision circuitry 15 in resonance switch convertor 100 according to Fig. 2 of the utility model embodiment.In one embodiment, by the polarity of the electric current I r judging resonant groove path, capacitive mode decision circuitry 15, when side switch pipe S1 or side switch pipe S2 turns off, judges that resonance switch convertor 100 is operated in capacitive state or perceptual state.When side switch pipe S1 turns off, when flowing through the electric current I r polarity of resonant groove path for time negative, judge that resonance switch convertor 100 is operated in capacitive state, otherwise when the electric current I r polarity flowing through resonant groove path is timing, judge that resonance switch convertor 100 is operated in perceptual state.When side switch pipe S2 turns off, when the electric current I r polarity flowing through resonant groove path is timing, judge that resonance switch convertor 100 is operated in capacitive state, otherwise when flowing through the electric current I r polarity of resonant groove path for time negative, judge that resonance switch convertor 100 is operated in perceptual state.In the embodiment shown in fig. 5, capacitive mode decision circuitry 15 comprises the current polarity decision circuitry, d type flip flop 53, d type flip flop 54 and the OR circuit 55 that are made up of comparator 51 and comparator 52.The inverting input received current sampled signal Vcs of comparator 51, in-phase input end receives negative current threshold value-Vcm, and output is coupled to the data input pin D of d type flip flop 53.The input end of clock C receive clock signal CLK of d type flip flop 53, the reset terminal Rst receive clock signal CLKN of d type flip flop 53, output Q judges signal Pol1 at the rising edge of clock signal clk according to the Output rusults polarization of comparator 51, and judges that signal Pol1 is to low level in the rising edge generation pulse signal reset polarity of clock signal clk N.At the rising edge of clock signal clk, when current sampling signal Vcs is less than negative current threshold value-Vcm, comparator 51 output low level, the electric current I r polarity that resonant groove path is flow through in instruction is negative, resonance switch convertor 100 is operated in perceptual state, and polarity judges that signal Pol1 is low level; Otherwise at the rising edge of clock signal clk, when current sampling signal Vcs is greater than negative current threshold value-Vcm, comparator 51 exports high level, the electric current I r polarity that resonant groove path is flow through in instruction is non-negative, resonance switch convertor 100 is operated in capacitive state, polarity judges that signal Pol1 is high level, and mode signal Cap_mode becomes high level.The inverting input of comparator 52 receives positive current threshold value Vcm, and in-phase input end received current sampled signal Vcs, output is coupled to the data input pin D of d type flip flop 54.The input end of clock C receive clock signal CLKN of d type flip flop 54, the reset terminal Rst receive clock signal CLK of d type flip flop 54, output Q is at the rising edge of clock signal clk N, namely judge signal Pol2 at the trailing edge of clock signal clk according to the Output rusults polarization of comparator 52, and judge that signal Pol2 is to low level in the rising edge generation pulse signal reset polarity of clock signal clk.At the trailing edge of clock signal clk, when current sampling signal Vcs is greater than positive current threshold value Vcm, comparator 52 output low level, the electric current I r polarity that resonant groove path is flow through in instruction is just, resonance switch convertor 100 is operated in perceptual state, and polarity judges that signal Pol2 is low level; Otherwise at the trailing edge of clock signal clk, when current sampling signal Vcs is less than positive current threshold value Vcm, comparator 52 exports high level, the electric current I r polarity that resonant groove path is flow through in instruction is anon-normal, resonance switch convertor 100 is operated in capacitive state, polarity judges that signal Pol2 is high level, and mode signal Cap_mode becomes high level.In one embodiment, positive current threshold value Vcm such as equals 80mV, and negative current threshold value-Vcm such as equals-80mV.
Fig. 6 is the circuit diagram of the slope sample circuit 13 in resonance switch convertor 100 according to Fig. 2 of the utility model one embodiment.In the embodiment shown in fig. 6, slope sample circuit 13 comprises capacitor Cd, resistor Rd and comprises the voltage control circuit of current source IS1 and current source IS2.Slope sample circuit 13 also comprises the switch S 3 be in series with current source IS1, and the switch S 4 be in series with current source IS2.Current source IS1 is that end points Nd1 charges when switch S 3 conducting, and current source IS2 discharges to end points Nd1 when switch S 4 conducting.Current source IS1, current source IS2 and flow through capacitor Cd electric current I d acting in conjunction under on end points Nd1, produce slope signal VHB.When the S1 conducting of side switch pipe, switch S 4 turns off under the control of control signal QL, switch S 3 conducting under the control of control signal QH.Slope signal VHB increases and maintains high level, when side switch pipe S1 turns off, the voltage at end points SW place reduces under the effect of resonance current Ir, the electric current I d flowing through capacitor Cd is negative current, if the absolute value of electric current I d is greater than the charging current that current source IS1 provides, then capacitor Cd discharges, and slope signal VHB is reduced to zero gradually.At the end of the voltage slope at end points SW place, electric current I d trends towards zero gradually, and now capacitor Cd charges under the effect of current source IS1, slope signal VHB increases gradually, switching tube S2 conducting on the downside of when slope signal VHB increases to slope threshold value Vd1, switch S 3 turns off, switch S 4 conducting.When downside switching tube S2 conducting, switch S 3 turns off under the control of control signal QH, switch S 4 conducting under the control of control signal QL.Slope signal VHB reduces and maintains low level, when downside switching tube S2 turns off, the voltage at end points SW place raises under the effect of resonance current Ir, the electric current I d flowing through capacitor Cd is positive current, if electric current I d is greater than the discharging current that current source IS2 provides, then capacitor Cd charges, and slope signal VHB increases gradually.At the end of the voltage slope at end points SW place, electric current I d trends towards zero gradually, now capacitor Cd discharges under the effect of current source IS2, slope signal VHB reduces gradually, the side switch pipe S1 conducting when slope signal VHB is decreased to slope threshold value Vd2, switch S 4 turns off, switch S 3 conducting, general Is1=Is2.Flow through electric current I d=Cd*D (the VSW)/D (t) of capacitor Cd, wherein VSW is the voltage at end points SW place.Slope sample circuit 13 produces slope signal VHB under the effect of electric current I d, current source IS1 and current source IS2, and now slope signal VHB reflects the change in voltage at end points SW place.Slope sample circuit 13 also comprises rest-set flip-flop 61 and rest-set flip-flop 62.The set end S reception control signal HG of rest-set flip-flop 61, reset terminal R reception control signal LG, output Q produce control signal QH with the conducting of control switch S3 and shutoff according to control signal HG and control signal LG.The set end S reception control signal LG of rest-set flip-flop 62, reset terminal R reception control signal HG, output Q produce control signal QL with the conducting of control switch S4 and shutoff according to control signal HG and control signal LG.In one embodiment, control signal QL and control signal QH is contrary in phase place.
Fig. 7 for according to Fig. 2 of the utility model embodiment resonance switch convertor 100 adjust the oscillogram of Dead Time when slope signal VHB is effective.In the embodiment shown in fig. 7, when slope signal VHB is effective, Dead Time Circuit tuning 16 controls the turn-on instant of side switch pipe S1 and side switch pipe S2, automatically to adjust the Dead Time between side switch pipe S1 and side switch pipe S2 according to slope signal VHB.
As shown in Figure 7, in the T1 moment, clock signal clk is in trailing edge, control signal HG becomes low level to turn off side switch pipe S1, dead zone function signal ADT becomes low level, control signal QH keeps high level to charge to end points Nd1 to control current source IS1, the VSW of end points SW place voltage declines simultaneously, the electric current I d flowing through capacitor Cd is negative, thus slope signal VHB declines under the effect of electric current I d and current source IS1, wherein the absolute value of electric current I d is greater than the charging current that current source IS1 provides.When detecting that slope signal VHB is decreased to slope threshold value Vx0, judging that slope signal VHB is effective, automatically adjusting Dead Time according to slope signal VHB, control the turn-on instant of side switch pipe S2.Until the T2 moment, voltage VSW is decreased to zero and remains unchanged, and flows through the electric current I d vanishing of capacitor Cd, through certain open Tdl1 time of delay after, side switch pipe S2 is in T3 moment conducting.In the embodiment shown in fig. 7, control to open Tdl1 time of delay according to slope signal VHB.In other embodiments, that also can be fixed by timing circuit generation opens Tdl1 time of delay.In the embodiment shown in fig. 7, increase gradually under the effect of the charging current that slope signal VHB provides at current source IS1, until the T3 moment, when slope signal VHB increases to slope threshold value Vd1, dead zone function signal ADT becomes high level, control signal LG becomes high level with conducting side switch pipe S2, control signal QH becomes low level with shutdown switch S3, control signal QL becomes high level with actuating switch S4, under the effect of the discharging current provided at current source IS2, slope signal VHB keeps low level.From side switch pipe S1 turn off to the Dead Time DT of side switch pipe S2 conducting be T3-T1.In one embodiment, for judging that the whether effective slope threshold value Vx0 of slope signal VHB is less than the slope threshold value Vd1 for controlling side switch pipe S2 turn-on instant.
In the T4 moment, clock signal clk is in rising edge, control signal LG becomes low level to turn off side switch pipe S2, dead zone function signal ADT becomes low level, control signal QL keeps high level to discharge to end points Nd1 to control current source IS2, and simultaneously due to the rising of voltage VSW, the electric current I d flowing through capacitor Cd is just, thus slope signal VHB increases under the effect of electric current I d and current source IS2, wherein electric current I d is greater than the discharging current that current source IS2 provides.When detecting that slope signal VHB increases to slope threshold value Vx1, judging that slope signal VHB is effective, automatically adjusting Dead Time according to slope signal VHB, control the turn-on instant of side switch pipe S1.Until the T5 moment, voltage VSW increases to maximum and remains unchanged, and flows through the electric current I d vanishing of capacitor Cd, through certain open Tdl2 time of delay after, side switch pipe S1 is in T6 moment conducting.In the embodiment shown in fig. 7, control to open Tdl2 time of delay according to slope signal VHB.In other embodiments, that also can be fixed by timing circuit generation opens Tdl2 time of delay.In the embodiment shown in fig. 7, under the effect of the discharging current that slope signal VHB provides at current source IS2, reduce gradually, until the T6 moment, when slope signal VHB is decreased to slope threshold value Vd2, dead zone function signal ADT becomes high level, control signal HG becomes high level with conducting side switch pipe S1, control signal QL becomes low level with shutdown switch S4, control signal QH becomes high level with actuating switch S3, under the effect of the charging current provided at current source IS1, slope signal VHB keeps high level.From side switch pipe S2 turn off to the Dead Time DT of upside switching tube S1 conducting be T6-T4.In one embodiment, for judging that the whether effective slope threshold value Vx1 of slope signal VHB is greater than the slope threshold value Vd2 for controlling side switch pipe S1 turn-on instant.
Fig. 8 for according to Fig. 2 of the utility model embodiment resonance switch convertor 100 adjust the oscillogram of Dead Time when slope signal VHB is invalid.In certain embodiments, when capacitor Cd to open a way because of damage or short circuit time, slope signal VHB can not embody the slope of voltage VSW, and namely slope signal VHB is invalid.The invalid slope signal VHB that such as can show as of slope signal VHB equals zero or equals a fixed voltage value.In the embodiment shown in fig. 8, at rising edge or the trailing edge of clock signal clk, slope signal VHB remains unchanged, Dead Time Circuit tuning 16 controls the turn-on instant of side switch pipe S1 and side switch pipe S2, automatically to adjust the Dead Time between side switch pipe S1 and side switch pipe S2 according to current sampling signal Vcs.
As shown in Figure 8, in the T7 moment, clock signal clk is in rising edge, and control signal LG becomes low level to turn off side switch pipe S2, and dead zone function signal ADT becomes low level, and voltage VSW increases, and current sampling signal Vcs increases.Until the T8 moment, current sampling signal Vcs increases to be greater than current threshold Vth2 from being less than current threshold Vth2, and dead zone function signal ADT becomes high level, and control signal HG becomes high level with conducting side switch pipe S1.From side switch pipe S2 turn off to the Dead Time DT of upside switching tube S1 conducting be T8-T7.In the T9 moment, clock signal clk is in trailing edge, and control signal HG becomes low level to turn off side switch pipe S1, and dead zone function signal ADT becomes low level, and voltage VSW reduces, and current sampling signal Vcs reduces.Until the T10 moment, current sampling signal Vcs is decreased to is less than current threshold Vth1 from being greater than current threshold Vth1, and dead zone function signal ADT becomes high level, and control signal LG becomes high level with conducting side switch pipe S2.The Dead Time DT turning off side switch pipe S2 conducting from side switch pipe S1 is T10-T9.
Although exemplary embodiment describe the utility model with reference to several, should be appreciated that term used illustrates and exemplary and nonrestrictive term.Specifically can implement in a variety of forms due to the utility model and not depart from spirit or the essence of utility model, so be to be understood that, above-described embodiment is not limited to any aforesaid details, and explain widely in the spirit and scope that should limit in claim of enclosing, therefore fall into whole change in claim or its equivalent scope and remodeling and all should be claim of enclosing and contained.
Claims (11)
1., for a control circuit for resonance switch convertor, described resonance switch convertor comprises the switching circuit with side switch pipe and side switch pipe and the resonant groove path being coupled to switching circuit, it is characterized in that, described control circuit comprises:
Slope sample circuit, the change in voltage according to the common port place of side switch pipe and side switch pipe produces slope signal, to characterize the voltage slope at the common port place of side switch pipe and side switch pipe;
Capacitive mode decision circuitry, the on off state according to representing the current sampling signal and side switch pipe and side switch pipe that flow through resonant groove path electric current judges whether switching circuit is operated in capacitive state, and produces mode signal;
Slope decision circuitry, produce slope according to slope signal and judge that signal is to judge that whether slope signal is effective, wherein close at side switch pipe and have no progeny, judge that when detecting that slope signal reduces slope signal is effective, and have no progeny in side switch pipe pass, judge that when detecting that slope signal increases slope signal is effective;
Clock generating circuit, clocking, wherein said control circuit controls the shutoff moment of side switch pipe and the shutoff moment of side switch pipe according to clock signal; And
Turn-on instant control circuit, judge that signal and slope signal regulate the Dead Time between side switch pipe and side switch pipe according to mode signal, slope, wherein when slope signal is effective, control the turn-on instant of side switch pipe according to the comparative result of slope signal and the first slope threshold value, and control the turn-on instant of side switch pipe according to the comparative result of slope signal and the second slope threshold value.
2. control circuit as claimed in claim 1, it is characterized in that, wherein when slope signal is invalid, control the turn-on instant of side switch pipe according to the comparative result of current sampling signal and the first current threshold, and control the turn-on instant of side switch pipe according to the comparative result of current sampling signal and the second current threshold.
3. control circuit as claimed in claim 1, it is characterized in that, wherein slope sample circuit also comprises:
First capacitor, have first end and the second end, wherein first end is coupled to the common port of side switch pipe and side switch pipe, the second end output voltage gradient signal;
First resistor, has first end and the second end, and wherein first end is coupled to the second end of the first capacitor, and the second end is coupled to systematically; And
Voltage control circuit, coupled in parallel is at the two ends of the first resistor, and wherein when the conducting of side switch pipe, voltage control circuit controls slope signal and keeps high level, and when downside switching tube conducting, voltage control circuit controls slope signal and keeps low level.
4. control circuit as claimed in claim 3, it is characterized in that, wherein voltage control circuit also comprises:
First current source, wherein when the conducting of side switch pipe, the first current source provides charging current, until the conducting of side switch pipe for the first resistor; And
Second current source, wherein when downside switching tube conducting, the second current source provides discharging current, until the conducting of side switch pipe for the first resistor.
5. control circuit as claimed in claim 4, it is characterized in that, wherein when side switch pipe turns off, the absolute value flowing through the electric current at the first capacitor two ends is greater than the charging current that the first current source provides, when downside switching tube turns off, the absolute value flowing through the electric current at the first capacitor two ends is greater than the discharging current that the second current source provides.
6. control circuit as claimed in claim 1, it is characterized in that, wherein slope decision circuitry also comprises:
First comparator, there is first input end, the second input and output, wherein first input end receives slope signal, and the second input receives the 3rd slope threshold value, and output exports the first comparison signal according to the comparative result of slope signal and the 3rd slope threshold value;
Second comparator, there is first input end, the second input and output, wherein first input end receives slope signal, and the second input receives the 4th slope threshold value, and output exports the second comparison signal according to the comparative result of slope signal and the 4th slope threshold value; And
First logical circuit, produce slope according to the first comparison signal, the second comparison signal and clock signal and judge signal, wherein after the rising edge of clock signal, produce slope according to the first comparison signal and judge that signal is to judge that whether slope signal is effective, and after the trailing edge of clock signal, produce slope according to the second comparison signal and judge that signal is to judge that whether slope signal effective.
7. control circuit as claimed in claim 1, wherein turn-on instant control circuit comprises:
3rd comparator, has first input end, the second input and output, and wherein first input end receives slope signal, and the second input receives the first slope threshold value, and output exports the 3rd comparison signal;
4th comparator, have first input end, the second input and output, wherein first input end received current sampled signal, the second input receives the first current threshold, and output exports the 4th comparison signal;
5th comparator, has first input end, the second input and output, and wherein first input end receives slope signal, and the second input receives the second slope threshold value, and output exports the 5th comparison signal;
6th comparator, have first input end, the second input and output, wherein first input end received current sampled signal, the second input receives the second current threshold, and output exports the 6th comparison signal;
Second logical circuit, there is first input end, the second input and output, wherein first input end receiving mode signal, the second input receive time-out signal, when mode signal indicator cock circuit working is in capacitive state, timeout signal exports at its output by the second logical circuit;
3rd logical circuit, there is first input end, the second input and output, wherein first input end receiving mode signal, second input receives maximum dead-time signal, when mode signal indicator cock circuit working is in non-capacitive state, maximum dead-time signal exports at its output by the second logical circuit;
First OR circuit, there is first input end, the second input, the 3rd input, four-input terminal and output, wherein first input end is coupled to the output of the 3rd comparator, second input is coupled to the output of the 4th comparator, 3rd input is coupled to the output of the second logical circuit, four-input terminal is coupled to the output of the 3rd logical circuit, and output exports the first reset signal to control the turn-on instant of side switch pipe; And
Second OR circuit, there is first input end, the second input, the 3rd input, four-input terminal and output, wherein first input end is coupled to the output of the 5th comparator, second input is coupled to the output of the 6th comparator, 3rd input is coupled to the output of the second logical circuit, four-input terminal is coupled to the output of the 3rd logical circuit, and output exports the second reset signal to control the turn-on instant of side switch pipe.
8. a resonance switch convertor, is characterized in that, comprising:
Switching circuit, comprises side switch pipe and the side switch pipe of coupled in series;
Resonant groove path, be coupled in side switch pipe and side switch pipe common port and systematically between;
Current sampling circuit, according to the electric current generation current sampled signal flowing through resonant groove path; And
Control circuit as described in claim 1 ~ 7.
9. a resonance switch convertor, is characterized in that, comprising:
Side switch pipe, has first end, the second end and control end, and wherein first end receives input voltage;
Side switch pipe, has first end, the second end and control end, and wherein first end is coupled to the second end of side switch pipe, and the second end is coupled to systematically;
Resonant groove path, be coupled in side switch pipe and side switch pipe common port and systematically between;
Current sampling circuit, according to the electric current generation current sampled signal flowing through resonant groove path;
Slope sample circuit, the change in voltage according to the common port place of side switch pipe and side switch pipe produces slope signal, to characterize the voltage slope at the common port place of side switch pipe and side switch pipe;
Slope decision circuitry, produce slope according to slope signal and judge that signal is to judge that whether slope signal is effective, wherein close at side switch pipe and have no progeny, judge that when detecting that slope signal reduces slope signal is effective, and have no progeny in side switch pipe pass, judge that when detecting that slope signal increases slope signal is effective;
Clock generating circuit, clocking, wherein said control circuit controls the shutoff moment of side switch pipe and the shutoff moment of side switch pipe according to clock signal; And
According to slope, turn-on instant control circuit, judges that signal, current sampling signal and slope signal adjust the Dead Time between side switch pipe and side switch pipe automatically; Wherein
When slope signal is effective, control the turn-on instant of side switch pipe according to the comparative result of slope signal and the first slope threshold value, and control the turn-on instant of side switch pipe according to the comparative result of slope signal and the second slope threshold value; And
When slope signal is invalid, control the turn-on instant of side switch pipe according to the comparative result of current sampling signal and the first current threshold, and control the turn-on instant of side switch pipe according to the comparative result of current sampling signal and the second current threshold.
10. resonance switch convertor as claimed in claim 9, it is characterized in that, wherein slope decision circuitry also comprises:
First comparator, there is first input end, the second input and output, wherein first input end receives slope signal, and the second input receives the 3rd slope threshold value, and output exports the first comparison signal according to the comparative result of slope signal and the 3rd slope threshold value;
Second comparator, there is first input end, the second input and output, wherein first input end receives slope signal, and the second input receives the 4th slope threshold value, and output exports the second comparison signal according to the comparative result of slope signal and the 4th slope threshold value; And
First logical circuit, produce slope according to the first comparison signal, the second comparison signal and clock signal and judge signal, wherein after the rising edge of clock signal, produce slope according to the first comparison signal and judge that signal is to judge that whether slope signal is effective, and after the trailing edge of clock signal, produce slope according to the second comparison signal and judge that signal is to judge that whether slope signal effective.
11. resonance switch convertors as claimed in claim 9, is characterized in that:
Close at side switch pipe and have no progeny, if slope signal is judged as effectively, then when slope signal is less than the first slope threshold value, control the conducting of side switch pipe; And
Close at side switch pipe and have no progeny, if slope signal is judged as effectively, then when slope signal is greater than the second slope threshold value, control the conducting of side switch pipe.
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| CN201420613809.7U CN204089601U (en) | 2014-09-19 | 2014-10-22 | resonant switching converter and control circuit thereof |
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| CN201420542168.0 | 2014-09-19 | ||
| CN201420542168 | 2014-09-19 | ||
| CN201420613809.7U CN204089601U (en) | 2014-09-19 | 2014-10-22 | resonant switching converter and control circuit thereof |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104270008A (en) * | 2014-09-19 | 2015-01-07 | 成都芯源系统有限公司 | Resonant switching converter, control circuit and control method for automatic dead time adjustment of resonant switching converter |
| CN104913713A (en) * | 2015-05-18 | 2015-09-16 | 西安建筑科技大学 | LVDT-based signal conditioning system and method |
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| CN104270008B (en) * | 2014-09-19 | 2017-01-18 | 成都芯源系统有限公司 | Resonant switching converter, control circuit and control method for automatic dead time adjustment of resonant switching converter |
| CN104913713A (en) * | 2015-05-18 | 2015-09-16 | 西安建筑科技大学 | LVDT-based signal conditioning system and method |
| CN108463943A (en) * | 2016-01-12 | 2018-08-28 | 丹麦技术大学 | The resonant power converter with Power MOSFET of circuit of synchronous rectification |
| CN108702086A (en) * | 2016-02-12 | 2018-10-23 | 飞利浦照明控股有限公司 | DC/DC resonance converters and the PFC using resonance converter and corresponding control method |
| CN108923657A (en) * | 2018-07-02 | 2018-11-30 | 杭州茂力半导体技术有限公司 | Controlled resonant converter and its control circuit and control method |
| CN108923657B (en) * | 2018-07-02 | 2020-06-09 | 杭州茂力半导体技术有限公司 | Resonant converter and control circuit and control method thereof |
| CN109980941A (en) * | 2019-03-20 | 2019-07-05 | 深圳市皓文电子有限公司 | The switch control unit and converter of the dcdc converter of LCC resonance |
| CN113452254A (en) * | 2021-05-27 | 2021-09-28 | 华为技术有限公司 | Resonance transformation system and control method |
| CN114825918A (en) * | 2022-04-21 | 2022-07-29 | 晶艺半导体有限公司 | COT control circuit, method and related integrated circuit |
| CN114825918B (en) * | 2022-04-21 | 2024-04-23 | 晶艺半导体有限公司 | COT control circuit, method and related integrated circuit |
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