CN108923660B

CN108923660B - Synchronous rectification converter

Info

Publication number: CN108923660B
Application number: CN201810921202.8A
Authority: CN
Inventors: 尹健; 罗阳; 李海松; 易扬波
Original assignee: Wuxi Xinpeng Microelectronics Co Ltd
Current assignee: Wuxi Xinpeng Microelectronics Co Ltd
Priority date: 2018-08-14
Filing date: 2018-08-14
Publication date: 2020-01-24
Anticipated expiration: 2038-08-14
Also published as: CN108923660A

Abstract

The invention relates to a synchronous rectification converter, which comprises a power circuit and a control circuit, wherein the power circuit comprises a switching MOS (metal oxide semiconductor) tube and a sampling MOS tube, and the control circuit comprises a starting comparator, an adjusting control circuit, a switching-off comparator, a driving circuit and an output line loss compensation circuit capable of carrying out over-temperature protection; the control circuit outputs a driving signal GATE to the power circuit and receives a sampling signal VDET output by the power circuit; the sampling MOS tube accurately samples a source-drain voltage signal VDET of the switching MOS tube, the regulation control circuit generates a regulation signal according to a set regulation point, a driving signal GATE potential is regulated in advance, the turn-off speed of the switching MOS tube is remarkably accelerated, and the reliability of a power supply system applying the synchronous rectification converter is remarkably improved; the bidirectional control of the regulating control circuit finely adjusts the GATE potential, so that the voltage between the source and the drain of the switching MOS tube is stabilized in a small interval, and the working of a front-stage chip is better matched.

Description

Synchronous rectification converter

Technical Field

The invention relates to a synchronous rectification converter, and belongs to the technical field of switching power supplies.

Background

At present, a flyback switching power supply system is widely applied due to the advantages of simple circuit, isolated input and output voltages, low cost, small size and the like, but when the output voltage is low and the output current is large, the conduction loss and the reverse recovery loss of a secondary rectifier diode in the traditional flyback switching power supply system are large, and the efficiency is low. In order to reduce the loss of the rectifier diode, a switch MOS tube with extremely low conduction resistance value is adopted to replace the diode as a rectifier, and the synchronous rectification technology can well improve the conversion efficiency of the whole power supply system.

Referring to fig. 1, in the circuit block diagram of the synchronous rectification converter 100, a high voltage MOS transistor N2 is used as a sampling MOS transistor in the control circuit, and the sampling MOS transistor N2 detects the drain-source voltage of the switching MOS transistor N1, so as to obtain a voltage sampling signal VDET for turning on the comparator 101 and turning off the comparator 102. The turn-on comparator 101 compares the sampling signal VDET with a first threshold V1 to generate a turn-on signal SR _ on; the turn-off comparator 102 compares the sampling signal VDET with the second threshold V2 to generate a turn-off signal SR _ off. The driving circuit 103 receives the turn-on signal SR _ on and the turn-off signal SR _ off, and generates a driving signal GATE to control the switching of the switching MOS transistor N1.

However, synchronous rectifier converters have a number of problems: firstly, due to the structure that the sampling MOS tube and the switch MOS tube are separated, the sampling MOS tube is difficult to accurately detect the voltage change between the drain electrode and the source electrode of the switch MOS tube, and then the synchronous rectification converter cannot be accurately controlled; secondly, when the synchronous rectification converter operates in the continuous conduction mode, the turn-off comparator is difficult to rapidly pull down the potential of the driving signal GATE from a high point, and a direct connection condition exists between the primary and secondary sides, so that the negative current of the secondary side becomes large, and the excessive negative current of the secondary side can cause the damage of a system. Thirdly, when the power system where the synchronous rectification converter is located works under heavy load, a large output current may cause a certain voltage loss on the output line, which may cause the voltage provided to the load end to exceed the specification, and the secondary does not have an over-temperature protection function, and cannot timely protect the power system when the temperature of the working environment is too high.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a synchronous rectification converter.

The purpose of the invention is realized by the following technical scheme:

a synchronous rectification converter comprises a power circuit and a control circuit, and is characterized in that:

the power circuit comprises a switch MOS tube and a sampling MOS tube, and the control circuit comprises a starting comparator, an adjusting control circuit, a switching-off comparator, a driving circuit and an output line loss compensation circuit capable of protecting over temperature;

the drain electrodes of the switching MOS tube and the sampling MOS tube are connected with a high-voltage port;

the grid electrode of the switch MOS tube is connected with the drive circuit and receives the drive signal output by the drive circuit, and the source electrode of the switch MOS tube is connected with the reference ground port;

the grid electrode of the sampling MOS tube is connected with the power supply port, and the source electrode of the sampling MOS tube is connected with the starting comparator, the adjusting control circuit and the switching-off comparator and outputs a sampling signal to the starting comparator, the adjusting control circuit and the switching-off comparator;

the end A of the starting comparator is connected with the first threshold, the end B of the starting comparator is connected with the source electrode of the sampling MOS tube, the sampling MOS tube receives a sampling signal, the starting comparator is connected with the driving circuit, and the starting comparator outputs a starting signal to the driving circuit;

the adjusting controller is connected with the source electrode of the sampling MOS tube, receives the sampling signal, is connected with the driving circuit, and outputs an adjusting pull-up signal and an adjusting pull-down signal to the driving circuit;

the end B of the turn-off comparator is connected with the second threshold, the end A of the turn-off comparator is connected with the source electrode of the sampling MOS tube and receives the sampling signal, and the turn-off comparator is connected with the driving circuit and outputs a turn-off signal to the driving circuit;

the drive circuit is connected with the turn-on comparator, the adjusting control circuit and the turn-off comparator, respectively receives a turn-on signal output by the turn-on comparator, an adjusting pull-up signal output by the adjusting control circuit, an adjusting pull-down signal and a turn-off signal output by the turn-off comparator, is connected with the grid of the switch MOS tube and the output line loss compensation circuit capable of being protected by over temperature, and outputs a drive signal to the grid of the switch MOS tube and the output line loss compensation circuit capable of being protected by over temperature;

the output line loss compensation circuit capable of over-temperature protection is connected with the grid electrode of the switch MOS tube and the driving circuit, receives a driving signal output by the driving circuit and is connected with the compensation port.

Further, in the synchronous rectification converter, the switching MOS transistor and the sampling MOS transistor are integrated on the same silicon chip and have a common substrate structure.

Further, in the synchronous rectification converter, the sampling MOS transistor detects a voltage signal between a source and a drain of the switching MOS transistor, and outputs the sampling signal to the control circuit; the control circuit generates a starting signal, a pull-up adjusting signal, a pull-down adjusting signal and a turn-off signal by processing the sampling signal, adjusts the potential of a driving signal connected to the grid electrode of the switch MOS tube, and controls the on and off of the synchronous rectifier converter.

Further, in the synchronous rectification converter, the regulation control circuit includes an upper sub-circuit and a lower sub-circuit, where the upper sub-circuit includes a first PMOS transistor, a second PMOS transistor, a first NPN transistor, a second NPN transistor, a third NPN transistor, a fourth NPN transistor, a first resistor, a second resistor, a first current source, and a second current source, a source of the first PMOS transistor is connected to the power supply port, and a gate thereof is connected to a drain thereof, a gate of the second PMOS transistor, and a collector of the first NPN transistor;

the source electrode of the second PMOS tube is connected with the power supply port, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the first PMOS tube and the collector electrode of the first NPN tube, and the drain electrode of the second PMOS tube is connected with the collector electrode of the fourth NPN tube and the output end Reg _ off;

the collector of the first NPN tube is connected with the grid of the first PMOS tube, the drain of the first PMOS tube and the grid of the second PMOS tube, the emitter of the first NPN tube is connected with the reference ground port, and the base of the first NPN tube is connected with the base of the second NPN tube, the collector of the second NPN tube and one end of the first resistor;

the base electrode of the second NPN tube is connected with the collector electrode of the second NPN tube, the base electrode of the first NPN tube and one end of the first resistor, and the emitter electrode of the second NPN tube is connected with the input end VDET;

the base electrode of the third NPN tube is connected with one end of the second resistor and the second current source, the collector electrode of the third NPN tube is connected with the other end of the second resistor and the base electrode of the fourth NPN tube, and the emitter electrode of the third NPN tube is connected with the reference ground port;

a base electrode of the fourth NPN tube is connected with a collector electrode of the third NPN tube and one end of the second resistor, a collector electrode of the fourth NPN tube is connected with a drain electrode of the second PMOS tube and the output end Reg _ off, and an emitter electrode of the fourth NPN tube is connected with the input end VDET;

one end of the first resistor is connected with the base electrode of the second NPN tube, the collector electrode of the second NPN tube and the base electrode of the first NPN tube, and the other end of the first resistor is connected with a first current source;

one end of the second resistor is connected with a collector of the third NPN tube and a base of the fourth NPN tube, and the other end of the second resistor is connected with a second current source;

the first current source is connected with one end of the first resistor;

the second current source is connected with one end of the second resistor and the base electrode of the third NPN tube;

the lower sub-circuit comprises a third PMOS (P-channel metal oxide semiconductor) tube, a fourth PMOS tube, a fifth NPN tube, a sixth NPN tube, a seventh NPN tube, an eighth NPN tube, a third resistor, a fourth resistor, a third current source and a fourth current source, wherein the source electrode of the third PMOS tube is connected with the power supply port, and the grid electrode of the third PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the collector electrode of the fifth NPN tube;

the source electrode of the fourth PMOS tube is connected with the power supply port, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, the drain electrode of the third PMOS tube and the collector electrode of the fifth NPN tube, and the drain electrode of the fourth PMOS tube is connected with the collector electrode of the eighth NPN tube and the output end Reg _ on;

a collector of the fifth NPN transistor is connected with a grid electrode of the third PMOS transistor, a drain electrode of the third PMOS transistor and a grid electrode of the fourth PMOS transistor, an emitter of the fifth NPN transistor is connected with an input end VDET, and a base of the fifth NPN transistor is connected with a collector of the sixth NPN transistor and one end of a third resistor;

a base electrode of the sixth NPN tube is connected with one end of the third resistor and the third current source, an emitter electrode of the sixth NPN tube is connected with a reference ground port, and a collector electrode of the sixth NPN tube is connected with the other end of the third resistor and the base electrode of the fifth NPN tube;

the base electrode of the seventh NPN tube is connected with the collector electrode of the seventh NPN tube, the base electrode of the eighth NPN tube and one end of the fourth resistor, and the emitter electrode of the seventh NPN tube is connected with the input end VDET;

the base electrode of the eighth NPN tube is connected with the collector electrode of the seventh NPN tube, the base electrode of the seventh NPN tube and one end of the fourth resistor, the collector electrode of the eighth NPN tube is connected with the drain electrode of the fourth PMOS tube and the output end Reg _ on, and the emitter electrode of the eighth NPN tube is connected with the reference ground port;

one end of the third resistor is connected with a collector of the sixth NPN tube and a base of the fifth NPN tube, and the other end of the third resistor is connected with the base of the sixth NPN tube and a third current source;

one end of the fourth resistor is connected with a collector of the seventh NPN tube, a base of the seventh NPN tube and a base of the eighth NPN tube, and the other end of the fourth resistor is connected with a fourth current source;

the third current source is connected with one end of the third resistor and the base electrode of the sixth NPN tube;

the fourth current source is connected with one end of the fourth resistor.

Further, in the above synchronous rectification converter, for the upper sub-circuit, when the voltage of the input terminal VDET is greater than the set third threshold V3, the output terminal Reg _ off is at a high level, that is, the following relationship is satisfied:

VDET+I1*R1>0

VDET>-I1*R1

the output Reg _ off is high.

Wherein, R1 refers to a first resistor, I1 refers to a first current source, VDET refers to a sampling signal input from an input terminal; defining-I1R 1 as a third threshold V3, wherein the first resistor and the second resistor in the upper sub-circuit are resistors with equal resistance values, and the first current source and the second current source are current sources with equal current values;

for the lower sub-circuit, when the voltage of the input terminal VDET is less than the set fourth threshold V4, the output terminal Reg _ on is at a high level, that is, the following relationship is satisfied:

VDET+I4*R4<0

VDET<-I4*R4

the output end Reg _ on is high potential;

wherein, R4 denotes a fourth resistor, I4 denotes a fourth current source, and VDET denotes a sampling signal input at the input terminal; let-I4 × R4 be defined as a fourth threshold V4, and the third resistor and the fourth resistor in the lower sub-circuit are resistors with equal resistance, and the third current source and the fourth current source are current sources with equal current.

Further, in the synchronous rectification converter, the over-temperature-protection output line loss compensation circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NPN transistor, a first voltage source, a fifth current source, a sixth current source, a seventh current source, and a first not gate;

the source electrode of the fifth PMOS tube is connected with the power supply port, and the grid electrode of the fifth PMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the sixth PMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the fifth NMOS tube;

the grid electrode of the sixth PMOS tube is connected with the grid electrode of the fifth PMOS tube, the drain electrode of the third NMOS tube and the drain electrode of the fifth NMOS tube, the source electrode of the sixth PMOS tube is connected with the power supply port, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the eighth NMOS tube, the grid electrode of the fourth NMOS tube and the input end of the first logical NOT gate;

the grid electrode of the seventh PMOS tube is connected with the base electrode of the ninth NPN tube, the collector electrode of the ninth NPN tube and the fifth current source, the source electrode of the seventh PMOS tube is connected with the sixth current source, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the sixth NMOS tube, the grid electrode of the fifth NMOS tube and the grid electrode of the third NMOS tube;

the grid electrode of the eighth PMOS tube is connected with a first voltage source, the source electrode of the eighth PMOS tube is connected with a sixth current source, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the seventh NMOS tube, the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube;

the grid electrode of the ninth PMOS tube is connected with the output end of the first logic NOT gate and used for receiving the over-temperature protection signal OTP, the source electrode of the ninth PMOS tube is connected with the seventh current source, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube and the output compensation port;

the grid electrode of the third NMOS tube is connected with the grid electrode of the fifth NMOS tube, the grid electrode of the sixth NMOS tube, the drain electrode of the sixth NMOS tube and the drain electrode of the seventh PMOS tube, the drain electrode of the third NMOS tube is connected with the grid electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the sixth PMOS tube and the drain electrode of the fifth NMOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube;

the grid electrode of the fourth NMOS tube is connected with the drain electrode of the sixth PMOS tube, the drain electrode of the eighth NMOS tube and the input end of the first logic NOT gate, the drain electrode of the fourth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the fourth NMOS tube is connected with the reference ground port;

the grid electrode of the fifth NMOS tube is connected with the grid electrode of the third NMOS tube, the drain electrode of the sixth NMOS tube, the grid electrode of the sixth NMOS tube and the drain electrode of the seventh PMOS tube, the drain electrode of the fifth NMOS tube is connected with the grid electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the sixth PMOS tube and the drain electrode of the third NMOS tube, and the source electrode of the fifth NMOS tube is connected with the reference ground port;

the grid electrode of the sixth NMOS tube is connected with the drain electrode of the sixth NMOS tube, the grid electrode of the fifth NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the seventh PMOS tube, and the source electrode of the sixth NMOS tube is connected with the reference ground port;

the grid electrode of the seventh NMOS tube is connected with the drain electrode of the seventh NMOS tube, the grid electrode of the eighth NMOS tube and the drain electrode of the eighth PMOS tube, and the source electrode of the seventh NMOS tube is connected with the reference ground port;

the grid electrode of the eighth NMOS tube is connected with the grid electrode of the seventh NMOS tube, the drain electrode of the seventh NMOS tube and the drain electrode of the eighth PMOS tube, the drain electrode of the eighth NMOS tube is connected with the drain electrode of the sixth PMOS tube, the grid electrode of the fourth NMOS tube and the input end of the first logical NOT gate, and the source electrode of the eighth NMOS tube is connected with the reference ground port;

the grid electrode of the ninth NMOS tube is connected with the input end GATE, the drain electrode of the ninth NMOS tube is connected with the output compensation port and the drain electrode of the ninth PMOS tube, and the source electrode of the ninth NMOS tube is connected with the reference ground port;

the base electrode of the ninth NPN tube is connected with the collector electrode of the ninth NPN tube, the fifth current source and the grid electrode of the seventh PMOS tube, and the emitting electrode of the ninth NPN tube is connected with the port of the reference ground;

the first voltage source is connected with the grid electrode of the eighth PMOS tube;

the fifth current source is connected with the base electrode of the ninth NPN tube, the collector electrode of the ninth NPN tube and the grid electrode of the seventh PMOS tube;

the sixth current source is connected with the source electrode of the seventh PMOS tube and the source electrode of the eighth PMOS tube;

the seventh current source is connected with the source electrode of the ninth PMOS tube;

the input end of the first logic not gate is connected with the drain electrode of the sixth PMOS tube, the grid electrode of the fourth NMOS tube and the drain electrode of the eighth NMOS tube, the output end of the first logic not gate is connected with the grid electrode of the ninth PMOS tube, and the over-temperature protection signal OTP is transmitted to the grid electrode of the ninth PMOS tube.

Further, in the synchronous rectification converter, when the input driving signal GATE is high, the ninth NMOS transistor is turned on, a current Icomp flows from the compensation port, and the output line loss compensation is realized by the current;

the grid electrode of the seventh PMOS tube is connected with the base electrode and the collector electrode of the ninth NPN tube, the grid electrode of the eighth PMOS tube is connected with the first voltage source, the junction voltage drop VBE between the base electrode and the emitter of the ninth NPN tube is a negative temperature coefficient, and when the temperature of the working environment of the chip is too high, at the moment:

VBE<V1

the over-temperature protection signal OTP is low;

VBE refers to a junction voltage drop between the base and the emitter of the ninth NPN transistor, and V1 refers to the first voltage source;

when the over-temperature protection signal OTP is low, the ninth PMOS tube is conducted, a current Icomp flows out from the compensation port, and the over-temperature protection is realized by using the current.

Compared with the prior art, the invention has obvious advantages and beneficial effects, and is embodied in the following aspects:

① A switching MOS tube and a sampling MOS tube in the power circuit of the synchronous rectification converter are integrated on the same silicon chip and are of a common substrate structure;

② the adjusting control circuit of the synchronous rectification converter adjusts the GATE electric potential of the driving signal in advance at the set adjusting point according to the accurate voltage sampling signal, which can accelerate the turn-off speed of the switch MOS tube, and the reliability of the power system applying the synchronous rectification converter is improved obviously, meanwhile, the bidirectional control of the adjusting control circuit can finely adjust the GATE electric potential, so that the voltage between the source and the drain of the switch MOS tube is stabilized in a small interval, and the operation of the front chip is better matched.

③ the synchronous rectification converter is added with a COMP port, the output line compensation circuit with over-temperature protection can realize the output line loss compensation function by using the COMP port, improve the influence of the output line loss difference on the consistency of the output voltage under different loads, and meanwhile, the output line compensation circuit has the over-temperature protection function, when the working environment temperature is detected to be too high, the over-temperature protection can be realized by using the COMP port, and the power supply system is protected in time.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

FIG. 1: a circuit block diagram of a synchronous rectification converter of the background art;

FIG. 2: the invention relates to a circuit block diagram of a synchronous rectification converter;

FIG. 3: the structure schematic diagram of the regulation control circuit of the invention;

FIG. 4: the working waveform diagram of the synchronous rectification converter of the invention;

FIG. 5: the invention discloses a structure schematic diagram of an output line loss compensation circuit capable of over-temperature protection;

FIG. 6: the synchronous rectification converter of the invention realizes the work oscillogram of the output line loss compensation and the over-temperature protection function.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the directional terms and the sequence terms, etc. are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

As shown in fig. 2, a synchronous rectification converter includes a power circuit and a control circuit,

the power circuit comprises a switch MOS tube N1 and a sampling MOS tube N2, and the control circuit comprises a starting comparator 201, an adjusting control circuit 202, a switching-off comparator 203, a driving circuit 204 and an output line loss compensation circuit 205 capable of protecting over temperature;

the drains of the switching MOS tube N1 and the sampling MOS tube N2 are connected with the high-voltage port SW;

the GATE of the switching MOS transistor N1 is connected to the driving circuit 204, and receives the driving signal GATE output by the driving circuit, and the source of the switching MOS transistor N1 is connected to the ground reference port GND;

the grid electrode of the sampling MOS tube N2 is connected with a power supply port VCC, and the source electrode of the sampling MOS tube N2 is connected with the turn-on comparator 201, the regulation control circuit 202 and the turn-off comparator 203 and outputs a sampling signal VDET to the turn-on comparator 201, the regulation control circuit 202 and the turn-off comparator 203;

the end A of the turn-on comparator 201 is connected with the first threshold V1, the end B of the turn-on comparator is connected with the source electrode of the sampling MOS tube N2, the turn-on comparator 201 is connected with the drive circuit 204 and outputs a turn-on signal SR _ on to the drive circuit 204, and the sampling signal VDET is received;

the adjusting controller 202 is connected with the source electrode of the sampling MOS transistor N2, receives the sampling signal VDET, is connected with the driving circuit 204, and outputs an adjusting pull-up signal Reg _ on and an adjusting pull-down signal Reg _ off to the driving circuit 204;

the terminal B of the turn-off comparator 203 is connected to the second threshold V2, the terminal a thereof is connected to the source of the sampling MOS transistor N2, receives the sampling signal VDET, and the turn-off comparator 203 is connected to the driving circuit 204, and outputs a turn-off signal SR _ off to the driving circuit 204;

the driving circuit 204 is connected to the on comparator 201, the regulation control circuit 202 and the off comparator 203, receives the on signal SR _ on output by the on comparator 201, the regulation pull-up signal Reg _ on output by the regulation control circuit 202, the regulation pull-down signal Reg _ off and the off signal SR _ off output by the off comparator 203, is connected to the GATE of the switch MOS transistor N1 and the output line loss compensation circuit 205 capable of over-temperature protection, and outputs the driving signal GATE to the GATE of the switch MOS transistor N1 and the output line loss compensation circuit 205 capable of over-temperature protection;

the output line loss compensation circuit 205 capable of over-temperature protection is connected to the GATE of the switching MOS transistor N1 and the driving circuit 204, receives the driving signal GATE output by the driving circuit 204, and is connected to the compensation port COMP.

The switching MOS tube N1 and the sampling MOS tube N2 are integrated on the same silicon chip and have a common substrate structure.

The sampling MOS tube N2 detects a voltage signal between the source and the drain of the switching MOS tube N1 and outputs a sampling signal VDET to the control circuit; the control circuit generates an on signal SR _ on, a pull-up adjusting signal Reg _ on, a pull-down adjusting signal Reg _ off and an off signal SR _ off by processing the sampling signal VDET, adjusts the potential of a driving signal GATE connected to the grid electrode of the switch MOS tube N1, and controls the on and off of the synchronous rectifier converter.

As shown in fig. 3, the regulation control circuit 202 includes an upper sub-circuit and a lower sub-circuit, wherein the upper sub-circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a fourth NPN transistor Q4, a first resistor R1, a second resistor R2, a first current source I1, and a second current source I2, a source of the first PMOS transistor P1 is connected to the power supply port VCC, and a gate thereof is connected to a drain of the first PMOS transistor P2, a gate of the second PMOS transistor P2, and a collector of the first NPN transistor Q1;

the source electrode of the second PMOS transistor P2 is connected to the power supply port VCC, the gate electrode thereof is connected to the gate electrode of the first PMOS transistor P1, the drain electrode of the first PMOS transistor P1 and the collector electrode of the first NPN transistor Q1, and the drain electrode thereof is connected to the collector electrode of the fourth NPN transistor Q4 and the output terminal Reg _ off;

a collector of the first NPN transistor Q1 is connected to the gate of the first PMOS transistor P1, the drain of the first PMOS transistor P1, and the gate of the second PMOS transistor P2, an emitter thereof is connected to the ground reference port GND, and a base thereof is connected to the base of the second NPN transistor Q2, the collector of the second NPN transistor Q2, and one end of the first resistor R1;

the base of the second NPN transistor Q2 is connected to the collector thereof, the base of the first NPN transistor Q1 and one end of the first resistor R1, and the emitter thereof is connected to the input terminal VDET;

a base electrode of the third NPN transistor Q3 is connected to one end of the second resistor R2 and the second current source I2, a collector electrode thereof is connected to the other end of the second resistor R2 and a base electrode of the fourth NPN transistor Q4, and an emitter electrode thereof is connected to the ground reference port GND;

a base electrode of the fourth NPN transistor Q4 is connected to a collector electrode of the third NPN transistor Q3 and one end of the second resistor R2, a collector electrode thereof is connected to a drain electrode of the second PMOS transistor P2 and the output terminal Reg _ off, and an emitter electrode thereof is connected to the input terminal VDET;

one end of the first resistor R1 is connected with the base of the second NPN transistor Q2, the collector of the second NPN transistor Q2 and the base of the first NPN transistor Q1, and the other end of the first resistor R1 is connected with the first current source I1;

one end of the second resistor R2 is connected with the collector of the third NPN transistor Q3 and the base of the fourth NPN transistor Q4, and the other end of the second resistor R2 is connected with the second current source I2;

the first current source I1 is connected with one end of a first resistor R1;

the second current source I2 is connected with one end of the second resistor R2 and the base of the third NPN transistor Q3;

the lower sub-circuit comprises a third PMOS tube P3, a fourth PMOS tube P4, a fifth NPN tube Q5, a sixth NPN tube Q6, a seventh NPN tube Q7, an eighth NPN tube Q8, a third resistor R3, a fourth resistor R4, a third current source I3 and a fourth current source I4, wherein the source electrode of the third PMOS tube P3 is connected with a power supply port VCC, and the grid electrode of the third PMOS tube P3 is connected with the drain electrode of the third PMOS tube P4, the grid electrode of the fourth PMOS tube P4 and the collector electrode of the fifth NPN tube Q5;

the source electrode of the fourth PMOS transistor P4 is connected to the power supply port VCC, the gate electrode thereof is connected to the gate electrode of the third PMOS transistor P3, the drain electrode of the third PMOS transistor P3 and the collector electrode of the fifth NPN transistor Q5, and the drain electrode thereof is connected to the collector electrode of the eighth NPN transistor Q8 and the output terminal Reg _ on;

a collector of the fifth NPN transistor Q5 is connected to the gate of the third PMOS transistor P3, the drain of the third PMOS transistor P3, and the gate of the fourth PMOS transistor P4, an emitter thereof is connected to the input terminal VDET, and a base thereof is connected to the collector of the sixth NPN transistor Q6 and one end of the third resistor R3;

a base electrode of the sixth NPN transistor Q6 is connected to one end of the third resistor R3 and the third current source I3, an emitter electrode thereof is connected to the ground reference port GND, and a collector electrode thereof is connected to the other end of the third resistor R3 and a base electrode of the fifth NPN transistor Q5;

the base of the seventh NPN transistor Q7 is connected to the collector thereof, the base of the eighth NPN transistor Q8 and one end of the fourth resistor R4, and the emitter thereof is connected to the input terminal VDET;

the base electrode of the eighth NPN transistor Q8 is connected to the collector electrode of the seventh NPN transistor Q7, the base electrode of the seventh NPN transistor Q7 and one end of the fourth resistor R4, the collector electrode thereof is connected to the drain electrode of the fourth PMOS transistor P4 and the output terminal Reg _ on, and the emitter electrode thereof is connected to the ground reference port GND;

one end of the third resistor R3 is connected to the collector of the sixth NPN transistor Q6 and the base of the fifth NPN transistor Q5, and the other end of the third resistor R3 is connected to the base of the sixth NPN transistor Q6 and the third current source I3;

one end of the fourth resistor R4 is connected to the collector of the seventh NPN transistor Q7, the base of the seventh NPN transistor Q7, and the base of the eighth NPN transistor Q8, and the other end of the fourth resistor R4 is connected to the fourth current source I4;

the third current source I3 is connected with one end of the third resistor R3 and the base of the sixth NPN transistor Q6;

the fourth current source I4 is connected to one end of the fourth resistor R4.

For the upper sub-circuit, when the voltage of the input terminal VDET is greater than the set third threshold V3, the output terminal Reg _ off is high, that is, the following relationship is satisfied:

VDET+I1*R1>0

VDET>-I1*R1

the output Reg _ off is high.

Wherein, R1 refers to a first resistor, I1 refers to a first current source, VDET refers to a sampling signal input from an input terminal; defining-I1 × R1 as a third threshold V3, wherein the first resistor R1 and the second resistor R2 in the upper sub-circuit are resistors with equal resistance, and the first current source I1 and the second current source I2 are current sources with equal current;

VDET+I4*R4<0

VDET<-I4*R4

the output end Reg _ on is high potential;

wherein, R4 denotes a fourth resistor, I4 denotes a fourth current source, and VDET denotes a sampling signal input at the input terminal; let-I4 × R4 be defined as the fourth threshold V4, and the third resistor R3 and the fourth resistor R4 in the lower sub-circuit are resistors with equal resistance, and the third current source I3 and the fourth current source I4 are current sources with equal current.

As shown in fig. 4, the working waveform of the synchronous rectification converter of the present invention has the following specific working mechanism:

the sampling MOS transistor N2 precisely samples the voltage signal VDET between the source and the drain of the switching MOS transistor N1, and transmits the sampled voltage signal VDET to the on comparator 201, the adjustment control circuit 202, and the off comparator 203.

At the time t0, when the voltage of the sampling signal VDET decreases to be less than the first threshold V1, the turn-on signal SR _ on output by the turn-on comparator 201 is high, and at this time, the driving circuit 204 is pulled high rapidly to receive the driving signal GATE of the switching MOS transistor N1.

In the period from t0 to t1, when the switching MOS transistor N1 is turned on, the secondary current Ids flows through the switching MOS transistor N1, and the voltage of the sampling signal VDET starts to rise.

When the voltage of the sampling signal VDET rises above the third threshold V3 corresponding to time t1, the regulation pull-down signal Reg _ off output by the regulation control circuit 202 is high, and the driving circuit 204 pulls down the driving signal GATE connected to the GATE of the switching MOS transistor N1.

In a period from t1 to t2, when the driving signal GATE of the switching MOS transistor N1 is pulled low, the voltage of the sampling signal VDET decreases slowly, and when the voltage of the sampling signal VDET decreases to be less than the fourth threshold V4, the regulation pull-up signal Reg _ on output by the regulation control circuit 202 is high, and at this time, the driving circuit 204 pulls high the driving signal GATE connected to the GATE of the switching MOS transistor N1, and the voltage of the sampling signal VDET decreases slowly. During this period, the drive signal GATE is repeatedly pulled down and pulled up, and the voltage of the sampling signal VDET is maintained between the third threshold V3 and the fourth threshold V4. Adjusting the bidirectional control signal generated by the control circuit: the GATE potential can be finely adjusted by adjusting the pull-up signal Reg _ on and the pull-down signal Reg _ off, so that the voltage between the source and the drain of the switching MOS tube is stabilized in a small interval, and the operation of a front-stage chip is better matched.

At the time t2, if the synchronous rectification converter operates in the continuous conduction mode, at this time, the falling slope of the secondary current Ids flowing through the switching MOS transistor N1 changes abruptly, the voltage of the sampling signal VDET also changes abruptly, when the voltage of the sampling signal VDET rises to be greater than the second threshold V2, the turn-off signal SR _ off output by the turn-off comparator 203 is high, and at this time, the driving circuit 204 rapidly pulls down the driving signal GATE connected to the GATE of the switching MOS transistor N1. Because the driving signal GATE is adjusted in the period from t1 to t2, the electric potential of the driving signal GATE is lower, the driving circuit 204 can rapidly pull down the driving signal GATE after receiving the high off signal SR _ off, and the secondary current Ids is not reversed or the reverse current is very small, so that the reliability of the system operation is improved.

As shown in fig. 5, the over-temperature protection output line loss compensation circuit 205 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a ninth NPN transistor Q9, a first voltage source V1, a fifth current source I5, a sixth current source I6, a seventh current source I7, and a first logic not gate M1;

the source electrode of the fifth PMOS tube P5 is connected with a power supply port VCC, and the grid electrode of the fifth PMOS tube P5 is connected with the drain electrode of the fifth PMOS tube P6, the grid electrode of the sixth PMOS tube P3526, the drain electrode of the third NMOS tube N3 and the drain electrode of the fifth NMOS tube N5;

the grid electrode of the sixth PMOS tube P6 is connected with the grid electrode of the fifth PMOS tube P5, the drain electrode of the fifth PMOS tube P5, the drain electrode of the third NMOS tube N3 and the drain electrode of the fifth NMOS tube N5, the source electrode of the sixth PMOS tube P6 is connected with the power supply port VCC, and the drain electrode of the sixth PMOS tube P3578 is connected with the drain electrode of the eighth NMOS tube N8, the grid electrode of the fourth NMOS tube N4 and the input end of the first logical NOT gate M1;

the gate of the seventh PMOS transistor P7 is connected to the base of the ninth NPN transistor Q9, the collector of the ninth NPN transistor Q9, and the fifth current source I5, the source thereof is connected to the sixth current source I6, the drain thereof is connected to the drain of the sixth NMOS transistor N6, the gate of the sixth NMOS transistor N6, the gate of the fifth NMOS transistor N5, and the gate of the third NMOS transistor N3;

the gate of the eighth PMOS transistor P8 is connected to the first voltage source V1, the source thereof is connected to the sixth current source I6, and the drain thereof is connected to the drain of the seventh NMOS transistor N7, the gate of the seventh NMOS transistor N7 and the gate of the eighth NMOS transistor N8;

the gate of the ninth PMOS transistor P9 is connected to the output terminal of the first nor gate M1, receives the over-temperature protection signal OTP, the source thereof is connected to the seventh current source I7, and the drain thereof is connected to the drain of the ninth NMOS transistor N9 and the output compensation port COMP;

the grid electrode of the third NMOS tube N3 is connected with the grid electrode of the fifth NMOS tube N5, the grid electrode of the sixth NMOS tube N6, the drain electrode of the sixth NMOS tube N6 and the drain electrode of the seventh PMOS tube P7, the drain electrode of the third NMOS tube N3 is connected with the grid electrode of the fifth PMOS tube P5, the drain electrode of the fifth PMOS tube P5, the grid electrode of the sixth PMOS tube P6 and the drain electrode of the fifth NMOS tube N5, and the source electrode of the third NMOS tube N3 is connected with the drain electrode of the fourth NMOS tube N4;

the grid electrode of the fourth NMOS tube N4 is connected with the drain electrode of the sixth PMOS tube P6, the drain electrode of the eighth NMOS tube N8 and the input end of the first logical NOT gate M1, the drain electrode of the fourth NMOS tube N4 is connected with the source electrode of the third NMOS tube N3, and the source electrode of the fourth NMOS tube N4 is connected with the ground reference port GND;

the grid electrode of the fifth NMOS tube N5 is connected with the grid electrode of the third NMOS tube N3, the drain electrode of the sixth NMOS tube N6, the grid electrode of the sixth NMOS tube N6 and the drain electrode of the seventh PMOS tube P7, the drain electrode of the fifth NMOS tube P5, the drain electrode of the fifth PMOS tube P5, the grid electrode of the sixth PMOS tube P6 and the drain electrode of the third NMOS tube N3, and the source electrode of the fifth NMOS tube N5 is connected with the ground reference port GND;

the grid electrode of the sixth NMOS tube N6 is connected with the drain electrode of the sixth NMOS tube N6, the grid electrode of the fifth NMOS tube N5, the grid electrode of the third NMOS tube N3 and the drain electrode of the seventh PMOS tube P7, and the source electrode of the sixth NMOS tube N6 is connected with the ground reference port GND;

the grid electrode of the seventh NMOS tube N7 is connected with the drain electrode of the seventh NMOS tube N7, the grid electrode of the eighth NMOS tube N8 and the drain electrode of the eighth PMOS tube P8, and the source electrode of the seventh NMOS tube N7 is connected with the ground reference port GND;

the grid electrode of the eighth NMOS tube N8 is connected with the grid electrode of the seventh NMOS tube N7, the drain electrode of the seventh NMOS tube N7 and the drain electrode of the eighth PMOS tube P8, the drain electrode of the eighth NMOS tube N8 is connected with the drain electrode of the sixth PMOS tube P6, the grid electrode of the fourth NMOS tube N4 and the input end of the first logical NOT gate M1, and the source electrode of the eighth NMOS tube N8 is connected with the ground reference port GND;

the grid electrode of the ninth NMOS tube N9 is connected with the input end GATE, the drain electrode of the ninth NMOS tube N9 is connected with the output compensation port COMP and the drain electrode of the ninth PMOS tube P9, and the source electrode of the ninth NMOS tube N9 is connected with the ground reference port GND;

the base electrode of the ninth NPN transistor Q9 is connected to the collector electrode thereof, the fifth current source I5 and the gate electrode of the seventh PMOS transistor P7, and the emitter electrode thereof is connected to the ground reference port GND;

the first voltage source V1 is connected with the gate of the eighth PMOS tube P8;

a fifth current source I5) is connected to the base of the ninth NPN transistor Q9, the collector of the ninth NPN transistor Q9 and the gate of the seventh PMOS transistor P7;

the sixth current source I6 is connected with the source electrode of the seventh PMOS tube P7 and the source electrode of the eighth PMOS tube P8;

the seventh current source I7 is connected with the source electrode of the ninth PMOS tube P9;

the input end of the first logic not gate M1 is connected to the drain of the sixth PMOS transistor P6, the gate of the fourth NMOS transistor N4, and the drain of the eighth NMOS transistor N8, and the output end thereof is connected to the gate of the ninth PMOS transistor P9, and transmits the over-temperature protection signal OTP to the gate of the ninth PMOS transistor P9.

When the input driving signal GATE is high, the ninth NMOS transistor N9 is turned on, a current Icomp flows from the compensation port COMP, and output line loss compensation is implemented by using the current;

the gate of the seventh PMOS transistor P7 is connected to the base and collector of the ninth NPN transistor Q9, the gate of the eighth PMOS transistor P8 is connected to the first voltage source V1, and the junction drop VBE between the base and emitter of the ninth NPN transistor Q9 is a negative temperature coefficient, when the temperature of the working environment of the chip is too high, at this time:

VBE<V1

the over-temperature protection signal OTP is low;

VBE refers to a junction voltage drop between the base and the emitter of the ninth NPN transistor Q9, and V1 refers to a first voltage source;

when the over-temperature protection signal OTP is low, the ninth PMOS transistor P9 is turned on, a current Icomp flows out from the compensation port COMP, and the over-temperature protection is realized by using the current.

As shown in fig. 6, the working waveform diagram of the synchronous rectification converter of the present invention for realizing the output line loss compensation and the over-temperature protection function has the following specific working mechanism:

the output line loss compensation circuit 205 capable of over-temperature protection receives the driving signal GATE input by the driving circuit 204, and the difference between the on duration and the off duration of the GATE may reflect the weight of the load at this time, and at this time, a corresponding current Icomp flows into the compensation COMP port, and the current is an average current.

Corresponding to the period from t0 to t1, the load is judged to be lighter at the moment according to the on and off duration of GATE, the current Icomp1 flows into the compensation COMP port at the moment, the voltage Vout (solid line) of the output end is finely adjusted to Vo1, and the voltage at the line end is basically stabilized near the voltage Vo (dotted line).

Corresponding to the time period from t1 to t2, according to the on-off duration of GATE, judging that the load is heavier relative to the time period from t0 to t1, the current Icomp2 flows into the compensation COMP port at the time, the voltage Vout (solid line) of the output end is finely adjusted to Vo2, and the voltage of the line end is basically stabilized near the voltage Vo (dotted line).

Corresponding to the time period from t2 to t3, according to the on-off duration of GATE, judging that the load is further increased relative to the time period from t1 to t2, the current Icomp3 flows into the compensation COMP port at the time, the voltage Vout (solid line) of the output end is finely adjusted to Vo3, and the voltage at the line end is basically stabilized near the voltage Vo (dotted line).

At the time t3, the over-temperature protection output line loss compensation circuit 205 detects that the working temperature of the chip is too high, at this time, the compensation COMP port flows out current Icomp4, the voltage Vout (solid line) of the output end is adjusted to Vo4, the output power of the power supply system is reduced, the temperature is reduced, and then the over-temperature protection is realized.

In summary, the control circuit of the present invention outputs the driving signal GATE to the power circuit, and receives the sampling signal VDET output by the power circuit; the sampling MOS tube of the synchronous rectification converter can accurately sample a voltage signal VDET between the source and the drain of the switching MOS tube, the regulation control circuit generates a regulation signal according to a set regulation point, the GATE potential of a driving signal is regulated in advance, the turn-off speed of the switching MOS tube is remarkably accelerated, and the reliability of a power supply system applying the synchronous rectification converter is remarkably improved; the bidirectional control of the regulating control circuit can finely regulate the GATE potential, so that the voltage between the source and the drain of the switching MOS tube is stabilized in a very small interval, and the bidirectional control circuit is better matched with the work of a front-stage chip; meanwhile, the synchronous rectification converter is additionally provided with a compensation port COMP, so that the output line loss compensation function with over-temperature protection can be realized.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and shall be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Claims

1. A synchronous rectifier converter comprising a power circuit and a control circuit, characterized in that:

the power circuit comprises a switching MOS (N1) and a sampling MOS (N2), and the control circuit comprises a starting comparator (201), an adjusting control circuit (202), a switching-off comparator (203), a driving circuit (204) and an output line loss compensation circuit (205) capable of protecting over-temperature;

the drains of the switching MOS tube (N1) and the sampling MOS tube (N2) are connected with a high-voltage port (SW);

the grid electrode of the switch MOS tube (N1) is connected with the drive circuit (204) and receives the drive signal (GATE) output by the drive circuit, and the source electrode of the switch MOS tube (N1) is connected with the ground reference port (GND);

the grid electrode of the sampling MOS tube (N2) is connected with a power supply port (VCC), and the source electrode of the sampling MOS tube (N2) is connected with the turn-on comparator (201), the regulation control circuit (202) and the turn-off comparator (203) to output a sampling signal (VDET) to the turn-on comparator;

the A end of the starting comparator (201) is connected with a first threshold (V1), the B end of the starting comparator (201) is connected with the source electrode of the sampling MOS tube (N2), the sampling MOS tube receives a sampling signal (VDET), the starting comparator (201) is connected with the driving circuit (204), and a starting signal (SR _ on) is output to the driving circuit (204);

the adjusting controller (202) is connected with the source electrode of the sampling MOS tube (N2), receives a sampling signal (VDET), is connected with the driving circuit (204), and outputs an adjusting pull-up signal (Reg _ on) and an adjusting pull-down signal (Reg _ off) to the driving circuit (204);

the terminal B of the turn-off comparator (203) is connected with a second threshold (V2), the terminal A of the turn-off comparator is connected with the source electrode of the sampling MOS tube (N2) and receives a sampling signal (VDET), the turn-off comparator (203) is connected with the driving circuit (204) and outputs a turn-off signal (SR _ off) to the driving circuit (204);

the driving circuit (204) is connected with the turn-on comparator (201), the regulation control circuit (202) and the turn-off comparator (203), respectively receives a turn-on signal (SR _ on) output by the turn-on comparator (201), a regulation pull-up signal (Reg _ on) and a regulation pull-down signal (Reg _ off) output by the regulation control circuit (202), and a turn-off signal (SR _ off) output by the turn-off comparator (203), is connected with the GATE of the switch MOS transistor (N1) and the output line loss compensation circuit (205) capable of over-temperature protection, and outputs a driving signal (GATE) to the GATE of the switch MOS transistor (N1) and the output line loss compensation circuit (205) capable of over-temperature protection;

the over-temperature protection output line loss compensation circuit (205) is connected with the grid of the switch MOS (N1) and the drive circuit (204), receives a drive signal (GATE) output by the drive circuit (204), and is connected with an output compensation port (COMP);

the adjusting control circuit (202) comprises an upper sub-circuit and a lower sub-circuit, wherein the upper sub-circuit comprises a first PMOS (P1), a second PMOS (P2), a first NPN (Q1), a second NPN (Q2), a third NPN (Q3), a fourth NPN (Q4), a first resistor (R1), a second resistor (R2), a first current source (I1) and a second current source (I2), the source of the first PMOS (P1) is connected with a power supply port (VCC), and the gate of the first PMOS is connected with the drain of the first PMOS, the gate of the second PMOS (P2) and the collector of the first NPN (Q1);

the source electrode of the second PMOS tube (P2) is connected with a power supply port (VCC), the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube (P1), the drain electrode of the first PMOS tube (P1) and the collector electrode of the first NPN tube (Q1), and the drain electrode of the second PMOS tube is connected with the collector electrode of the fourth NPN tube (Q4) and the output end Reg _ off;

a collector of the first NPN tube (Q1) is connected with a grid of the first PMOS tube (P1), a drain of the first PMOS tube (P1) and a grid of the second PMOS tube (P2), an emitter of the first NPN tube (Q1) is connected with a reference ground port (GND), a base of the first NPN tube (Q2) is connected with a base of the second NPN tube (Q2), and one end of the first resistor (R1);

the base electrode of the second NPN tube (Q2) is connected with the collector electrode of the second NPN tube, the base electrode of the first NPN tube (Q1) and one end of the first resistor (R1), and the emitter electrode of the second NPN tube is connected with the sampling signal (VDET);

a base electrode of the third NPN tube (Q3) is connected with one end of the second resistor (R2) and the second current source (I2), a collector electrode of the third NPN tube is connected with the other end of the second resistor (R2) and a base electrode of the fourth NPN tube (Q4), and an emitter electrode of the third NPN tube is connected with a reference ground port (GND);

the base electrode of the fourth NPN tube (Q4) is connected with the collector electrode of the third NPN tube (Q3) and one end of the second resistor (R2), the collector electrode of the fourth NPN tube is connected with the drain electrode of the second PMOS tube (P2) and the output end Reg _ off, and the emitter electrode of the fourth NPN tube is connected with the sampling signal (VDET);

one end of the first resistor (R1) is connected with the base electrode of the second NPN tube (Q2), the collector electrode of the second NPN tube (Q2) and the base electrode of the first NPN tube (Q1), and the other end of the first resistor (R1) is connected with a first current source (I1);

one end of the second resistor (R2) is connected with the collector of the third NPN tube (Q3) and the base of the fourth NPN tube (Q4), and the other end of the second resistor (R2) is connected with the second current source (I2);

the first current source (I1) is connected with one end of the first resistor (R1);

the second current source (I2) is connected with one end of the second resistor (R2) and the base electrode of the third NPN tube (Q3);

the lower sub-circuit comprises a third PMOS (P3), a fourth PMOS (P4), a fifth NPN (Q5), a sixth NPN (Q6), a seventh NPN (Q7), an eighth NPN (Q8), a third resistor (R3), a fourth resistor (R4), a third current source (I3) and a fourth current source (I4), wherein the source electrode of the third PMOS (P3) is connected with a power supply port (VCC), and the gate electrode of the third PMOS is connected with the drain electrode of the third PMOS, the gate electrode of the fourth PMOS (P4) and the collector electrode of the fifth NPN (Q5);

the source electrode of the fourth PMOS tube (P4) is connected with the power supply port (VCC), the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube (P3), the drain electrode of the third PMOS tube (P3) and the collector electrode of the fifth NPN tube (Q5), and the drain electrode of the fourth PMOS tube is connected with the collector electrode of the eighth NPN tube (Q8) and the output end Reg _ on;

a collector of the fifth NPN transistor (Q5) is connected with a gate of the third PMOS transistor (P3), a drain of the third PMOS transistor (P3) and a gate of the fourth PMOS transistor (P4), an emitter of the fifth NPN transistor is connected with a sampling signal (VDET), and a base of the fifth NPN transistor is connected with a collector of the sixth NPN transistor (Q6) and one end of the third resistor (R3);

a base electrode of the sixth NPN tube (Q6) is connected with one end of the third resistor (R3) and the third current source (I3), an emitter electrode of the sixth NPN tube is connected with the ground reference port (GND), and a collector electrode of the sixth NPN tube is connected with the other end of the third resistor (R3) and the base electrode of the fifth NPN tube (Q5);

the base electrode of the seventh NPN tube (Q7) is connected with the collector electrode of the seventh NPN tube, the base electrode of the eighth NPN tube (Q8) and one end of a fourth resistor (R4), and the emitter electrode of the seventh NPN tube is connected with the sampling signal (VDET);

the base electrode of the eighth NPN tube (Q8) is connected with the collector electrode of the seventh NPN tube (Q7), the base electrode of the seventh NPN tube (Q7) and one end of a fourth resistor (R4), the collector electrode of the eighth NPN tube is connected with the drain electrode of the fourth PMOS tube (P4) and the output end Reg _ on, and the emitter electrode of the eighth NPN tube is connected with a reference ground port (GND);

one end of the third resistor (R3) is connected with the collector of the sixth NPN tube (Q6) and the base of the fifth NPN tube (Q5), and the other end of the third resistor (R3) is connected with the base of the sixth NPN tube (Q6) and the third current source (I3);

one end of a fourth resistor (R4) is connected with a collector of a seventh NPN tube (Q7), a base of the seventh NPN tube (Q7) and a base of an eighth NPN tube (Q8), and the other end of the fourth resistor (R4) is connected with a fourth current source (I4);

the third current source (I3) is connected with one end of the third resistor (R3) and the base electrode of the sixth NPN tube (Q6);

the fourth current source (I4) is connected to one end of the fourth resistor (R4).

2. A synchronous rectification converter as claimed in claim 1, wherein: the switch MOS tube (N1) and the sampling MOS tube (N2) are integrated on the same silicon chip and have a common substrate structure.

3. A synchronous rectifying converter according to claim 1 or 2, characterized in that: the sampling MOS tube (N2) detects a voltage signal between the source and the drain of the switching MOS tube (N1) and outputs a sampling signal (VDET) to the control circuit; the control circuit generates a turn-on signal (SR _ on), a regulation pull-up signal (Reg _ on), a regulation pull-down signal (Reg _ off) and a turn-off signal (SR _ off) by processing the sampling signal (VDET), adjusts the potential of a driving signal (GATE) connected to the grid electrode of the switch MOS tube (N1), and controls the turn-on and turn-off of the synchronous rectification converter.

4. A synchronous rectification converter as claimed in claim 1, wherein: for the upper sub-circuit, when the voltage of the sampling signal (VDET) is greater than the set third threshold V3, the output terminal Reg _ off is high, that is, the following relationship is satisfied:

VDET+I1*R1>0

VDET>-I1*R1

the output end Reg _ off is high potential;

wherein, R1 refers to the first resistor, I1 refers to the first current source, VDET refers to the voltage value of the sampled signal; defining-I1 × R1 as a third threshold V3, wherein the first resistor (R1) and the second resistor (R2) in the upper sub-circuit are resistors with equal resistance values, and the first current source (I1) and the second current source (I2) are current sources with equal current values;

for the lower sub-circuit, when the voltage of the sampling signal (VDET) is less than the set fourth threshold V4, the output terminal Reg _ on is at a high level, that is, the following relationship is satisfied:

VDET+I4*R4<0

VDET<-I4*R4

the output end Reg _ on is high potential;

wherein, R4 refers to a fourth resistor, I4 refers to a fourth current source, and VDET refers to the voltage value of the sampled signal; let-I4 × R4 be defined as the fourth threshold V4, and the third resistor (R3) and the fourth resistor (R4) in the lower sub-circuit are resistors with equal resistance, and the third current source (I3) and the fourth current source (I4) are current sources with equal current.

5. A synchronous rectification converter as claimed in claim 1, wherein: the over-temperature protection output line loss compensation circuit (205) comprises a fifth PMOS (P5), a sixth PMOS (P6), a seventh PMOS (P7), an eighth PMOS (P8), a ninth PMOS (P9), a third NMOS (N3), a fourth NMOS (N4), a fifth NMOS (N5), a sixth NMOS (N6), a seventh NMOS (N7), an eighth NMOS (N8), a ninth NMOS (N9), a ninth NPN (Q9), a first voltage source (V1), a fifth current source (I5), a sixth current source (I6), a seventh current source (I7) and a first logic NOT gate (M1);

the source electrode of the fifth PMOS tube (P5) is connected with a power supply port (VCC), and the grid electrode of the fifth PMOS tube (P5) is connected with the drain electrode of the fifth PMOS tube (P6), the grid electrode of the sixth PMOS tube (P6), the drain electrode of the third NMOS tube (N3) and the drain electrode of the fifth NMOS tube (N5);

the grid electrode of the sixth PMOS tube (P6) is connected with the grid electrode of the fifth PMOS tube (P5), the drain electrode of the fifth PMOS tube (P5), the drain electrode of the third NMOS tube (N3) and the drain electrode of the fifth NMOS tube (N5), the source electrode of the sixth PMOS tube is connected with the power supply port (VCC), and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the eighth NMOS tube (N8), the grid electrode of the fourth NMOS tube (N4) and the input end of the first logic NOT gate (M1);

a gate of the seventh PMOS transistor (P7) is connected to a base of the ninth NPN transistor (Q9), a collector of the ninth NPN transistor (Q9), and the fifth current source (I5), a source thereof is connected to the sixth current source (I6), a drain thereof is connected to a drain of the sixth NMOS transistor (N6), a gate of the sixth NMOS transistor (N6), a gate of the fifth NMOS transistor (N5), and a gate of the third NMOS transistor (N3);

the gate of the eighth PMOS tube (P8) is connected with the first voltage source (V1), the source of the eighth PMOS tube is connected with the sixth current source (I6), and the drain of the eighth PMOS tube is connected with the drain of the seventh NMOS tube (N7), the gate of the seventh NMOS tube (N7) and the gate of the eighth NMOS tube (N8);

the grid electrode of the ninth PMOS tube (P9) is connected with the output end of the first logic NOT gate (M1) and receives the over-temperature protection signal OTP, the source electrode of the ninth PMOS tube is connected with the seventh current source (I7), and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube (N9) and the output compensation port (COMP);

the grid electrode of the third NMOS tube (N3) is connected with the grid electrode of the fifth NMOS tube (N5), the grid electrode of the sixth NMOS tube (N6), the drain electrode of the sixth NMOS tube (N6) and the drain electrode of the seventh PMOS tube (P7), the drain electrode of the third NMOS tube is connected with the grid electrode of the fifth PMOS tube (P5), the drain electrode of the fifth PMOS tube (P5), the grid electrode of the sixth PMOS tube (P6) and the drain electrode of the fifth NMOS tube (N5), and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube (N4);

the grid electrode of the fourth NMOS tube (N4) is connected with the drain electrode of the sixth PMOS tube (P6), the drain electrode of the eighth NMOS tube (N8) and the input end of the first logic NOT gate (M1), the drain electrode of the fourth NMOS tube is connected with the source electrode of the third NMOS tube (N3), and the source electrode of the fourth NMOS tube is connected with the ground reference port (GND);

the grid electrode of the fifth NMOS tube (N5) is connected with the grid electrode of the third NMOS tube (N3), the drain electrode of the sixth NMOS tube (N6), the grid electrode of the sixth NMOS tube (N6) and the drain electrode of the seventh PMOS tube (P7), the drain electrode of the fifth NMOS tube (P5), the drain electrode of the fifth PMOS tube (P5), the grid electrode of the sixth PMOS tube (P6) and the drain electrode of the third NMOS tube (N3), and the source electrode of the fifth NMOS tube (N5) is connected with the ground reference port (GND);

the grid electrode of the sixth NMOS tube (N6) is connected with the drain electrode of the sixth NMOS tube (N5), the grid electrode of the fifth NMOS tube (N5), the grid electrode of the third NMOS tube (N3) and the drain electrode of the seventh PMOS tube (P7), and the source electrode of the sixth NMOS tube (N6) is connected with the ground reference port (GND);

the grid electrode of the seventh NMOS tube (N7) is connected with the drain electrode of the seventh NMOS tube, the grid electrode of the eighth NMOS tube (N8) and the drain electrode of the eighth PMOS tube (P8), and the source electrode of the seventh NMOS tube is connected with the ground reference port (GND);

the grid electrode of the eighth NMOS tube (N8) is connected with the grid electrode of the seventh NMOS tube (N7), the drain electrode of the seventh NMOS tube (N7) and the drain electrode of the eighth PMOS tube (P8), the drain electrode of the eighth NMOS tube is connected with the drain electrode of the sixth PMOS tube (P6), the grid electrode of the fourth NMOS tube (N4) and the input end of the first logic NOT gate (M1), and the source electrode of the eighth NMOS tube (N8) is connected with the ground reference port (GND);

the grid electrode of the ninth NMOS tube (N9) is connected with the driving signal (GATE), the drain electrode of the ninth NMOS tube is connected with the output compensation port (COMP) and the drain electrode of the ninth PMOS tube (P9), and the source electrode of the ninth NMOS tube is connected with the ground reference port (GND);

the base electrode of the ninth NPN tube (Q9) is connected with the collector electrode of the ninth NPN tube, the fifth current source (I5) and the grid electrode of the seventh PMOS tube (P7), and the emitter electrode of the ninth NPN tube is connected with the ground reference port (GND);

the first voltage source (V1) is connected with the grid electrode of the eighth PMOS tube (P8);

the fifth current source (I5) is connected with the base electrode of the ninth NPN tube (Q9), the collector electrode of the ninth NPN tube (Q9) and the grid electrode of the seventh PMOS tube (P7);

the sixth current source (I6) is connected with the source electrode of the seventh PMOS tube (P7) and the source electrode of the eighth PMOS tube (P8);

the seventh current source (I7) is connected with the source electrode of the ninth PMOS tube (P9);

the input end of the first logic not gate (M1) is connected with the drain electrode of the sixth PMOS transistor (P6), the gate electrode of the fourth NMOS transistor (N4) and the drain electrode of the eighth NMOS transistor (N8), and the output end of the first logic not gate is connected with the gate electrode of the ninth PMOS transistor (P9), and transmits the over-temperature protection signal OTP to the gate electrode of the ninth PMOS transistor (P9).

6. A synchronous rectification converter as claimed in claim 5, wherein: when the driving signal (GATE) is high, the ninth NMOS tube (N9) is conducted, a current Icomp flows in from the output compensation port (COMP), and output line loss compensation is realized by using the current;

the gate of the seventh PMOS transistor (P7) is connected to the base and collector of the ninth NPN transistor (Q9), the gate of the eighth PMOS transistor (P8) is connected to the first voltage source (V1), the junction drop VBE between the base and emitter of the ninth NPN transistor (Q9) is a negative temperature coefficient, and when the temperature of the working environment of the chip is too high, at this time:

VBE<V1

the over-temperature protection signal OTP is low;

wherein VBE refers to a junction voltage drop between the base and the emitter of the ninth NPN transistor (Q9), and V1 refers to the first voltage source;

when the over-temperature protection signal OTP is low, the ninth PMOS tube (P9) is conducted, a current Icomp flows out from the output compensation port (COMP), and the over-temperature protection is realized by using the current.