CN108880204B - Chaotic frequency modulation digital switching power supply control circuit based on FPGA - Google Patents
Chaotic frequency modulation digital switching power supply control circuit based on FPGA Download PDFInfo
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- CN108880204B CN108880204B CN201811018393.3A CN201811018393A CN108880204B CN 108880204 B CN108880204 B CN 108880204B CN 201811018393 A CN201811018393 A CN 201811018393A CN 108880204 B CN108880204 B CN 108880204B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
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- Manipulation Of Pulses (AREA)
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Abstract
The invention discloses a chaotic frequency modulation digital switching power supply control circuit based on an FPGA, which comprises a PID duty ratio parameter calculation circuit, a chaotic sequence generation circuit, a chaotic signal processing circuit and a digital pulse width modulation circuit; the PID duty ratio parameter calculation circuit is electrically connected with the digital pulse width modulation circuit; the chaotic sequence generating circuit is electrically connected with the chaotic signal processing circuit; the chaotic signal processing circuit is electrically connected with the digital pulse width modulation circuit; the digital pulse width modulation circuit is electrically connected with the circuit output signal. The circuit can realize chaotic modulation of the switching frequency of the numerical control switching power supply, has controllable modulation range, can inhibit electromagnetic interference of the numerical control switching power supply, and can be used for designing a control chip of the numerical control switching power supply.
Description
Technical Field
The invention relates to the technical field of power electronic control, in particular to a chaotic frequency pulse width modulation FPGA control circuit which is suitable for electromagnetic interference suppression control of a digital switching power supply.
Background
The numerical control switch power supply is more and more popular in the market due to the characteristics of special programmability, portability, realization of multifunctional control and the like, but the input current and the switch tube voltage of the switch power supply contain rich switch frequency harmonic components which cause electromagnetic interference noise, and the energy is concentrated at the switch frequency and the frequency multiplication position thereof, so that serious electromagnetic interference is formed. The application of the chaotic frequency modulation technology can disperse the harmonic frequency of noise, reduce the amplitude of discrete harmonic, and inhibit electromagnetic interference, wherein the power spectrum has continuous frequency spectrum characteristics. At present, particularly in the field of digital switching power supply control, a chaotic frequency modulation scheme which is economical, effective and high in universality is lacking.
Disclosure of Invention
The invention aims to provide a control circuit of a chaotic frequency modulation digital switching power supply based on an FPGA, which can realize chaotic modulation of switching frequency, and the modulation range can be set through parameters, so that electromagnetic interference of the digital switching power supply can be effectively inhibited.
The technical scheme for solving the technical problems is as follows: the chaotic frequency modulation digital switching power supply control circuit based on the FPGA is characterized in that: the device comprises a PID duty ratio parameter calculation circuit, a chaotic sequence generation circuit, a chaotic signal processing circuit and a digital pulse width modulation circuit; the PID duty ratio parameter calculation circuit is electrically connected with the digital pulse width modulation circuit; the chaotic sequence generating circuit is electrically connected with the chaotic signal processing circuit; the chaotic signal processing circuit is electrically connected with the digital pulse width modulation circuit; the digital pulse width modulation circuit is electrically connected with the circuit output signal.
In the chaotic sequence generating circuit, the output end of a delay falling edge Single Pulse1 is connected with a data selection port of a data selector multiplex 1, the output end of the data selector multiplex 2 is connected with a 0 input end of the data selector multiplex 1, a Constant1 chaotic mapping initial value is connected with a 1 input end of the data selector multiplex 1, the output end of the data selector multiplex 1 is connected with the input end of a chaotic mapping function circuit and a 1 input end of the chaotic mapping function circuit, the output end of the chaotic mapping function circuit is connected with a 0 input end of the multiplex 2, the data selection end of the data selector multiplex 2 is connected with the output end of a complex 1 of a digital Comparator word Pulse width modulation circuit, and the output end of the data selector multiplex 2, namely a chaotic sequence Nc, is connected with a chaotic signal processing circuit; a new chaos number Nc is generated each time the output of the Comparator1 is low, i.e. a new switching cycle starts.
In the chaotic signal processing circuit, the output end of multiple 2, namely a chaotic sequence, is connected with the input end of a data bus AltBus1, the output end of the data bus AltBus1 is connected with one input end of a multiplier Product1, a Constant2 chaotic frequency modulation degree parameter Re is connected with the other input end of the Product1, the output end of the Product1 is connected with the 0 input end of a data selector multiple 3, a Constant3 fixed period offset value N' is connected with the 1 input end of the data selector multiple 3, an input signal In2, namely a chaotic frequency modulation switching signal, is connected with a data selection port of the multiple 3, and the output end of the multiple 3 is connected with one input end of an Adder Adder1The end is connected, the Constant4 period addend N is connected with another input end of the Adder Adder1, the output end of the Adder Adder1 is connected with the input end of the Delay unit Delay1, and the output end of the Delay unit Delay1 is the switching period number N T The digital pulse width modulation circuit is connected with the digital pulse width modulation circuit; when the input signal In2, i.e. the chaotic frequency modulated switching signal is at a high level, the switching period number N T The switching frequency is a fixed value f/(N' +N), where f is the working clock of the accumulator Inc1, and the switching period number N is when the input signal In2, i.e. the chaotic frequency modulation switching signal, is at a low level T The switching frequency is the chaos modulation value f/(nc·re+n) for the chaos change value nc·re+n, the switching frequency is determined by Nc for each new switching cycle, the magnitude of Re determines the frequency modulation degree, and the larger the Re is, the larger the switching frequency change range is.
In the PID duty cycle parameter calculation circuit and the digital pulse width modulation circuit, an input signal In1, namely a power supply feedback signal, is connected with the input end of the PID duty cycle parameter calculation circuit, the output end of the PID duty cycle parameter calculation circuit, namely the duty cycle parameter D, is connected with the 'b' input end of the Comparator Comparator2, the output end of the accumulator Inc1 is connected with the 'a' input end of the Comparator Comparator2 and the 'b' input end of the Comparator Comparator1, the output end of the Comparator2 is connected with the reset end of the accumulator Inc1, and the 'a' input end of the Comparator1 is connected with the switching cycle number N T The output end of the Comparator Comparator2 is connected with the 'R' input end of the S-R trigger, the output end of the Comparator Comparator1 is connected with the 'S' input end of the S-R trigger, and the output end Q of the S-R trigger, namely the switching pulse, is connected with the output signal Out of the circuit; when the reset of the accumulator Inc1 is 0 and starts counting, i.e. a new switching period starts, the switching pulse outputs a high level, and once the accumulator Inc1 is larger than the duty cycle parameter D, the switching pulse locks to output a low level until the accumulator Inc1 is larger than N T One switching cycle ends and then accumulator Inc1 resets to 0, starting a new switching cycle.
The beneficial effects of the invention are as follows: the chaotic modulation of the switching frequency of the numerical control switching power supply can be realized, the modulation range is controllable, the electromagnetic interference of the numerical control switching power supply can be restrained, and the digital switching power supply can be used for designing a control chip of the numerical control switching power supply.
Drawings
Fig. 1 is a schematic block diagram of the circuit of the present invention.
Detailed Description
The invention provides a design scheme for an FPGA circuit, wherein a chaotic mapping function circuit and a PID duty ratio parameter calculation circuit can adopt a common design scheme as a circuit module.
The chaotic frequency modulation digital switching power supply control circuit based on the FPGA comprises a PID duty ratio parameter calculation circuit 3, a chaotic sequence generation circuit 1, a chaotic signal processing circuit 2 and a digital pulse width modulation circuit 4; the PID duty ratio parameter calculation circuit is electrically connected with the digital pulse width modulation circuit; the chaotic sequence generating circuit is electrically connected with the chaotic signal processing circuit; the chaotic signal processing circuit is electrically connected with the digital pulse width modulation circuit; the digital pulse width modulation circuit is electrically connected with the circuit output signal.
The chaotic sequence generating circuit comprises a falling edge Single Pulse1, a data selector multiple 2, a Constant1 chaotic mapping initial value and a chaotic mapping function circuit; in the chaotic sequence generating circuit, the output end of a delay falling edge Single Pulse1 is connected with a data selection port of a data selector multiplex 1, the output end of the data selector multiplex 2 is connected with a 0 input end of the data selector multiplex 1, a Constant1 chaotic mapping initial value is connected with a 1 input end of the data selector multiplex 1, the output end of the data selector multiplex 1 is connected with the input end of a chaotic mapping function circuit and a 1 input end of the chaotic mapping function circuit, the output end of the chaotic mapping function circuit is connected with a 0 input end of the multiplex 2, the data selection end of the data selector multiplex 2 is connected with the output end of a complex 1 of a digital Comparator word Pulse width modulation circuit, and the output end of the data selector multiplex 2, namely a chaotic sequence Nc, is connected with a chaotic signal processing circuit; a new chaos number Nc is generated each time the output of the Comparator1 is low, i.e. a new switching cycle starts. The chaotic sequence generating circuit is used for generating a new chaotic number Nc at the beginning of each new switching period and setting the current switching period so as to modulate the switching frequency.
The chaotic signal processing circuit comprises a data bus AltBus1, a multiplier Product1, a Constant2 chaotic frequency modulation degree parameter Re, a data selector multiple 3, a Constant3 fixed period offset value N', an Adder ADder1, a Constant4 period addend N and a Delay unit Delay1. In the chaotic signal processing circuit, the output end of multiple 2, namely, the chaotic sequence, is connected with the input end of a data bus AltBus1, the output end of the data bus AltBus1 is connected with one input end of a multiplier Product1, a Constant2 chaotic frequency modulation degree parameter Re is connected with the other input end of the Product1, the output end of the Product1 is connected with the 0 input end of a data selector multiple 3, a Constant3 fixed period offset value N' is connected with the 1 input end of the data selector multiple 3, an input signal In2, namely, a chaotic frequency modulation switching signal is connected with a data selection port of multiple 3, the output end of multiple 3 is connected with one input end of an Adder Adder1, a Constant4 period addition number N is connected with the other input end of the Adder Adder1, the output end of the Adder Adder1 is connected with the input end of a Delay unit Delay1, and the output end of the Delay unit Delay1, namely, the switching period number N T The digital pulse width modulation circuit is connected with the digital pulse width modulation circuit; when the input signal In2, i.e. the chaotic frequency modulated switching signal is at a high level, the switching period number N T The switching frequency is a fixed value f/(N' +N), where f is the working clock of the accumulator Inc1, and the switching period number N is when the input signal In2, i.e. the chaotic frequency modulation switching signal, is at a low level T The switching frequency is the chaos modulation value f/(nc·re+n) for the chaos change value nc·re+n, the switching frequency is determined by Nc for each new switching cycle, the magnitude of Re determines the frequency modulation degree, and the larger the Re is, the larger the switching frequency change range is. The function is to generate a switching period parameter N T The switching frequency is f/N T The working clock of the accumulator Inc1 can be selected between a fixed switching frequency and a chaotic modulation switching frequency through an input signal In2, and Re can be adjusted to be large when the chaotic modulation switching frequency is adoptedThe frequency modulation degree is set small.
The PID duty cycle parameter calculation circuit and the digital pulse width modulation circuit comprise a PID duty cycle parameter calculation circuit, comparators compiler 1 and compiler 2, an accumulator Inc1 and an S-R trigger. In the PID duty cycle parameter calculation circuit and the digital pulse width modulation circuit, an input signal In1, namely a power supply feedback signal, is connected with the input end of the PID duty cycle parameter calculation circuit, the output end of the PID duty cycle parameter calculation circuit, namely the duty cycle parameter D, is connected with the 'b' input end of the Comparator Comparator2, the output end of the accumulator Inc1 is connected with the 'a' input end of the Comparator Comparator2 and the 'b' input end of the Comparator Comparator1, the output end of the Comparator2 is connected with the reset end of the accumulator Inc1, and the 'a' input end of the Comparator1 is connected with the switching cycle number N T The output end of the Comparator Comparator2 is connected with the 'R' input end of the S-R trigger, the output end of the Comparator Comparator1 is connected with the 'S' input end of the S-R trigger, and the output end Q of the S-R trigger, namely the switching pulse, is connected with the output signal Out of the circuit; when the reset of the accumulator Inc1 is 0 and starts counting, i.e. a new switching period starts, the switching pulse outputs a high level, and once the accumulator Inc1 is larger than the duty cycle parameter D, the switching pulse locks to output a low level until the accumulator Inc1 is larger than N T One switching cycle ends and then accumulator Inc1 resets to 0, starting a new switching cycle. The function is that when the reset of the accumulator Inc1 is 0 and a new switching period is started, the switching pulse outputs high level, once the accumulator Inc1 is larger than the duty ratio parameter D, the switching pulse locks and outputs low level until the accumulator Inc1 is larger than N T And after one switching period is ended, the accumulator Inc1 is reset to 0, a new switching period is started, and the control of the power switch is completed.
Claims (2)
1. The chaotic frequency modulation digital switching power supply control circuit based on the FPGA is characterized in that: the device comprises a PID duty ratio parameter calculation circuit, a chaotic sequence generation circuit, a chaotic signal processing circuit and a digital pulse width modulation circuit; the PID duty ratio parameter calculation circuit is electrically connected with the digital pulse width modulation circuit; the chaotic sequence generating circuit is electrically connected with the chaotic signal processing circuit; the chaotic signal processing circuit is electrically connected with the digital pulse width modulation circuit; the digital pulse width modulation circuit is electrically connected with the circuit output signal;
in the chaotic sequence generating circuit, the output end of a delay falling edge single pulse1 is connected with a data selection port of a data selector multiple 1, the output end of the data selector multiple 2 is connected with a 0 input end of the data selector multiple 1, a Constant1 chaotic mapping initial value is connected with a 1 input end of the data selector multiple 1, the output end of the data selector multiple 1 is respectively connected with the input end of a chaotic mapping function circuit and the 1 input end of the data selector multiple 2, the output end of the chaotic mapping function circuit is connected with a 0 input end of the data selector multiple 2, the data selection port of the data selector multiple 2 is connected with the output end of a Comparator complex 1 of the digital pulse width modulation circuit, and the output end of the data selector multiple 2, namely a chaotic sequence Nc, is connected with a chaotic signal processing circuit; generating a new chaos number every time the output terminal of the Comparator1 is low level, i.e. a new switching period starts;
in the chaotic signal processing circuit, an output end of a data selector multiple 2, namely a chaotic sequence Nc, is connected with an input end of a data bus AltBus1, an output end of the data bus AltBus1 is connected with one input end of a multiplier Product1, a Constant2 chaotic frequency modulation degree parameter Re is connected with the other input end of the multiplier Product1, an output end of the multiplier Product1 is connected with a ' 0 ' input end of the data selector multiple 3, a Constant3 fixed period offset value N ' is connected with a ' 1 ' input end of the data selector multiple 3, an input signal In2, namely a chaotic frequency modulation switching signal, is connected with a data selection port of the data selector multiple 3, an output end of the data selector multiple 3 is connected with one input end of an Adder Ad1, a Constant Constant4 period addition number N is connected with the other input end of the Adder Adder1, an output end of the Adder1 is connected with an input end of a Delay unit Delay1, and an output end of the Delay unit Delay1 is connected with an output end of the Delay unitNumber of phases N T The digital pulse width modulation circuit is connected with the digital pulse width modulation circuit; when the input signal In2, i.e. the chaotic frequency modulated switching signal is at a high level, the switching period number N T When the input signal In2 is a chaotic frequency modulation switching signal at a low level, the switching frequency is a fixed value f/(N '+N), wherein f is an operating clock of an accumulator Inc1 In the digital pulse width modulation circuit, and the switching period number N is equal to the fixed value N' +N T For the chaos change value nc·re+n, the switching frequency is the chaos modulation value f/(nc·re+n), the switching frequency is determined by the chaos sequence Nc every new switching period, the magnitude of the Constant2 chaos frequency modulation parameter Re determines the frequency modulation, and the larger the Constant2 chaos frequency modulation parameter Re is, the larger the switching frequency change range is.
2. The FPGA-based chaotic frequency modulated digital switching power supply control circuit of claim 1, wherein: in the PID duty cycle parameter calculation circuit and the digital pulse width modulation circuit, an input signal In1, namely a power supply feedback signal, is connected with the input end of the PID duty cycle parameter calculation circuit, the output end of the PID duty cycle parameter calculation circuit, namely a duty cycle parameter D, is connected with the 'b' input end of the Comparator Comparator2, the output end of the accumulator Inc1 is respectively connected with the 'a' input end of the Comparator Comparator2 and the 'b' input end of the Comparator Comparator1, the output end of the Comparator Comparator2 is connected with the reset end of the Comparator Inc1, and the 'a' input end of the Comparator Comparator1 is connected with the switching cycle number N T The output end of the Comparator Comparator2 is connected with the 'R' input end of the S-R trigger, the output end of the Comparator Comparator1 is connected with the 'S' input end of the S-R trigger, and the output end Q of the S-R trigger, namely the switching pulse, is connected with the output signal of the circuit; when the reset of the accumulator Inc1 is 0 and starts counting, i.e. a new switching period starts, the switching pulse outputs a high level, and once the accumulator Inc1 is larger than the duty cycle parameter D, the switching pulse locks to output a low level until the accumulator Inc1 is larger than the switching period number N T One switching cycle ends and then accumulator Inc1 resets to 0, starting a new switching cycle.
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| CN101860196B (en) * | 2010-02-11 | 2013-01-16 | 华南理工大学 | Method and circuit for inhibiting switching converter EMI with chaos using PMW chip |
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| CN104883161A (en) * | 2015-05-05 | 2015-09-02 | 顺德职业技术学院 | Chaotic pulse width modulation and chaotic impulse position modulation circuit |
| CN108322060A (en) * | 2017-12-29 | 2018-07-24 | 河南北瑞电子科技有限公司 | A kind of digital program controlled AC power based on PWM controller |
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| 混沌频率调制技术在移相全桥变换器抑制EMI的应用;牛俊英;《顺德职业技术学院学报》;第12卷(第2期);第22-27页 * |
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