CN208874464U - Chaotic frequency modulation digital switch power control circuit based on FPGA - Google Patents
Chaotic frequency modulation digital switch power control circuit based on FPGA Download PDFInfo
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Abstract
The utility model discloses a kind of chaotic frequency modulation digital switch power control circuit based on FPGA, including PID duty cycle parameters counting circuit, chaos sequence generation circuit, chaotic Signals Processing circuit, digital pulse width modulation circuit；The PID duty cycle parameters counting circuit is electrically connected with digital pulse width modulation circuit；The chaos sequence generation circuit is electrically connected with chaotic Signals Processing circuit；The chaotic Signals Processing circuit is electrically connected with digital pulse width modulation circuit；The digital pulse width modulation circuit is electrically connected with circuit output signal.The chaotic modulation of numerical control switch power switch frequency may be implemented in the circuit, and modulation range is controllable, can inhibit the electromagnetic interference of numerical control switch power supply, can be used for the design of digitizing switch power supply control chip.
Description
Technical field
The utility model relates to power electronics control technology fields, are to be related to a kind of arteries and veins of chaos frequency more specifically
Width modulation modulation FPGA control circuit, inhibits to control it is suitable for the electromagnetic interference of digital switch power supply.
Background technique
Due to the distinctive programmability of numerical control switch power supply, portability, the characteristics such as multi-functional control can be achieved, gets over it
The favor by market is got over, however input current and switch tube voltage due to Switching Power Supply is rich in causes electromagnetism dry
The switching frequency harmonic components of noise are disturbed, energy concentrates at switching frequency and its frequency multiplication, forms serious electromagnetic interference.It answers
Noise harmonic frequency can be dispersed with chaotic frequency modulation technology, reduce discrete harmonic amplitude, be power spectrum in continuous frequency spectrum
Characteristic inhibits electromagnetic interference.And at present especially in digital switch power supply control field, also lack economical and effective, versatile
Chaotic frequency modulation scheme.
Utility model content
The purpose of this utility model is to provide a kind of, and the chaotic frequency modulation digital switch power supply based on FPGA controls electricity
Road, may be implemented the chaotic modulation of switching frequency, and modulation range can effectively can inhibit digital switch power supply by parameter setting
Electromagnetic interference.
The technical scheme in the invention for solving the technical problem is: a kind of chaotic frequency modulation number based on FPGA is opened
Powered-down source control circuit, it is characterised in that: including PID duty cycle parameters counting circuit, chaos sequence generation circuit, chaotic signal
Processing circuit, digital pulse width modulation circuit；The PID duty cycle parameters counting circuit and digital pulse width modulation circuit carry out electrical
Connection；The chaos sequence generation circuit is electrically connected with chaotic Signals Processing circuit；The chaotic Signals Processing circuit
It is electrically connected with digital pulse width modulation circuit；The digital pulse width modulation circuit is electrically connected with circuit output signal
It connects.
In the chaos sequence generation circuit, the output end and data of delay failing edge one (Single Pulse1) are selected
The data selection port of device one (Multiplexe1) is connected, the output end and data of data selector two (Multiplexe2)
The zero-input terminal of selector one (Multiplexe1) is connected, and (Constant1) the chaotic maps initial value of constant one and data are selected
The one-input terminal for selecting device one (Multiplexe1) is connected, and the output end of data selector one (Multiplexe1) is reflected with chaos
The input terminal for penetrating functional circuit is connected with the one-input terminal of data selector two (Multiplexe2), chaotic maps function electricity
The output end on road is connected with the zero-input terminal of data selector two (Multiplexe2), data selector two
(Multiplexe2) data selection end is defeated with the comparator one (Comparator1) of digital comparator pulse-width modulation circuit
Outlet is connected, and output end, that is, chaos sequence Nc of data selector two (Multiplexe2) is connected with chaotic Signals Processing circuit；
When the output end of comparator one (Comparator1) is that the new switch periods of low level i.e. start, one is generated newly
Chaos number Nc.
In the chaotic Signals Processing circuit, output end, that is, chaos sequence of data selector two (Multiplexe2) with
The input terminal of data/address bus one (AltBus1) is connected, the output end and multiplier one of data/address bus one (AltBus1)
(Product1) a input terminal is connected, constant two (Constant2) chaotic frequency modulation degree parameter Re and multiplier one
(Product1) another input terminal is connected, the output end and data selector three of multiplier one (Product1)
(Multiplexe3) zero-input terminal is connected, constant three (Constant3) fixed cycle deviant N ' and data selector three
(Multiplexe3) one-input terminal is connected, input signal In2, that is, chaotic frequency modulation switching signal and data selector three
(Multiplexe3) data selection port is connected, the output end and adder one of data selector three (Multiplexe3)
(Adder1) a input terminal is connected, constant four (Constant4) period addend N and adder one (Adder1) another
Input terminal is connected, and the output end of adder one (Adder1) is connected with the input terminal of delay unit one (Delay1), delay unit
The output end of one (Delay1), that is, switch periods number NTIt is connected with digital pulse width modulation circuit；When input signal In2, that is, chaos frequency
When rate modulation switch signal is high level, switch periods number NTFor fixed value N '+N, then switching frequency is fixed value f/ (N '+N),
Wherein f is the work clock of accumulator (Inc1), when input signal In2, that is, chaotic frequency modulation switching signal is low level,
Switch periods number NTFor chaos change value NcRe+N, then switching frequency is chaotic modulation value f/ (NcRe+N), each new
Switch periods determine switching frequency by Nc, and the size of Re determines warble rate, and the bigger switching frequency variation range of Re is more
Greatly.
In the PID duty cycle parameters counting circuit and digital pulse-width modulation circuit, input signal In1, that is, power supply feedback
Signal is connected with the input terminal of PID duty cycle parameters counting circuit, output end, that is, duty ratio of PID duty cycle parameters counting circuit
Parameter D is connected with " b " input terminal of comparator two (Comparator2), the output end and comparator two of accumulator (Inc1)
(Comparator2) " a " input terminal is connected with " b " input terminal of comparator one (Comparator1), comparator two
(Comparator2) output end is connected with the reset terminal of accumulator (Inc1), and " a " of comparator one (Comparator1) is defeated
Enter end and switch periods number NTIt is connected, " R " input terminal phase of the output end and S-R trigger of comparator two (Comparator2)
Even, the output end of comparator one (Comparator1) is connected with " S " input terminal of S-R trigger, the output end of S-R trigger
Q, that is, switching pulse is connected with the output signal Out of circuit；When accumulator (Inc1) be reset to 0 start counting i.e. one it is new
When switch periods start, switching pulse exports high level, once accumulator (Inc1) is greater than duty cycle parameters D, switching pulse is just
Locking output low level is greater than N until accumulator (Inc1)T, a switch periods terminate, and then accumulator (Inc1) is reset to
0, start a new switch periods.
The beneficial effects of the utility model are: the chaotic modulation of numerical control switch power switch frequency may be implemented, model is modulated
It encloses controllably, the electromagnetic interference of numerical control switch power supply can be inhibited, can be used for the design of digitizing switch power supply control chip.
Detailed description of the invention
Fig. 1 is the utility model schematic block circuit diagram.
Specific embodiment
The utility model is that FPGA circuitry realizes design scheme, wherein chaotic maps functional circuit and PID duty cycle parameters
Conventional design scheme can be used as circuit module in counting circuit.
A kind of chaotic frequency modulation digital switch power control circuit based on FPGA, including PID duty cycle parameters calculate
Circuit 3, chaos sequence generation circuit 1, chaotic Signals Processing circuit 2, digital pulse width modulation circuit 4；The PID duty cycle parameters
Counting circuit is electrically connected with digital pulse width modulation circuit；The chaos sequence generation circuit and chaotic Signals Processing circuit
It is electrically connected；The chaotic Signals Processing circuit is electrically connected with digital pulse width modulation circuit；The digital pulse width
Modulation circuit is electrically connected with circuit output signal.
Chaos sequence generation circuit includes failing edge one (Single Pulse1), data selector one
(Multiplexe1) and data selector two (Multiplexe2), (Constant1) chaotic maps of constant one initial value, chaos
Mapping function circuit；In the chaos sequence generation circuit, the output end and data of delay failing edge one (Single Pulse1)
The data selection port of selector one (Multiplexe1) is connected, the output end and number of data selector two (Multiplexe2)
It is connected according to the zero-input terminal of selector one (Multiplexe1), (Constant1) the chaotic maps initial value of constant one and data
The one-input terminal of selector one (Multiplexe1) is connected, the output end and chaos of data selector one (Multiplexe1)
The input terminal of mapping function circuit is connected with the one-input terminal of data selector two (Multiplexe2), chaotic maps function electricity
The output end on road is connected with the zero-input terminal of data selector two (Multiplexe2), data selector two
(Multiplexe2) data selection end is defeated with the comparator one (Comparator1) of digital comparator pulse-width modulation circuit
Outlet is connected, and output end, that is, chaos sequence Nc of data selector two (Multiplexe2) is connected with chaotic Signals Processing circuit；
When the output end of comparator one (Comparator1) is that the new switch periods of low level i.e. start, one is generated newly
Chaos number Nc.Chaos sequence generation circuit, when starting its role is to each new switch periods, generate one it is new mixed
Ignorant several Nc, for current switch period to be arranged to modulation switch frequency.
Chaotic Signals Processing circuit includes data/address bus one (AltBus1), multiplier one (Product1), constant two
(Constant2) chaotic frequency modulation degree parameter Re, data selector three (Multiplexe3), constant three (Constant3) are solid
Fixed cycle deviant N ', adder one (Adder1), constant four (Constant4) period addend N, delay unit one
(Delay1).In the chaotic Signals Processing circuit, output end, that is, chaos sequence of data selector two (Multiplexe2)
It is connected with the input terminal of data/address bus one (AltBus1), the output end and multiplier one of data/address bus one (AltBus1)
(Product1) a input terminal is connected, constant two (Constant2) chaotic frequency modulation degree parameter Re and multiplier one
(Product1) another input terminal is connected, the output end and data selector three of multiplier one (Product1)
(Multiplexe3) zero-input terminal is connected, constant three (Constant3) fixed cycle deviant N ' and data selector three
(Multiplexe3) one-input terminal is connected, input signal In2, that is, chaotic frequency modulation switching signal and data selector three
(Multiplexe3) data selection port is connected, the output end and adder one of data selector three (Multiplexe3)
(Adder1) a input terminal is connected, and constant four (Constant4) period addend N is another with adder one (Adder1)
A input terminal is connected, and the output end of adder one (Adder1) is connected with the input terminal of delay unit one (Delay1), and delay is single
Output end, that is, switch periods number N of one (Delay1) of memberTIt is connected with digital pulse width modulation circuit；When input signal In2, that is, chaos
When frequency modulation switch signal is high level, switch periods number NTFor fixed value N '+N, then switching frequency be fixed value f/ (N '+
N), wherein f be accumulator (Inc1) work clock, when input signal In2, that is, chaotic frequency modulation switching signal be low level
When, switch periods number NTFor chaos change value NcRe+N, then switching frequency is chaotic modulation value f/ (NcRe+N), each
New switch periods determine switching frequency by Nc, and the size of Re determines warble rate, the bigger switching frequency variation range of Re
It is bigger.Its role is to generate switch periods parameter NT, switching frequency is that wherein f is f/NT, when the work of accumulator (Inc1)
Clock can be selected by input signal In2 between fixed switching frequency and chaotic modulation switching frequency, when using chaotic modulation
Warble rate can be set by adjusting the size of Re when switching frequency.
PID duty cycle parameters counting circuit and digital pulse-width modulation circuit include PID duty cycle parameters counting circuit, compare
Device one (Comparator1) and comparator two (Comparator2), accumulator (Inc1), S- R trigger.The PID is accounted for
Sky is than in parameter calculation circuit and digital pulse-width modulation circuit, input signal In1, that is, power supply feedback signal and PID duty cycle parameters
The input terminal of counting circuit is connected, the output end, that is, duty cycle parameters D and comparator two of PID duty cycle parameters counting circuit
(Comparator2) " b " input terminal is connected, the output end of accumulator (Inc1) and " a " of comparator two (Comparator2)
Input terminal is connected with " b " input terminal of comparator one (Comparator1), the output end of comparator two (Comparator2) with
The reset terminal of accumulator (Inc1) is connected, " a " input terminal and switch periods number N of comparator one (Comparator1)TIt is connected,
The output end of comparator two (Comparator2) is connected with " R " input terminal of S-R trigger, comparator one (Comparator1)
Output end be connected with " S " input terminal of S-R trigger, the output of output end Q, that is, switching pulse of S-R trigger and circuit is believed
Number Out is connected；When accumulator (Inc1) is when being reset to 0 and starting counting that i.e. a new switch periods start, switching pulse is defeated
High level out, once accumulator (Inc1) is greater than duty cycle parameters D, switching pulse just locks output low level until accumulator
(Inc1) it is greater than NT, a switch periods terminate, and then accumulator (Inc1) is reset to 0, start a new switch periods.Its
Effect is that switching pulse exports when accumulator (Inc1) is when being reset to 0 and starting counting that i.e. a new switch periods start
High level, once accumulator (Inc1) is greater than duty cycle parameters D, switching pulse just locks output low level until accumulator
(Inc1) it is greater than NT, a switch periods terminate, and then accumulator (Inc1) is reset to 0, start a new switch periods, complete
The control of pairs of power switch.
Claims (4)
1. a kind of chaotic frequency modulation digital switch power control circuit based on FPGA, it is characterised in that: including PID duty ratio
Parameter calculation circuit, chaos sequence generation circuit, chaotic Signals Processing circuit, digital pulse width modulation circuit；The PID duty ratio
Parameter calculation circuit is electrically connected with digital pulse width modulation circuit；The chaos sequence generation circuit and chaotic Signals Processing
Circuit is electrically connected；The chaotic Signals Processing circuit is electrically connected with digital pulse width modulation circuit；The number
Pulse-width modulation circuit is electrically connected with circuit output signal.
2. the chaotic frequency modulation digital switch power control circuit based on FPGA according to claim 1, it is characterised in that:
In the chaos sequence generation circuit, the output end of delay failing edge one is connected with the data selection port of data selector one,
The output end of data selector two is connected with the zero-input terminal of data selector one, one chaotic maps initial value of constant and data
The one-input terminal of selector one is connected, the output end of data selector one and the input terminal and data of chaotic maps functional circuit
The one-input terminal of selector two is connected, the zero-input terminal phase of the output end and data selector two of chaotic maps functional circuit
Even, the data selection end of data selector two is connected with the output end of the comparator one of digital comparator pulse-width modulation circuit, number
It is connected according to output end, that is, chaos sequence Nc of selector two with chaotic Signals Processing circuit；Whenever the output end of comparator one is low
When the new switch periods of level i.e. start, a new chaos number Nc is generated.
3. the chaotic frequency modulation digital switch power control circuit based on FPGA according to claim 1, it is characterised in that:
In the chaotic Signals Processing circuit, the input terminal phase of the output end, that is, chaos sequence and data/address bus one of data selector two
Even, the output end of data/address bus one is connected with an input terminal of multiplier one, two chaotic frequency modulation degree parameter Re of constant and
Another input terminal of multiplier one is connected, and the output end of multiplier one is connected with the zero-input terminal of data selector three, constant
Three fixed cycle deviant N ' are connected with the one-input terminal of data selector three, input signal In2, that is, chaotic frequency modulation switch
Signal is connected with the data selection port of data selector three, the output end of data selector three and an input of adder one
End is connected, and four period of constant, addend N was connected with another input terminal of adder one, the output end and delay unit of adder one
One input terminal is connected, output end, that is, switch periods number N of delay unit oneTIt is connected with digital pulse width modulation circuit；Work as input
When signal In2, that is, chaotic frequency modulation switching signal is high level, switch periods number NTFor fixed value N '+N, then switching frequency is
Fixed value f/ (N '+N), wherein f is the work clock of accumulator, when input signal In2, that is, chaotic frequency modulation switching signal is
When low level, switch periods number NTFor chaos change value NcRe+N, then switching frequency is chaotic modulation value f/ (NcRe+N),
Each new switch periods determine switching frequency by Nc, and the size of Re determines warble rate, the bigger switching frequency variation of Re
Range is bigger.
4. the chaotic frequency modulation digital switch power control circuit based on FPGA according to claim 1, it is characterised in that:
In the PID duty cycle parameters counting circuit and digital pulse-width modulation circuit, power supply feedback signal and PID duty cycle parameters meter
The input terminal for calculating circuit is connected, output end, that is, duty cycle parameters D of PID duty cycle parameters counting circuit and " b " of comparator two
Input terminal is connected, and the output end of accumulator is connected with " b " input terminal of " a " input terminal of comparator two and comparator one, compares
The output end of device two is connected with the reset terminal of accumulator, " a " input terminal and switch periods number N of comparator oneTIt is connected, comparator
Two output end is connected with " R " input terminal of S-R trigger, " S " input terminal phase of the output end and S-R trigger of comparator one
Even, output end Q, that is, switching pulse of S-R trigger is connected with the output signal Out of circuit；0 beginning is reset to when accumulator
When counting is that a new switch periods start, switching pulse exports high level, once accumulator is greater than duty cycle parameters D, opens
Just locking exports low level until accumulator is greater than N for Guan pulse punchingT, a switch periods terminate, and then accumulator is reset to 0, opens
Begin a new switch periods.
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| CN201821443355.8U CN208874464U (en) | 2018-09-03 | 2018-09-03 | Chaotic frequency modulation digital switch power control circuit based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108880204A (en) * | 2018-09-03 | 2018-11-23 | 顺德职业技术学院 | Chaotic frequency modulation digital switch power control circuit based on FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108880204A (en) * | 2018-09-03 | 2018-11-23 | 顺德职业技术学院 | Chaotic frequency modulation digital switch power control circuit based on FPGA |
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