CN108878530A - 用于限定垂直晶体管器件中的沟道区的方法 - Google Patents

用于限定垂直晶体管器件中的沟道区的方法 Download PDF

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CN108878530A
CN108878530A CN201810460928.6A CN201810460928A CN108878530A CN 108878530 A CN108878530 A CN 108878530A CN 201810460928 A CN201810460928 A CN 201810460928A CN 108878530 A CN108878530 A CN 108878530A
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layer
fin
transistor
transistor device
dielectric
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CN108878530B (zh
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J·雷恰特
堀口直人
D·莫库塔
鲍 T·胡耶恩
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Interuniversitair Microelektronica Centrum vzw IMEC
Universite Libre de Bruxelles ULB
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Abstract

揭示了一种用于限定垂直晶体管器件中的沟道区的方法。该方法包括在衬底上提供由第一层(501)、第二层(502)和第三层(503)的堆叠形成的鳍(504、505、506)，其中第二层被置于第一层以上，并且第三层被置于第二层以上，选择性地在该鳍的第一和第三层的侧壁上形成电介质(507)，以及形成用于接触第二层的侧壁的栅极接触层(509)。第一和第三层分别限定垂直晶体管器件的源极和漏极区，第二层限定垂直晶体管器件的沟道区，并且第一和第三层的侧壁上的电介质将源极和漏极区与栅极接触层电隔离。

Description

用于限定垂直晶体管器件中的沟道区的方法
技术领域
本发明的概念涉及一种用于限定晶体管器件中的沟道区的方法。
背景技术
争取提供具有减小的存储器位单元和增加的电路密度的较小集成电路。
最近已经朝垂直晶体管进行了开发，垂直晶体管可能提供比基于先前晶体管的设计甚至更小的布局面积。实现当前和未来的缩放的晶体管类型是具有基于纳米线沟道的晶体管，诸如垂直纳米线场效应晶体管(FET)。由于垂直定向的沟道结构，栅极长度不由横向线宽而是由该层的垂直厚度来限定。此类晶体管尤其允许减小的栅极长度，同时使与平面器件相关联的短沟道效应问题最小化。
此外，垂直晶体管器件的源极区和漏极区相对于彼此垂直放置。出于这些原因，以及其它，垂直晶体管器件实现了密集器件集成。然而，制造垂直晶体管可能是相当复杂和昂贵的工艺。由此，需要用于制造此类晶体管器件的改善方法。
发明内容
本发明的概念的目的是为了提供一种用于限定晶体管器件中的沟道区的改进方法。从以下可以理解更多和替代目标。
根据本发明概念的一方面，提供了一种限定垂直沟道器件中的沟道区的方法，该方法包括：
在衬底上提供由第一层、第二层和第三层的堆叠形成的鳍，其中第二层位于第一层以上并且第三层位于第二层以上；
选择性地在鳍的第一和第三层的侧壁上形成电介质；以及
形成用于接触第二层的侧壁的栅极接触层；其中：
第一和第三层分别限定垂直晶体管器件的源极区和漏极区；
第二层限定垂直晶体管器件的沟道区；以及
第一和第三层的侧壁上的电介质将源极和漏极区与栅极接触层电隔离。
本发明的概念实现一种用于垂直对准晶体管器件中的沟道区的方法。这是通过以下来进行的：选择性地在鳍的源极和漏极区的侧壁上形成电介质，从而接触由第二层的表面侧壁限定的沟道区的栅极接触层可与源极和漏极区电隔离。电介质的选择性沉积因此允许栅极接触层在沟道区处的自对准，这简化了器件的处理。该方法因此可有利地被应用于形成垂直晶体管。该方法可以特别有利地被用来形成包括互补金属氧化物半导体(CMOS)，特别是静态随机存取存储器单元(SRAM单元)的电路系统。
鳍可被理解为至少沿其长度的一部分可在直线中延伸并且呈现均匀宽度的特征。鳍例如可通过蚀刻包括多层的堆叠结构来形成，从而所得到的鳍是多层结构。鳍的宽度以及相邻鳍之间的最小距离可使用多种图案化技术，诸如自对准双图案化(SADP)或四重图案化(SAQP)来限定。
藉由层的“堆叠”由此意指例如在垂直方向上被安排在彼此上方或顶部的层。
在诸如层、层面或其它元件之类的第一特征“上”形成层、层面或其它元件由此意指在垂直方向上在第一特征上形成第二特征。
藉由垂直晶体管器件由此意指源极和漏极区被安排在彼此以上的晶体管器件。作为在垂直方向上流动的电流，该器件可被认为形成垂直晶体管器件。
藉由术语“接触层”由此意指与其它层处于电接触的层，例如经由电场不直接接触或者藉由欧姆接触直接接触。
在本申请的上下文中，术语“栅极接触层”或者“栅极层面”可指包括导电路径的结构，该导电路径通过电隔离材料或电介质彼此分开。还可被称为栅极线的导电路径可在鳍的侧壁上在鳍之间以及在鳍上延伸。由此，将领会，术语“层”或“层面”并不限于平面结构或导电材料。相反，它可包括在不同垂直层面上延伸并且彼此电隔离的栅极线。
术语“沟道”或“沟道区”可指晶体管结构的安排在源极与漏极区之间的功能部件，并且电流可通过该功能部件在晶体管器件处于其导通状态时流动。
此外，术语“栅极”、“栅极接触”、或“栅极电极”可指栅极接触层或栅极线的安排在沟道区处的部分，并且晶体管器件的导电状态可通过该部分来控制。由此，栅极接触可指栅极接触层的与鳍的第二层的(诸)侧壁(即，由鳍形成的晶体管器件的沟道区)接触的部件。将领会，栅极电极可被安排在鳍的仅一侧上，或者在两侧上。此外，在鳍已经形成在柱中的情况下，栅极电极也可被安排在该柱的其余侧壁的一者或两者上。在栅极电极被安排成围绕柱的情况下，晶体管器件可被称为环栅晶体管。
藉由术语“选择性地形成”意指导致在第一和第三层的侧壁上，但是不在鳍的第二层上形成电介质的过程。由此，结果所得的结构允许由后续添加的栅极接触层来接触沟道区，同时源极和漏极区保持与栅极接触层电隔离。选择性的形成可在单个过程中执行，或者藉由多个处理步骤来执行。以下将进一步详细地讨论不同的例示实施例。
电介质的沉积的选择性可例如通过形成材料的第二层的侧壁来实现，与其它层的侧壁材料相比，该材料较不易于形成(或接收或构造)电介质。例如，这可通过组合具有不同氧化速率的两种材料来进行，从而在某些条件下，第一和第三层的材料可形成比第二层的材料厚的多的氧化层。因此，诸如举例而言与氧化物形成过程期间的温度和压力有关的环境或过程参数之类的条件可被选择成使得与鳍的第二层的氧化速率相比，增加第一与第三层的氧化速率之间的比率。
此外，应领会，在某些电介质材料也被沉积在第二层的侧壁上的情况下，它可在后续处理步骤中被移除。该移除可以是选择性的，从而从第二层但不从第一和第三层中移除电介质，或者均匀地移除电介质。在移除是均匀的情况下，电介质可在第一和第三层处形成更厚的层，从而允许在从第二层中移除电介质之后，至少一些电介质保留在第一和第三层上。
由此，根据一实施例，选择性地形成电介质的步骤可包括在一温度和压力下氧化第一、第二和第三层，该温度和压力被选择成使得在第一和第三层上提供比在第二层上更厚的电介质。为了移除已经形成的电介质，即使以低得多的速率，在第二层的侧壁上，可增加蚀刻电介质以暴露第二层的侧壁的后续步骤，从而电介质中的至少一些电介质保留在第一和第三层上以将源极和漏极区与栅极接触层隔离。
电介质于此可指特定氧化物。由此，在特定温度和/或压力下，各层上的不同材料以不同速度氧化。通过选择温度和/或压力从而以比第二层上更高的速率在第一和第三层上形成电介质，该电介质在各侧壁上得到不同的厚度。例如，第二层可一无所获或者得到非常薄的层，而第一和第三层可得到相比第二层较厚的层。实现这些不同的厚度可被视为选择性沉积。在一个示例中，第一和第三层可由硅锗SiGe形成而第二层可由硅Si形成。因此，SiGe可在相同温度和/或压力下，以与Si层相比更高的速率氧化。
选择性地形成电介质的替换或附加示例可以是功能化(或制备)各层的表面从而与第二层的(诸)侧壁表面相比，电介质在第一和第三层的侧壁表面上更快地生长。功能化的示例可包括原子层沉积(ALD)以增强在第一和第三层的侧壁表面上的沉积，或者ALD或化学汽相沉积(CVD)以禁止第二层的侧壁表面的成核。鳍的侧壁表面的功能化的其它示例可以利用亲水性-H键与疏水性-O-H键以实现形成电介质中的选择性。
在另一实施例中，该方法可包括在形成栅极接触层之前在第二层的至少一个侧壁上形成栅极氧化堆叠的步骤。栅极氧化物堆叠允许场效应晶体管(FET)。栅极氧化物可以是高k电介质(具有高电介质常数k)。使用高k材料允许在没有相关联的漏泄效应的情况下增加的栅极电容。
根据一个实施例，可提供至少两个平行的鳍。此外，栅极接触层可包括至少三个平行的栅极线，其中每个栅极线可与其它隔离并且相对于至少两个鳍在正交方向上在两个鳍上延伸。
由此，各鳍可以是平行的，其中栅极接触层可由与鳍正交地延伸的平行栅极线形成。每个栅极线遵循鳍的轮廓，即被安排在各鳍上、沿鳍的侧壁安排并在相邻鳍之间延伸。栅极线与鳍之间的交点可限定晶体管器件的位置，晶体管器件因此可在交点以下的垂直区中形成。换句话说，垂直区可被理解为鳍的垂直延伸部分。
根据一实施例，每个鳍可包括用于形成N型晶体管器件的第一垂直区，和用于形成P型晶体管器件的第二垂直区。这允许在需要不同晶体管类型的组合的不同类型的逻辑部件，诸如逻辑单元、反相器和存储器位单元中形成鳍。垂直区可包括由第一、第二和第三层形成的堆叠结构，其中第一和第三层可以是N掺杂或P掺杂的，而第二层是P掺杂的、N掺杂或根本未掺杂的，这取决于要形成的晶体管的类型。在一些示例中，垂直区可形成NMOS晶体管，其中源极/漏极区可以是高度n掺杂(N++)的并且沟道区是轻掺杂(P、本征或N)或根本未掺杂的。因此，垂直区可形成PMOS晶体管，其中源极/漏极区可以是高度p掺杂(P++)的，而沟道区可具有与NMOS晶体管的沟道区相同的掺杂。
每个鳍可形成在若干柱中，每个柱藉由将垂直区彼此分开的蚀刻过程形成晶体管器件。这可例如藉由硬掩模来执行，可向硬掩模提供被转移至鳍中的图案。在一个示例中，栅极线可被用作蚀刻掩模以将各鳍切成柱。蚀刻可仅通过第三和第二层来执行，从而第一层的材料保留在鳍的垂直区之间，由此形成底电极。通过术语柱摂因此应被理解为竖直结构或桩，该竖直结构或桩可形成为例如通过蚀刻被切成片的鳍。柱可例如由鳍的两个上层形成，留下完整的低层以互连鳍的晶体管的底部区域，或者由所有三个层形成(万一形成隔离的晶体管(即，不共享源极/漏极区))。
根据一个实施例，鳍中的第一鳍可被形成在第一晶体管器件、第二晶体管器件和第三晶体管器件中，而鳍中的第二鳍可被形成在第四晶体管器件、第五晶体管器件和第六晶体管器件中。鳍中的每个鳍可包括包含P型和N型晶体管器件的晶体管对。由此，将认识到，每个鳍可被形成在例如两个N型晶体管器件和一个P型晶体管器件，或者一个N型晶体管器件和两个P型晶体管器件中，从而允许形成逻辑组件。通过仅切割鳍的两个上层，可形成两个晶体管器件，这两个晶体管器件共享底层从而晶体管中的第一晶体管的源极与晶体管中的第二晶体管的漏极共享。例如P型晶体管和N型晶体管经由第一层共享源极/漏极区的这种结构可被用于形成例如反相器。
根据一个实施例，栅极线可被中断在各鳍之间从而第一鳍中的晶体管器件的栅极与第二鳍中的晶体管器件的栅极隔离。
在一个实施例中，鳍中的每个鳍的晶体管器件可通过由该鳍的第一层形成的漏极连接，或者通过切割第一层以将晶体管器件彼此隔离并且随后重新生长第一层以形成底电极被连接至其相邻晶体管器件。以此方式，第一层可被用于互连晶体管器件以及用于形成漏极区两者，这允许高效布局。这种形成可例如促成SRAM单元的存储器阵列中的器件的集成。
在本申请的上下文中，“相邻晶体管器件”可指同一个鳍的晶体管器件。
通过术语“SRAM单元”或“SRAM位单元”由此意指包括用于存储数据的至少两个交叉耦合的反相器的SRAM器件。这些术语可贯穿本文互换地使用。
在一个实施例中，在源极/漏极区具有合适的掺杂类型之后，第一层可以是每个鳍的第一层的区域中的硅化物，从而在两个相邻晶体管之间形成漏极连接。以此方式，PN结的硅化可减少对源极/漏极区的访问电阻。
在一个实施例中，每个鳍的晶体管对的栅极可彼此电连接并且连接至其它鳍中的晶体管对的漏极连接。这允许形成SRAM单元，其中可至少在两个平行的鳍之间的区域中形成电互连。通过电连接的这种安排，可实现SRAM单元的更紧凑设计。
在一个实施例中，至漏极连接的电连接可延伸到两个平行的鳍之间的区域以外。这允许底电极(即，安排在两个柱之间的第一层的部分)在形成晶体管器件的柱的任一侧上的第一层的高掺杂(并且可能是硅化的)区域上接触。
在一个实施例中，SRAM单元可进一步具有用于位线(BL)和字线(WL)的电连接，该BL和WL可被连接至每个鳍的其余晶体管器件(即，不包括在该对晶体管器件中的晶体管器件)的相应栅极。这些电连接可至少形成在两个平行的鳍之间的区域中从而允许紧凑的设计。以此方式，SRAM单元可被电连接至WL用于控制在读和写操作器件对该单元的访问。在栅极电极被设置在形成柱的鳍的两个侧壁的情况下，可从鳍的任一侧访问该栅极。
如已经提及的，术语“其余的晶体管”由此可意指该晶体管不包括在电连接至其它鳍的漏极连接的晶体管对中。
在一个实施例中，第二层可由硅(Si)形成而第一层和第三层可由硅锗(SiGe)形成。替换地，第二层可由SiGe形成并且第一层和第三层由Si形成。如本文所提及的诸如举例而言Si和SiGe的材料可在每层的形成期间(例如，在外延生长期间添加的杂质的形成中)或者在已经形成该层之后(例如，藉由离子注入)被掺杂。
附图说明
参考附图，通过以下解说性和非限制性详细描述，将更好地理解本发明概念的以上以及附加目标、特征和优点。在附图中，相同的附图标记将被用于相同的元素，除非另外指明。
图1-6示意性地解说了一种从透视图中看的根据本发明的概念的一个或多个实施例的用于限定晶体管器件中的沟道区的方法。
图7a和图8a示出了根据一些实施例的鳍结构的俯视图，而图7b和图8b示出了该鳍结构的横截面侧视图。
图9示出了SRAM器件的透视图。
图10是示出根据温度的不同材料上的氧化物生长。
具体实施方式
现在将参照图1-8来描述一种用于限定晶体管器件中的沟道区的方法。
在图1中，揭示了堆叠结构100的透视图。堆叠结构100可包括第一层101、第二层102和第三层103。第一层可被安排在各层的底部，而第二层可被放置在第一层以上而第三层可被放置在各层的顶部或者第二层以上。堆叠结构100可被安排在半导体衬底(附图中未示出)上。当形成垂直晶体管器件时，源极区可由第一层来限定，栅极区可由第二层来限定，而漏极区可由第三层来限定。第一和第三层的材料可由例如硅锗(SiGe)形成。第二材料可不同于第一和第三材料，并且例如可以是硅(Si)。
图2示出了与以上结合图1描述的结构类似的堆叠结构200的透视图，已经通过使用经图案化的抗蚀层在垂直方向上跨该堆叠并且优选地使用各向异性蚀刻来蚀刻穿了堆叠结构200，由此形成三个平行的鳍204、205、206，其中每个鳍具有三个层201、202、203。
图3示出了堆叠结构300的透视图，堆叠结构300可类似于参照图2描述的结构，它有具有第一层301、第二层302和第三层303的三个平行的鳍304、305、306。如本附图中所指示的，电介质307可被选择性地形成在第三层303和第一层301的垂直侧壁的表面上。电介质307可由此形成鳍的第一和第三层的侧壁的电隔离，同时留下第二层的(诸)侧壁未被覆盖以允许它被栅极接触层接触。
存在用于选择性地在鳍304、305、306的侧壁上形成电介质307的不同技术。根据一示例的方法包括在一温度和压力下氧化第一层301、第二层302和第三层303，该温度和压力被选择成使得电介质的厚度在第一层301和第三层303上生长得比在第二层302上快。以此方式，第一和第三层上更厚的电介质可被生产，而相对较薄的电介质层或者根本没有电介质在第二层的(诸)侧壁上形成。电介质随后可被蚀刻以暴露第二层的侧壁。电介质的均匀蚀刻可导致电介质被完全从第二层中移除，而至少一些电介质保留在第一和第三层上。
图10是示出形成第一、第二和第三层的材料可如何影响氧化物(电介质)在不同温度下如何生长到不同的氧化物厚度的示例的示图。在具体示例中，示出了Si和SiGe上的氧化物生长。氧化物厚度由垂直y轴来表示而温度由水平x轴来表示。如图10中所指示的，SiGe可在比Si高得多的温度，并且具体地在400℃到700℃之间的温度下氧化。电介质的选择性沉积因此可通过以此种温度区间氧化SiGe的第一和第三层以及Si的第二层，接着是从Si层中移除氧化物从而允许栅极层接触晶体管器件的沟道区的步骤来实现。
替换地或附加地，电介质的选择性形成可通过以如下方式来功能化(或制备)各层的表面来实现：允许电介质(诸如举例而言氧化物)较快地在第一和第三层的侧壁表面上沉积而较慢地在第二层的(诸)侧壁表面上沉积。一种选项可以是利用原子层沉积(ALD)，该ALD可增强在第一和第三层的侧壁表面上的沉积，而另一选项可以是使用ALD或化学汽相沉积(CVD)以禁止第二层的侧壁表面的成核。此外，亲水性-H键和疏水性-O-H键可被用于实现形成电介质中的选择性。
图4示出了鳍结构400的透视图，鳍结构400可与参照图3所描述的结构类似，具有三个鳍、第一层401、第二层402和第三层403以及电介质407，但是其中栅极氧化物或栅极氧化物堆叠408可形成在第一层401、第二层402和第三层403的侧壁上。以此方式，第二层402可限定FET的垂直沟道区。栅极氧化物堆叠408可不同于先前在第一和第三层上形成的电介质，并且在一些示例中可以是诸如举例而言SiO2之类的高k材料。
图5示出了鳍结构500的透视图，鳍结构500可与参照图3所描述的结构类似，具有三个鳍504、505、506、第一层501、第二层502和第三层503以及电介质507、栅极氧化物堆叠508，进一步包括在鳍之间提供的用于接触第二层502的侧壁的栅极接触层509。例如可包括W或Co的栅极接触层509由此可形成晶体管器件的栅极接触。
栅极接触层609可被提供以填充鳍504、505、506之间的空间并且从而覆盖第三层503。由于电介质507已经被选择性地形成在第一和第三层上，接触沟道区502的栅极电极可在第一层501和第三层503的侧壁上在电介质507之间垂直对准。由此，沟道区在鳍的垂直方向上可以是自对准的。
词语“接触”可不限于因各层之间的可能栅极氧化物而导致的欧姆接触。例如，它可以是藉由如例如在场效应晶体管(FET)的电场操作的栅极接触。
为了形成不同类型的晶体管器件，诸如举例而言N型和P型晶体管，每个鳍可包括不同掺杂的垂直区。此类区域的示例在图6中解说，图6示出了其中已经藉由外延生长形成了各层的鳍600的透视图。在外延生长期间，杂质可被添加至材料以形成每层的N和P掺杂区。在一个示例中，鳍可被水平分为三个垂直区或部分，即第一部分612、第二部分613和第三部分614。在第一区612和第三区614中，第一和第三层601、603可以是P掺杂的而第二层是N掺杂的。第一区612和第三区614因此可被分别形成在N型晶体管中。第二区613可包括N掺杂的第一和第三层601、603，以及P掺杂的第二层。由此可形成P型晶体管。掺杂例如可针对每层和每区分开执行，例如通过在相应层的外延生长期间和/或注入离子之后添加杂质。在离子注入中，掺杂物材料的离子可在电场中被加速并被压入到待掺杂的材料中。
图7a示出了两个鳍704、705的俯视图，而图7b示出了鳍中的一个鳍的侧视图(如通过图7a的虚线所见)，其中每个鳍可类似于如参照图5所描述的鳍。栅极接触层可由三个平行栅极线710形成，垂直于鳍704、705延伸并且沿鳍的轮廓在第三层703以上。栅极线710的材料可在所有栅极线710中是相同的。此外，这些栅极线710可在柱中形成鳍时被用作蚀刻掩模728。
图8a示出了两个鳍800的俯视图，而图8b示出了鳍中的一个鳍的侧视图(如通过图8的虚线所见)。鳍可类似于如参照图7a和7b所述的鳍。如本图中所示，第二层802和第三层803可通过蚀刻掩模728被蚀刻以形成每个鳍的柱811。在鳍804、805与栅极线810之间的交点处，柱811可被形成在晶体管器件830中。第一层801或底层可以是对相同鳍的所有垂直晶体管器件的公共层或公共漏极，因为蚀刻可在第一层801上停止。替换地，第一层801可同样被蚀刻以将晶体管器件830彼此分开。该步骤可在优选地为经掺杂材料的柱之间重新生长层之后，从而形成连接晶体管器件830的源极/漏极区的底电极。
每个鳍可包括第一垂直区，其中第一层801和第三层803可以是N掺杂的而第二层802可以是P掺杂的。第一垂直区由此可形成N型晶体管器件。每个鳍可进一步包括第二垂直区，其中第一层801和第三层803可以是P掺杂的而第二层802可以是N掺杂的。第二垂直区由此可形成P型晶体管器件。
此外，每个鳍可具有由P型和N型晶体管器件形成的晶体管对，以及由N型和P型晶体管器件形成的其余晶体管器件。作为示例，每个鳍可形成一个P型晶体管器件和至少两个N型晶体管器件，或者至少两个P型晶体管器件和至少一个N型晶体管器件。
栅极线810也可被中断在各鳍之间从而第一鳍804中的晶体管器件的栅极与第二鳍805中的晶体管器件的栅极隔离。因为源极和漏极区被安排在彼此以上，因此电流在垂直方向上流动并形成垂直晶体管器件。因为栅极线810可被安排在鳍804、805的两个横侧上，晶体管器件830的栅极可从鳍804、805的任一侧(或两侧)接触。
每个鳍的晶体管器件可被互连以形成静态随机存取存储器SRAM器件。在一个示例中，两个鳍的六个晶体管器件可形成SRAM器件。SRAM器件可包括两个N型晶体管器件和四个P型晶体管器件或者两个P型晶体管和四个N型晶体管。SRAM器件通常包括由N型和P型晶体管器件形成的旁通(PG)晶体管、下拉晶体管(PD)和上拉晶体管(PU)。
图9示出了根据一实施例的SRAM器件900的示例。SRAM器件可由两个鳍，即第一鳍和第二鳍形成。鳍可被形成在六个垂直晶体管器件：第一鳍的第一晶体管器件915、第二晶体管器件916和第三晶体管器件917以及第二鳍的第四晶体管器件918、第五晶体管器件919、第六晶体管器件920中。
每个鳍的三个晶体管器件可通过由该鳍的第一层形成的漏极连接被连接至它们的鳍的它们的相邻晶体管器件。第一层可在在两个相邻晶体管之间形成漏极连接的部分处被硅化。
每个鳍的晶体管对的栅极可被电连接在一起并且进一步电连接至其它鳍中的晶体管对的漏极连接，从而形成SRAM单元。电连接可至少被形成在两个平行的鳍之间的区域中，这允许晶体管器件之间的相对较短互连并且因此允许高效面积使用。减少互连长度进一步允许减少的电容并且因此允许SRAM单元的增加的速度。
至漏极连接的电连接还可延伸到两个平行的鳍之间的区域以外。在一些情况下，SRAM单元可从该单元的外围以外的点接触，这促成了与其它鳍或逻辑组件的连接。
其余晶体管器件的栅极，例如第一晶体管器件915和第六晶体管器件920的分别栅极可被电连接至字线(WL)921，字线921可在读和写操作器件被用于控制对存储单元的存取。第六晶体管器件920的栅极还可被电连接至位线(BL)并且第一晶体管器件915的栅极可被电连接至经反向的位线(iBL)。电连接可至少在两个平行的鳍之间的区域中形成。位线可被用于传递针对存储器单元的读和写操作两者的数据。第二晶体管916和第三晶体管917的栅极可由连接925被电连接在一起并且还被电连接至第二鳍中的晶体管对920、919的漏极连接929。由此，SRAM单元可被提供，其中可至少在两个平行的鳍之间的区域中形成电连接。以类似的方式，第四晶体管器件918和第五晶体管器件919的栅极可通过连接924被电连接在一起并且还电连接至第一鳍中的晶体管对916、915的漏极连接(未示出)，从而形成交叉耦合的反相器对。
在上文中已经参照有限数目的示例主要描述了本发明概念。然而，如本领域技术人员容易领会的，除上面公开的示例以外的其它示例在如所附权利要求限定的本发明概念的范围内是同样可能的。

Claims (12)

1.一种用于限定垂直晶体管器件中的沟道区的方法，所述方法包括：
在衬底上提供由第一层(501)、第二层(502)和第三层(503)的堆叠形成的鳍(504、505、506)，其中所述第二层位于第一层以上并且所述第三层位于所述第二层以上；
选择性地在所述鳍的所述第一层和所述第三层的侧壁上形成电介质(507)；以及
形成用于接触所述第二层的侧壁的栅极接触层(509)；
其中：
所述第一层和所述第三层分别限定所述垂直晶体管器件的源极和漏极区；
所述第二层限定所述垂直晶体管器件的沟道区；以及
所述第一层和所述第三层的所述侧壁上的所述电介质将所述源极和漏极区与所述栅极接触层电隔离。
2.如权利要求1所述的方法，其特征在于，选择性地形成所述电介质的所述步骤包括：
以一温度和压力氧化所述第一层、所述第二层和所述第三层，所述温度和压力被选择成使得在所述第一层和所述第三层上提供比在所述第二层上更厚的电介质；并且其后
蚀刻所述电介质以暴露所述第二层的所述侧壁从而所述电介质的至少一些电介质保留在所述第一层和所述第三层上。
3.如权利要求1或2中任一项所述的方法，其特征在于，所述方法进一步包括在形成所述栅极接触层之前，在所述第二层的所述侧壁上形成栅极氧化物堆叠(509)的步骤。
4.如先前权利要求中任一项所述的方法，其特征在于，包括提供至少两个平行的鳍，其中：
所述栅极接触层包括至少三个平行栅极线(710)，所述栅极线彼此隔离并且与所述至少两个鳍正交；以及
每个鳍包括用于形成N型晶体管器件的第一垂直区，和用于形成P型晶体管器件的第二垂直区。
5.如权利要求4所述的方法，其特征在于，包括：
在第一晶体管器件(915)、第二晶体管器件(916)和第三晶体管器件(917)中形成所述鳍中的第一鳍；以及
在第四晶体管器件(918)、第五晶体管器件(919)和第六晶体管器件(920)中形成所述鳍中的第二鳍；其中
所述鳍中的每个鳍具有由P型晶体管器件和N型晶体管器件形成的晶体管对。
6.如权利要求5所述的方法，其特征在于，所述栅极线被中断在所述鳍之间从而将所述第一鳍中的所述晶体管器件的所述栅极与所述第二鳍中的所述晶体管器件的所述栅极隔离。
7.如权利要求5或6所述的方法，其特征在于，所述鳍中的每个鳍的所述晶体管器件通过由所述鳍的所述第一层形成的漏极连接被连接至它们的相邻晶体管器件。
8.如权利要求7所述的方法，其特征在于，进一步包括使每个鳍的所述第一层的在两个相邻晶体管之间形成所述漏极连接的部分硅化的步骤。
9.如权利要求7或8所述的方法，其特征在于，进一步包括电连接每个鳍的所述晶体管对的所述栅极的步骤以及将所述栅极电连接至另一鳍中的所述晶体管对的所述漏极连接的步骤，由此形成SRAM单元，其中所述电连接至少在所述两个平行的鳍之间的区域中形成。
10.如权利要求9所述的方法，其特征在于，至所述漏极连接的所述电连接延伸到所述两个平行的鳍之间的所述区域以外。
11.如权利要求9和10所述的方法，其特征在于，进一步包括将所述鳍中的每个鳍的其余晶体管器件的所述栅极分别连接至位线和字线的步骤，其中所述电连接至少在所述两个平行的鳍之间的区域中形成。
12.如先前权利要求中任一项所述的方法，其特征在于，所述第二层由硅(Si)形成而所述第一层和所述第三层由硅锗(SiGe)形成。
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