CN108810429A - A kind of linear ccd image acquisition system - Google Patents
A kind of linear ccd image acquisition system Download PDFInfo
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- CN108810429A CN108810429A CN201810882970.7A CN201810882970A CN108810429A CN 108810429 A CN108810429 A CN 108810429A CN 201810882970 A CN201810882970 A CN 201810882970A CN 108810429 A CN108810429 A CN 108810429A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
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Abstract
The present invention relates to image capturing systems,More particularly to a kind of inexpensive high-speed linear ccd image acquisition system,Including microprocessor,Power module,Communication module,Host module,Linear ccd image acquisition module,Image signal processing blocks,The microprocessor,Communication module,Linear ccd image acquisition module is connected with the power module,The host module connects the microprocessor by the communication module,The linear ccd image acquisition module and described image signal processing module are connected with the microprocessor,The linear ccd image acquisition module is connect with described image signal processing module,Compared with prior art,Structure of the invention is simplified,It is at low cost,Stable connection,Noise is small,Picking rate is fast,Work efficiency is high,Image procossing link had both remained original image detail feature,The noise of target image can be inhibited again,It reads and analyzes for follow-up microprocessor image data,Provide higher validity and reliability,It has a extensive future.
Description
Technical field
The present invention relates to image capturing system more particularly to a kind of inexpensive high-speed linear ccd image acquisition systems.
Background technology
It is well known that CCD is using charge as signal, basic function is generation, storage, transmission and the inspection of signal charge
It surveys.When light is incident on the photosurface of CCD, CCD completes opto-electronic conversion first, that is, generates linear with incident radiation amount
Optical charge.The operation principle of CCD is to gather corresponding charge according to the power of light, generates the light current directly proportional to charge quantity of light
Signal is pressed, filtered, enhanced processing, allergen light intensity weak electric signal or mark can be indicated by exporting one by driving circuit
Accurate vision signal.Line array CCD realizes image sensing based on the above-mentioned principle that one dimensional optical information is changed into power information output
With the functions such as dimensional measurement.
With the fast development of modern science and technology, ccd image acquisition system is widely used in Optical System Design, as in
A kind of laser thickness measuring apparatus disclosed in state's utility model patent 201721237810.4 comprising instrument body, the instrument body
Camera lens, a speculum, a measurement module and a peripheral drive circuit and a line array CCD, work are received including a laser module, one
The line array CCD carries out Image Acquisition under the driving of the peripheral drive circuit when making, but the circuit module exists in use
Many defects, such as connect that noise in the unstable, course of work is big, picking rate is slow, working efficiency is low, have seriously affected the laser
The performance of measuring thickness device.
For the linear CCD of different characteristics, driver' s timing difference, common type of drive in currently available technology
Mainly there are RPROM drivings, digital circuit driving, FPGA drivings and MCU driving, first three type of drive to there is volume mostly
Larger, of high cost, the shortcomings of design is complicated and the development cycle is long, although MCU driving mode flexible design, at low cost,
It is that, due to being influenced by microcontroller working clock frequency, high-frequency impulse phase difference is adjusted there are certain difficulty, and microcontroller
Communication speed is a bottleneck again, and the overwhelming majority is communicated using serial ports or RS232, and data transmission bauds is too slow, may be only available for
The simple application system of low speed, therefore, MCU driving mode cannot be widely applied.In addition, in ccd image acquisition system
In, the pretreatment of linear CCD output signal is the vital link of precise acquisition image data, the quality for the treatment of effect
The analysis that the quality and later stage of image will be directly influenced, should eliminate as much as the noise mixed in signal, and not in processing
The details of loss of energy image, and to ensure that the output of ccd image signal is changed linearly with the variation of detection object brightness, because
This, signal processing circuit design, parts selection, parameter configuration also become the difficult point and key in the design of ccd image acquisition system
Point.
Invention content
Present invention aim to address above-mentioned the deficiencies in the prior art, provide a kind of stable connection, at low cost, noise is small,
The linear ccd image acquisition system that picking rate is fast, work efficiency is high.
Technical solution is used by the present invention solves above-mentioned the deficiencies in the prior art：
A kind of linear ccd image acquisition system, which is characterized in that including microprocessor, power module, communication module, host mould
Block, linear ccd image acquisition module, image signal processing blocks, the microprocessor, communication module, linear ccd image acquisition
Module is connected with the power module, and the host module connects the microprocessor, the line by the communication module
Property ccd image acquisition module and described image signal processing module are connected with the microprocessor, and the linear ccd image is adopted
Collection module is connect with described image signal processing module.
Preferably, heretofore described microprocessor includes ADC digital analog converters, DMA direct memory access unit, storage
Device, timer, the DMA direct memory access unit are separately connected the ADC digital analog converters and the memory, and being used for will
The data that the ADC digital analog converters are read are saved in the memory, can realize the intermediate time in data hold time
Output data is acquired.
Preferably, heretofore described communication module includes 2.0 chips of USB, and communication effect is good, disclosure satisfy that data reality
The requirement of when property transmission, stable and reliable working performance.
Preferably, 2.0 chips of heretofore described USB use 8 bit data bus with the microprocessor communication, described
It is connected using USB D+ and USB D- data-interfaces between 2.0 chips of USB and the host module.
Preferably, the ADC numbers of the data output and the microprocessor of heretofore described linear ccd image acquisition module
The digital independent beat of mode converter matches, and picking rate is fast, and work efficiency is high.
Preferably, heretofore described image signal processing blocks include filtering shaping circuit, signal intensifier circuit, described
Filtering shaping circuit, signal intensifier circuit are set in turn in linear ccd image acquisition module rear end, and the ccd image is adopted
The picture signal of collection module output is filtered shaping and signal by the filtering shaping circuit and signal intensifier circuit successively
Enhancing, effectively overcomes the defect that conventional images signal processing circuit has delay noise big, and picture signal is distorted small, conversion speed
Soon, image detail feature had not only been remained, but also the noise of target image can have been inhibited, has been follow-up ADC digital analog converters image
Digital independent and analysis provide higher validity and reliability, image data transmission speed between system and host module
40M/s is reached as high as, especially suitable for low cost and to speed, the higher application of required precision.
Preferably, heretofore described filtering shaping circuit is inverse filter circuit, including operational amplifier U5, resistance
R11-R13, adjustable resistance VR1, capacitance C39-C43, C51, the positive input of the operational amplifier U5 is through adjustable resistance VR1
3.3V supply voltages are connected, the other end ground connection of the adjustable resistance VR1, the reverse input end of the operational amplifier U5 is through electricity
Hinder R11 connection CC OS（Linear ccd image signal exports I/O port）, the resistance R13 is arranged in the defeated of the operational amplifier U5
Outlet, signal of the present invention are inputted from the backward end of operational amplifier, and the photosensitive members of CCD for receiving ambient light, output can be allowed high
Voltage, while the noise mixed in picture signal is eliminated, the adjustable resistance VR1 is real for adjusting CCD dark voltage amplitudes
Tend to 0V under existing non-illuminated conditions, which can retain original feature of image, especially wave to the maximum extent
There is good effect at the edge and detail section of shape to the inhibition of noise.
Preferably, heretofore described signal intensifier circuit is amplifying circuit in the same direction, including operational amplifier U6, resistance
The positive input connection resistance R14 of R14-R16, R23, capacitance C44-C46, the operational amplifier U6, reversed input
End is grounded after the resistance R15, and the resistance R16 connect the operational amplifier U6 with one end after the capacitance C46 parallel connections
Reverse input end, the other end connects the output end of the operational amplifier U6 through resistance R23, and it is resistance R16 to make output voltage
With the ratio of R15, capacitance C46 can eliminate the multiple video in picture signal, keep waveform more smooth, stable.
Preferably, heretofore described image signal processing blocks are additionally provided with signal circuit, the signal are followed to follow electricity
Road is set to the signal intensifier circuit rear end, can have before picture signal enters the ADC digital analog converters of microprocessor
Imitate interacting between avoiding front stage.
Preferably, it is to follow circuit, including operational amplifier U7, resistance in the same direction that heretofore described signal, which follows circuit,
The positive input of R17-R21, capacitance C48-G50, the operational amplifier U7 connect the resistance R17, and reverse input end connects
The one end the resistance R21, the other end ground connection of the resistance R21 are connect, the output end of the operational amplifier U7 connects through resistance R18
The ADC digital analog converters of the microprocessor are connect, the R17 is used to eliminate the reflection of signal, this follows circuit for prime electricity
Road is equivalent to open circuit, is equivalent to a constant pressure source to late-class circuit, both output voltage had not by late-class circuit impedance influences
Buffer action further increases the stability of picture signal.
Preferably, heretofore described microprocessor is STM32F407, without increasing external ADC and CCD driver' s timings
Frequency dividing circuit, you can realize that ADC acquisitions match with ccd data rate, compared with other schemes, circuit is simplified, at low cost,
PCB can be designed more small and exquisite, have high cost performance and practicability.
The invention has the advantages that core of the image capturing system of the present invention by microprocessor STM32F407 as system
The speed of service of the heart, the normal operation of control system, abundant peripheral hardware and up to 168MHz is sufficient for system function requirement,
3 road Timing driver linear CCDs are exported using 3 16 bit timing devices of high-precision in STM32F407 pieces, picture signal is exported through height
After fast operational amplifier circuit processing, beat is obtained as high-speed ADC image in piece by 1 advanced timer, is deposited in conjunction with the direct memories of DMA
Data are stored in data buffer zone by storage technology, and image transmitting then uses USB2.0 chips to be passed as system and computer data
Defeated bridge realizes the high-speed transfer of image.The present invention is not necessarily to increase external ADC and CCD driver' s timing frequency dividing circuits simultaneously,
ADC acquisitions can be realized with ccd data rate to match, compared with prior art, circuit is simplified, at low cost, and PCB can be with
It is designed more small and exquisite, there is high cost performance and practicability.In terms of ccd image signal processing, existing low pass filtered is overcome
The defect that wave operational amplifier circuit has delay, noise big, for picture signal from exporting, reversed, amplification shaping, following output, distortion is few
In -3DB, conversion speed 30V/ μ s had not only remained image detail feature, but also can inhibit to the noise of target image, after being
Continuous ADC image datas are read and analysis, provide higher validity and reliability, image data passes between system and computer
Defeated speed reaches as high as 40M/s, especially suitable for low cost and to speed, the higher application of required precision.The present invention can be extensive
Applied to necks such as bar code recognition, various types image scanning, displacement, thickness accurate measurement application and intelligent vehicle racing track knowledges
Domain has broad application prospects.
Description of the drawings
Fig. 1 is the structure diagram of linear ccd image acquisition system of the present invention.
Fig. 2 is the circuit diagram of communication module of the present invention.
Fig. 3 is the structure diagram of image signal processing blocks of the present invention.
Fig. 4 is the circuit diagram of filtering shaping circuit of the present invention.
Fig. 5 is the circuit diagram of signal intensifier circuit of the present invention.
Fig. 6 is the circuit diagram that signal of the present invention follows circuit.
Fig. 7 is data acquisition principle schematic diagram of the present invention.
Fig. 8 is image data acquisition flow diagram of the present invention.
Specific implementation mode
It is described below for disclosing the present invention so that those skilled in the art can realize the present invention.It is excellent in being described below
Embodiment is selected to be only used as illustrating, it may occur to persons skilled in the art that other obvious modifications.It defines in the following description
The present invention basic principle can be applied to other embodiments, deformation scheme, improvement project, equivalent program and do not carry on the back
Other technologies scheme from the spirit and scope of the present invention.
Fig. 1 shows a kind of example structure block diagram of linear ccd image acquisition system of the present invention and a kind of preferred reality
Illustration is applied to be intended to.Linear ccd image acquisition system as shown in Figure 1, including microprocessor 10, power module 20, communication module
30, host module 40, linear ccd image acquisition module 50, image signal processing blocks 60, the microprocessor 10, communication mould
Block 30, linear ccd image acquisition module 50 are connected with the power module 20, and the host module 40 passes through the communication mould
Block 30 connects the microprocessor 10, the linear ccd image acquisition module 50 and described image signal processing module 60 with
The microprocessor 10 is connected, and the linear ccd image acquisition module 50 is connect with described image signal processing module 60.
Preferably, in Fig. 1 it can be seen from microprocessor described in the present embodiment include that ADC digital-to-analogues turn
Parallel operation 11, DMA direct memory access unit 12, memory 13, timer 14, the DMA direct memory access unit 12 are distinguished
The ADC digital analog converters 11 and the memory 13 are connected, the data for reading the ADC digital analog converters are saved in
The memory can realize that the intermediate time in data hold time is acquired output data.
Preferably, microprocessor 10 described in the present embodiment uses the high-performance ARM of STMicw Electronics
Cores of the Cortex-M4 microprocessors STM32F407 as system, the speed of service foot of abundant peripheral hardware and up to 168MHz
To meet system function requirement, 3 tunnel sequential are exported using 3 16 bit timing devices of high-precision in STM32F407 pieces（Shift pulse,
Master clock, reset pulse）Linear CCD is driven, picture signal output is after the processing of high speed operational amplifier circuit, by 1 advanced timer
Beat is obtained as high-speed ADC image in piece, data are stored in data buffer zone in conjunction with DMA direct memory storage technologies, and
Image transmitting then uses bridge of the USB2.0 chips as system and data transfer of computer, realizes the high-speed transfer of image.Together
When the present embodiment can make full use of peripheral hardware in STM32F407 pieces, divide electricity without increasing external ADC and CCD driver' s timings
Road, you can realize that ADC acquisitions match with ccd data rate, compared with prior art, circuit is simplified, at low cost, PCB
It can be designed more small and exquisite, there is high cost performance and practicability.
Preferably, as shown in Fig. 2, communication module described in the present embodiment includes 2.0 chips of USB, specifically
It is in the present embodiment USB3300 chips, communication effect is good, disclosure satisfy that the requirement of real-time property transmission, working performance are steady
It is fixed reliable.Preferably, the chips of USB 2.0 described in the present embodiment use 8 bit data bus with the microprocessor communication, described
It is connected using USB D+ and USB D- data-interfaces between 2.0 chips of USB and the host module.As shown in Fig. 2, USB3300
Chip clock source comes from external high speed 25MHz crystal oscillators, and main control chip STM32F407 is handed over by 8 bit data bus and USB3300
Two endpoints are arranged in mutual data, STM32F407, and endpoint size is 512Byte, a Bulk IN, as host module data
Output port, the input port of equipment, another Bulk OUT, as host module data-in port, the output of equipment
Port, host module are communicated by device descriptor, identification equipment and with equipment foundation.Host module passes through Bulk OUT first
It sends and obtains image data order, after equipment receives the order that host module issues, data are passed through Bulk IN endpoints by cycle
Image data is sent to host module.
Preferably, as shown in figure 3, image signal processing blocks 60 described in the present embodiment include that filtering is whole
Shape circuit 61, signal intensifier circuit 62, the filtering shaping circuit, signal intensifier circuit are set in turn in the linear CCD figure
As acquisition module 50 rear end, the picture signal of the ccd image acquisition module output pass through successively the filtering shaping circuit and
Signal intensifier circuit is filtered shaping and signal enhancing, and effectively overcoming conventional images signal processing circuit has delay, noise
Big defect, picture signal distortion are less than -3DB, and conversion speed 30V/ μ s had not only remained image detail feature, but also can be to target
The noise of image is inhibited, for follow-up ADC digital analog converters image data read and analyze, provide higher validity and
Reliability, image data transmission speed reaches as high as 40M/s between system and host module, especially suitable for low cost and to speed
Degree, the higher application of required precision.
Preferably, the linear ccd image acquisition module described in the present embodiment uses Toshiba
TCD1254GFG, 2500 pixels, typical driving pulse 2MHz, data rate 1MHz.CCD driver' s timings are by STM32F407
Timer generates PWM, and driving capability is sufficiently strong, and I/O pin output simplifies circuit without increasing other devices.Since CCD is quick
Feel component, under the pulsed drive of high frequency, be easy to introduce noise, waveform is jagged, noise on image processing influence compared with
Greatly, the links such as the input, acquisition and processing of image procossing and output result are influenced.Therefore, other images are being carried out
Before processing, it is necessary to carry out denoising to image.
Preferably, as shown in figure 4, filtering shaping circuit 61 described in the present embodiment is inverse filter electricity
Road, including operational amplifier U5, resistance R11-R13, adjustable resistance VR1, capacitance C39-C43, C51, the operational amplifier U5
Positive input through adjustable resistance VR1 connection 3.3V supply voltages, the other end of the adjustable resistance VR1 is grounded, the fortune
The reverse input end of amplifier U5 is calculated through resistance R11 connection CC OS（Linear ccd image signal exports I/O port）, the resistance R13
Output end in the operational amplifier U5 is set.Signal of the present invention is inputted from the backward end of operational amplifier, can allow reception
To the photosensitive members of CCD of ambient light, output HIGH voltage, while eliminating the noise mixed in picture signal, the adjustable resistance
VR1 is realized for adjusting CCD dark voltage amplitudes and is tended to 0V under non-illuminated conditions, which can be to the maximum extent
Retain original feature of image, the especially edge and detail section of waveform, has good effect to the inhibition of noise.
Preferably, as shown in figure 5, signal intensifier circuit 62 described in the present embodiment is that amplification is electric in the same direction
Road, including operational amplifier U6, resistance R14-R16, R23, capacitance C44-C46, the positive input of the operational amplifier U6
The resistance R14 is connected, reverse input end is grounded after the resistance R15, after the resistance R16 is in parallel with the capacitance C46
One end connects the reverse input end of the operational amplifier U6, and the other end connects the defeated of the operational amplifier U6 through resistance R23
Outlet, it is the ratio of resistance R16 and R15 to make output voltage, and capacitance C46 can eliminate the multiple video in picture signal, make wave
Shape is more smooth, stablizes.
Preferably, as shown in figure 3, image signal processing blocks 60 described in the present embodiment are additionally provided with signal
Follow circuit 63, the signal that circuit is followed to be set to the signal intensifier circuit rear end, it can be in picture signal into locating in a subtle way
Before the ADC digital analog converters for managing device, interacting between front stage is effectively avoided.Preferably, as shown in fig. 6, this implementation
It is to follow circuit, including operational amplifier U7, resistance R17-R21 in the same direction that signal described in example, which follows circuit, capacitance C48-G50,
The positive input of the operational amplifier U7 connects the resistance R17, and reverse input end connects the one end the resistance R21, institute
The other end ground connection of resistance R21 is stated, the output end of the operational amplifier U7 connects the ADC of the microprocessor through resistance R18
Digital analog converter, the R17 are used to eliminate the reflection of signal, this follows circuit to be equivalent to open circuit for front stage circuits, to rear class
Circuit is equivalent to a constant pressure source, and both output voltage had buffer action, and further increased not by late-class circuit impedance influences
The stability of picture signal.
In addition, to ensure CCD outputting high quality signal, operation amplifier described in the present embodiment under high frequency clock driving
Device U5-U7 is all made of shaping, amplification and the isolation that high speed amplifier AD8031 completes signal, which has 80MHz gain bandwidths,
1 MHz input signal rates, total harmonic distortion are -62 dBc, 30V/ μ s conversion speeds and quickly establish feature, disclosure satisfy that
System bandwidth and noise requirements.
Preferably, as shown in fig. 7, for data acquisition principle schematic diagram of the present invention, system in the present embodiment
Image data acquiring utilizes STM32F407 inner high speed ADC digital analog converters, is operated under 36MHz clocks, completes modulus and turns
It changes, 0.41 μ s of conversion time store data in conjunction with DMA direct memory access technologies, are subject to flexible software algorithm, real
The intermediate time of present data hold time is acquired output data, and linear ccd image described in the present embodiment is made to acquire
The data output of module and the digital independent beat of the ADC digital analog converters of the microprocessor match, and picking rate is fast, work
Make efficient.
Preferably, as shown in figure 8, for image data acquisition flow diagram of the present invention, in the present embodiment
Host module is computer host computer, and by computer host computer as host, STM32F407 is equipment, between host and equipment
Communication is based on USB2.0 agreements, and each equipment has unique PID, VID and device descriptor, for identification equipment identities, opens
And pass hull closure, the communication of data are always initiated by host, corresponding instruction and length is written by WriteDataBuffer in host
Degree, equipment receive the instruction of host, are judged first and execute corresponding instruction.To improve picture number between host and equipment
According to efficiency of transmission, slave image data packet is sized such that 5KB, in the same size with host receiving data packet, and host is without sending number
According to packet size request, it need to only send and obtain image data order, i.e., be recycled from data buffer zone ReadDataBuffer and read figure
As data.
It should be understood by those skilled in the art that the embodiment of the present invention shown in foregoing description and attached drawing is only used as illustrating
And it is not intended to limit the present invention.The purpose of the present invention has been fully and effectively achieved.The function and structural principle of the present invention exists
It shows and illustrates in embodiment, under without departing from the principle, embodiments of the present invention can have any deformation or modification.
Claims (10)
1. a kind of linear ccd image acquisition system, which is characterized in that including microprocessor, power module, communication module, host
Module, linear ccd image acquisition module, image signal processing blocks, the microprocessor, communication module, linear ccd image are adopted
Collection module is connected with the power module, and the host module connects the microprocessor by the communication module, described
Linear ccd image acquisition module and described image signal processing module are connected with the microprocessor, the linear ccd image
Acquisition module is connect with described image signal processing module.
2. linear ccd image acquisition system according to claim 1, which is characterized in that the microprocessor includes ADC numbers
Mode converter, DMA direct memory access unit, memory, timer, the DMA direct memory access unit are separately connected institute
ADC digital analog converters and the memory are stated, the data for reading the ADC digital analog converters are saved in the storage
Device.
3. linear ccd image acquisition system according to claim 1, which is characterized in that the communication module includes USB
2.0 chip.
4. linear ccd image acquisition system according to claim 3, which is characterized in that 2.0 chips of the USB with it is described
Microprocessor communication uses 8 bit data bus, and USB D+ and USB are used between 2.0 chips of the USB and the host module
D- data-interfaces are connected.
5. linear ccd image acquisition system according to claim 1, which is characterized in that described image signal processing module
Including filtering shaping circuit, signal intensifier circuit, the filtering shaping circuit, signal intensifier circuit are set in turn in described linear
The picture signal of ccd image acquisition module rear end, the ccd image acquisition module output passes through the filtering shaping circuit successively
It is filtered shaping and signal enhancing with signal intensifier circuit.
6. linear ccd image acquisition system according to claim 5, which is characterized in that the filtering shaping circuit is anti-
To filter circuit, including operational amplifier U5, resistance R11-R13, adjustable resistance VR1, capacitance C39-C43, C51, the fortune
The positive input of amplifier U5 is calculated through adjustable resistance VR1 connection 3.3V supply voltages, another termination of the adjustable resistance VR1
Ground, the reverse input end of the operational amplifier U5 through resistance R11 connection CC OS, in the operation put by the resistance R13 settings
The output end of big device U5.
7. linear ccd image acquisition system according to claim 5, which is characterized in that the signal intensifier circuit is same
To amplifying circuit, including operational amplifier U6, resistance R14-R16, R23, capacitance C44-C46, the operational amplifier U6 is just
The resistance R14 is connected to input terminal, reverse input end is grounded after the resistance R15, the resistance R16 and the capacitance
One end connects the reverse input end of the operational amplifier U6 after C46 parallel connections, and the other end is through the resistance R23 connections operation amplifier
The output end of device U6.
8. linear ccd image acquisition system according to claim 5, which is characterized in that described image signal processing module
Being additionally provided with signal follows circuit, the signal that circuit is followed to be set to the signal intensifier circuit rear end.
9. linear ccd image acquisition system according to claim 8, which is characterized in that it is same that the signal, which follows circuit,
To circuit, including operational amplifier U7, resistance R17-R21 is followed, capacitance C48-G50's, the operational amplifier U7 is positive defeated
Enter end and connect the resistance R17, reverse input end connects the one end the resistance R21, the other end ground connection of the resistance R21, institute
The output end for stating operational amplifier U7 connects the ADC digital analog converters of the microprocessor through resistance R18.
10. linear ccd image acquisition system according to claim 1, which is characterized in that the microprocessor is
STM32F407。
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109769096A (en) * | 2019-01-23 | 2019-05-17 | 电子科技大学 | A kind of servo control method for linear array CCD scanning process |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101254110A (en) * | 2008-03-04 | 2008-09-03 | 西安交通大学 | Medical X ray CCD type digital pick-up camera |
| CN103674248A (en) * | 2013-11-22 | 2014-03-26 | 深圳先进技术研究院 | Spectral data acquisition and transmission system and operating and application methods thereof |
| CN204578637U (en) * | 2015-04-24 | 2015-08-19 | 湖南大学 | Small-sized rotor patrol flight device visually-perceptible system |
| CN107782531A (en) * | 2016-08-25 | 2018-03-09 | 郭琳 | A kind of line array CCD spectral resolution detecting system |
| CN208540035U (en) * | 2018-08-06 | 2019-02-22 | 深圳精创视觉科技有限公司 | A kind of linear ccd image acquisition system |
-
2018
- 2018-08-06 CN CN201810882970.7A patent/CN108810429A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101254110A (en) * | 2008-03-04 | 2008-09-03 | 西安交通大学 | Medical X ray CCD type digital pick-up camera |
| CN103674248A (en) * | 2013-11-22 | 2014-03-26 | 深圳先进技术研究院 | Spectral data acquisition and transmission system and operating and application methods thereof |
| CN204578637U (en) * | 2015-04-24 | 2015-08-19 | 湖南大学 | Small-sized rotor patrol flight device visually-perceptible system |
| CN107782531A (en) * | 2016-08-25 | 2018-03-09 | 郭琳 | A kind of line array CCD spectral resolution detecting system |
| CN208540035U (en) * | 2018-08-06 | 2019-02-22 | 深圳精创视觉科技有限公司 | A kind of linear ccd image acquisition system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109769096A (en) * | 2019-01-23 | 2019-05-17 | 电子科技大学 | A kind of servo control method for linear array CCD scanning process |
| CN109769096B (en) * | 2019-01-23 | 2021-03-30 | 电子科技大学 | Servo motion control method for linear array CCD scanning process |
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