CN108055527A - Universal EMCCD tests system - Google Patents
Universal EMCCD tests system Download PDFInfo
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- CN108055527A CN108055527A CN201711337314.0A CN201711337314A CN108055527A CN 108055527 A CN108055527 A CN 108055527A CN 201711337314 A CN201711337314 A CN 201711337314A CN 108055527 A CN108055527 A CN 108055527A
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
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Abstract
The invention discloses a kind of universal EMCCD tests system, including NI hosts, EMCCD device bases, serial ports pinboard, differential signal pinboard, VPC series connectors, low voltage difference level shifting circuit, sine-wave drive circuit, programmable power supply circuit, backboard, correlated double sampling circuit and power supply.The present invention carries out voltage conversion using integrated power supply chip, integrated power supply chip have it is efficient, low in energy consumption, noise is low, integrated level is high, the advantages that additional filter capacitor and inductance is not required, meets the needs of industrial rank test system, for the EMCCD of different model, it is only necessary to design different EMCCD pedestals.
Description
Technical field
The invention belongs to low-light level imaging technical field, particularly a kind of universal EMCCD (electron multiplication CCD) test system
System.
Background technology
In recent years, CCD is used widely in fields such as industrial vision, dimensional measurement, aerospace and broadcast photographies,
The application in low-light field also reaches its maturity.Low-light refers to light or energy fainter under the conditions of night or low light environment
It is low to the light for being not enough to cause human vision sense organ.Low-light level imaging technology is then to be far below the micro- of normal illumination to what target was sent
The technology that dim light is detected generally enhances faint light condition or is directly obtained by low-light level imaging device under low-light (level) environment
The faint optical signalling of target is taken, so as in low light conditions by bias light realization to the blur-free imaging of target, the technology gram
Having taken needs extraneous the defects of providing active optical illumination under poor light condition, directly utilize faint light catoptric imaging.
At present, lll night vision imaging field is used there are mainly three types of relatively broad image enhancement means：First, it allows faint
Signal is amplified by image intensifier, is coupled to CCD, i.e. ICCD technologies using relay optics.The key of ICCD technologies is main
It is image intensifier, although the country has been able to independent development and produces Third Generation Image Intensifier, in terms of stability
It need to be improved.Second is that electron bombardment is carried out to CCD to obtain enhancing image, i.e. EBCCD technologies.The characteristic of EBCCD technologies is determined
CCD is determined and has been lost at work larger, working life is shorter, and noise is larger, significantly limits the application of EBCCD.Third, it reads
" avalanche effect " is utilized when going out signal charge, is realized and doubled by charge ionization by collision, is i.e. EMCCD technologies.EMCCD technologies are being
Built-in total solidity electronic doubling register controllably, passes through the on piece gain to signal, completes to read in common CCD device
The multiplication enhancing of charge, is realized under poor light condition to the imaging detection of target in signal process.Compared to ICCD, EMCCD is not
Image intensifier is needed, it can realize the amplification of signal charge by doubling register and is more clearly imaged under low-light,
EBCCD technologies are compared simultaneously, EMCCD service lifes are longer.And since the read frequency of signal does not interfere with reading noise, institute
It is relatively low with EMCCD reading noises, make it have the ability of fast imaging.
The beginning of this century, doctor Hynecek disclose report silicon CCD device realize the research of charge avalanche multiplication into
Fruit.The Texas Instruments (abbreviation TI) where it releases Impactron CCD series of products simultaneously.The same year, Britain E2V
Technologies companies are successfully proposed the EMCCD of entitled L3Vision, have declared the birth of all solid state micro-opto imaging CCD,
New milestone is set up in low-light level imaging field.The company that the world can manufacture EMCCD chips at present only has E2V and TI, but
There is the exploitation that many companies have started the low-illuminance cameras product based on EMCCD detector chips.2001, Britain Andor
Company has issued hypersensitivity camera iXON of the First based on EMCCD in the world, is then proposed and is studied for spectrum again
The Newton cameras of picture, the Luca cameras for releasing high performance-price ratio again in 2005, are suitble to common lab to use.In addition,
The companies such as Princeton Instruments, E2V Technologies, SALVADOR Imaging are also all for EMCCD's
Using having made intensive studies.
In terms of the performance test of EMCCD chips, foreign countries have had ripe chip test platform.From domestic development
From the point of view of, domestic be more focused on to the research of EMCCD minimizes the research and development of camera and EMCCD camera imaging performance parameters is ground
Study carefully, for example, research of the Yang Shaohua to EMCCD digitizing camera systems of Xi'an Xibei Nuclear Techn Inst, Beijing Control Engineering Inst.
The application study to EMCCD in highly sensitive star sensor such as Gong Dezhu, Wang Li, Institutes Of Technology Of Nanjing is to the light of EMCCD
Electrical property and test method expand research.The country also lays particular emphasis on the research and development to EMCCD cameras and performance evaluation at present, for
EMCCD test systematic researches have compared a certain distance with developed countries, are shown slightly not for test systematic research
Foot.
The achievement in research of domestic and international EMCCD shows：China is to the emphasis of EMCCD imaging system researchs suitable for a kind of type
The research and development of the miniaturization camera of number chip, this imaging system cannot test different EMCCD chips, have great limitation
Property.In addition, although domestic in recent years solve many technical barriers, and foreign countries in terms of EMCCD chip manufacturing process
Developed country lacks general, reliable EMCCD chip testing devices, therefore is unfolded to multi-purpose type than still there is very big gap
The research of EMCCD imaging systems, Development of Universal type EMCCD test systems, for research miniaturization EMCCD cameras, research EMCCD
Color night vision technology, the EMCCD chip production process for improving China have important practical significance.
The content of the invention
It is an object of the invention to provide a kind of universal EMCCD tests systems, can test and analyze various models
The imaging performance of EMCCD devices.
Realize the object of the invention technical solution be：A kind of universal EMCCD test system, including NI hosts,
EMCCD device bases, serial ports pinboard, differential signal pinboard, VPC series connectors, low voltage difference level shifting circuit,
Sine-wave drive circuit, programmable power supply circuit, backboard, correlated double sampling circuit and power supply；
NI hosts include NI6585 boards, CAMERALINK boards and serial ports board, and NI6585 boards turn with differential signal
Fishplate bar connects, and serial ports board is connected with serial ports pinboard, and serial ports pinboard, differential signal pinboard are connected respectively with VPC series
Device connects, and VPC series connectors are connected to backboard；Wherein, 4 serial ports are shared on serial ports board, control low voltage difference respectively
Level shifting circuit, sine-wave drive circuit, programmable power supply circuit, correlated double sampling circuit；Low-voltage is secured on backboard
Differential level shift circuit, sine-wave drive circuit, programmable power supply circuit, correlated double sampling circuit, and it is fixed on backboard
Four circuits connected by cable with EMCCD device bases；One MDR-26 connector of placement on the backboard, is used for
The connection of CAMERALINK boards.
Compared with prior art, the present invention its remarkable advantage：(1) timing control signal of system is compiled by LabView language
It writes, the parameters such as cycle, the phase of horizontal transfer sequential and vertical transfer timing can be changed, be conducive to test various types of
EMCCD.(2) sine wave drive write by Verilog language controls program, can change sine wave by serial ports assistant and drive
Amplitude, cycle and the phase of dynamic signal, are conducive to test various types of EMCCD.(3) by Verilog language write can
Bias supply voltage control routine is communicated between FPGA and DAC8420 chips by SPI protocol, can pass through rs 232 serial interface signal control
FPGA processed configures DAC chip DAC8420 chips, generates 0~5V voltages, and by the different amplifier in three tunnel of rear class, it is inclined to change direct current
The amplitude of voltage is put, meets the needs of a variety of EMCCD bias voltages.(4) in system hardware circuit using integrated power supply chip into
Row voltage conversion, integrated power supply chip have that efficient, low in energy consumption, noise is low, integrated level is high, be not required additional filter capacitor and
The advantages that inductance, meets the needs of industrial rank test system.(5) system can be with online programming, therefore is applicable in very strong
Property, for the EMCCD of different model, it is only necessary to design different EMCCD pedestals.(6) two are passed through on correlated-double-sampling plate
The ping-pong operation caching image data of piece SDRAM, has that capacity is big, speed is fast, the advantages such as cheap, low in energy consumption.(7) pass through
CAMERALINK communication protocols transmit digital image data, including 5 pairs of differential signals, have strong antijamming capability, transmission range
The advantages that remote.
The present invention is described in further detail below in conjunction with the accompanying drawings.
Description of the drawings
Fig. 1 is the general structure schematic diagram of the present invention.
Fig. 2 is the structure diagram of the level conversion unit of the low voltage difference level shifting circuit of the present invention.
Fig. 3 is the structure diagram of the high pressure amplifier unit of the sine-wave drive circuit of the present invention.
Fig. 4 is one structure diagram of first kind circuit DAC units of the programmable power supply circuit of the present invention.
Fig. 5 is the structure diagram of the analog front circuit of the correlated double sampling circuit of the present invention.
Fig. 6 is system signal of interest connection diagram.
Fig. 7 is the image using EMCCD chips CCD65.
Fig. 8 is the image using EMCCD chips CCD216.
Specific embodiment
With reference to Fig. 1, the universal EMCCD tests system of the present invention, including NI hosts, EMCCD device bases, serial ports switching
It is plate, differential signal pinboard, VPC series connectors, low voltage difference level shifting circuit, sine-wave drive circuit, programmable
Power circuit, backboard, correlated double sampling circuit and the power supply for the power supply of all devices.
NI hosts include CAMERALINK boards, serial ports board, NI6585 boards, and the NI6585 boards are capable of providing 16
Road differential signal output.There are the 120PIN connectors of VPC at the back side of backboard, and MDR-26 connectors, there are four 96PIN connections in front
Device female.Subrack card is connected to by the special Serial Port Lines of NI on serial ports pinboard, and the serial ports pinboard other end fixes VPC's
192PIN connectors.Likewise, 16 passage NI6585 boards are connected to differential signal pinboard by NI differential signal transmissions
On, the differential signal pinboard other end fixes the 192PIN connectors of VPC.120PIN connectors on backboard can contact pin.Two
192PIN connectors are connected to by the client cables of a VPC on the 120PIN connectors on backboard, pass through walking on backboard
Line transfers signals to modules.Power supply is provided by Agilent power supply, and including positive and negative 5V, positive and negative 15V, positive and negative 45V lead to
VPC power source special transmission lines are crossed to be connected on the 120PIN connectors on backboard, be respectively low voltage difference level shifting circuit,
Sine-wave drive circuit, programmable power supply circuit and correlated double sampling circuit provide 6 groups of power supplys.Low voltage difference level conversion electricity
Road, sine-wave drive circuit, programmable power supply circuit and correlated double sampling circuit are inserted into the back of the body by 96PIN connector male heads respectively
On 96PIN connectors on plate.The output port of low voltage difference level shifting circuit, the output port of sine-wave drive circuit
Connect 3 input ports of EMCCD device bases respectively with the output port of programmable power supply circuit, EMCCD device bases
Output port connects the input port of correlated double sampling circuit.MDR-26 connectors connection CAMERALINK boards on backboard.
The generation of EMCCD clock drive signals and pixel synchronizing signal is realized by NI LabView softwares, thus it is possible to vary transfering clock
Phase, the work period, the phase of frame frequency and pixel synchronizing signal.Low voltage difference conversion program, sine wave control program,
DC voltage control program and image acquisition procedure are write by Verilog hardware description languages.Low voltage difference conversion program
The voltage value of transfering clock can be changed.Sine wave control program can change the cycle of sine wave drive signal, phase etc.；Directly
Stream voltage control routine can change the voltage value of DC offset voltage signal；Image acquisition procedure can gather quantization in real time
EMCCD outputs signal, data buffer storage and digital data transmission.
When system works, shifted clock signal, frequency multiplied clock are generated by LabView softwares control NI6585 boards and synchronously believed
Number and pixel synchronizing signal, and all clock signals are transmitted in the form of LVDS, and the interference by noise is smaller.Wherein,
Shifted clock signal is transmitted to low voltage difference level shifting circuit, frequency multiplied clock synchronous transmission of signal to sinewave circuit, as
Plain synchronous transmission of signal is to correlated double sampling circuit.
By the control program of LabView software modification NI6585 boards, change the sequential relationship that board exports signal, so as to
The running parameters such as work period, frame frequency, the phase of the clock signal of EMCCD can be set.
Program is controlled by serial ports, sine-wave clock can be set to drive between other transfering clocks with serial ports assistant
Phase relation, amplitude, the selection in cycle, output channel.
Programmable power supply circuit includes FPGA unit one, DAC units one, amplifying unit, TVS pipe protection location, electronic cutting
It closes.The FPGA unit one connects 3 DAC units one, and each DAC units one connect an amplifying unit, which connects
4 electronic switches are connect, each electronic switch is connected by connector with EMCCD device bases, so as to form 3 group of 12 paths.TVS
Protection of pipe unit is connected to the output terminal of electronic switch.
DAC units one generate analog voltage according to the control signal and reference voltage of the FPGA unit one received, pass through
The input pin of electronic switch is connected to after the gain of rear class proportion operational amplifier, electronic switch is given according to FPGA unit one
Enable signal come control switch.The output of electronic switch is connected to male connector DB25, is the non-screen of female DB25 by both ends
Cable transmission is covered to EMCCD device bases.The rs 232 serial interface signal of serial ports board output is sent to the input terminal of programmable power supply circuit
Mouthful, FPGA unit one is connected to, control FPGA unit one configures DAC units one, and voltage output is defeated to different amplifier modules
Enter pin, obtain the DC voltage for meeting EMCCD device job requirements, send to the output port of DC offset voltage circuit.It is logical
Damage of the TVS pipe protection location from various surge pulses is crossed, electronic switch control is per break-make all the way.
Programmable power supply circuit can generate the voltage of three classes scope altogether in the present invention, be respectively -10~+10V ,+5~+
20V ,+7.5~+30V, with reference to Fig. 4, the chip selection of DAC units one is that 4 passage of ADI companies exports, 12 DAC chips
DAC8420, FPGA unit one configure its output voltage according to rs 232 serial interface signal.The reference voltage of the chip is respectively+
2.5V and+10V, programmable output voltage range are+2.5~10V, and the choosing of rear class amplifier chip is TI companies high-precision low noise
Amplifier, input voltage can export+7.5~+30V after scale operation in the same direction amplification, and what electronic switch was selected is
ADI companies cmos analog switch passes through the break-make for the enable signal control passage that FPGA unit one is given.Other two classes DAC chips
Reference voltage be+2.5V and+10V, -10V and+10V.Amplifier amplification range is 2 times and 1 times respectively, therefore generates voltage model
Enclose respectively+5~+20V, -10~+10V.The scope of above-mentioned three classes voltage almost meets all EMCCD chip bias voltages
Job requirement.
Low voltage difference level shifting circuit includes FPGA unit two, LVTTL turns TTL units, voltage conversion unit, amplification
Unit and DAC units two.FPGA Unit bis- connect 4 DAC units two, wherein 2 DAC units two generate 16 tunnel low levels
Voltage, voltage range are -5~0V, connect a low level amplifying unit per road voltage, voltage range is after amplifying unit
0~15V；Other 2 DAC units two generate high level voltage, and voltage range is 0~5V, and a high level is connected per road voltage
Amplifying unit, voltage range is 0~15V after amplifying unit.LVTTL, which turns TTL units, can export 16 road TTL signals, TTL
Signal inputs FPGA unit two.TTL signal, all the way high level voltage and low level voltage is connected to voltage conversion list all the way all the way
Member, the 40PIN for generating EMCCD shifted clock signals to AMP shield plug-in unit, EMCCD devices are connected to by the dedicated shielded cables of AMP
Part pedestal.
During work, FPGA unit two first has to the differential signal that NI6585 boards export being converted into single-ended signal, then will
Single-ended signal, which is sent to LVTTL, turns TTL units, generates TTL signal and send to level conversion unit.In addition, FPGA unit two also needs root
16 road high level voltages and 16 road low level voltages are generated according to rs 232 serial interface signal configuration DAC units two, 32 road voltages are using amplification
It is sent after unit to level conversion unit.With reference to Fig. 2, the level conversion unit of low voltage difference level shifting circuit of the invention makes
It is formed with EL7156 chips and LM7171 amplifier chips.The amplification factor of wherein positive voltage amplifier chip is 3 times, i.e. positive voltage
Scope is 0~15V；The amplification factor of negative voltage amplifier chip is 1 times, i.e. the scope of negative voltage is -5~0V.1 He of EL7156
5 pins connect high level, and 7 and No. 8 feet connect low level.Input clock accesses No. 3 feet of EL7156, the frequency of input clock 1M~
20M, within the working range of EL7156.Output clock is connected on No. 6 feet of EL7156, export clock low and high level and two
The output of amplifier determines.The amplitude of oscillation can reach 16.5V, almost meet all EMCCD job requirements.
Sine-wave drive circuit includes FPGA unit three, DAC units three, low pressure amplifier unit and high pressure amplifier unit.Institute
It states FPGA unit three and connects 2 DAC units three, each DAC units three connect a low pressure amplifier unit, low pressure amplifier unit
Output is connected to high pressure amplifier unit, and high pressure amplifier unit is connected again with a SMA connector, by cable by sine wave signal
It is output to EMCCD device bases.The difference control signal of NI6585 boards output is sent to the input terminal of sine-wave drive circuit
Mouthful, control FPGA unit three generates digital signal.In addition the rs 232 serial interface signal of serial ports board enters the input pin of FPGA unit three,
FPGA unit three is controlled to export 14 trapezoidal wave digital signals according to sinusoidal wave searching meter, it is defeated that DAC units three carry out analog-to-digital conversion
Go out to simulate trapezoidal wave signal, into first order amplifier unit filtering after export sine wave, by rear class high pressure amplifier unit export
To clamping unit, the sine wave drive signal for meeting EMCCD device job requirements is obtained, is sent to the output of sine-wave drive circuit
Port.
During work, FPGA unit three receives NI6585 board frequency multiplied clock synchronizing signals, starts to generate digital signal, and
FPGA unit three controls phase and the cycle of digitized sine wave according to rs 232 serial interface signal, is transferred to rear class D/A conversion unit, digital-to-analogue
Converting unit generates corresponding output according to reference voltage and the coding of digital signal, that is, exports a trapezoidal wave, and amplitude exists
2.5V left and right.First order low-voltage amplifier unit is mainly filtered trapezoidal wave signal amplification, obtains a smooth sine
Ripple, amplitude is in 4.5V or so.Second level high pressure amplifier unit is amplified the amplitude of sine wave, and amplification factor is 10 times, warp
It crosses clamping unit and obtains the sine wave signal for meeting EMCCD job requirements afterwards, amplitude about in 4~45V, passes through SMA connectors
It is connected to EMCCD device bases.With reference to Fig. 3, the amplifier unit of sine-wave drive circuit uses high pressure amplifier chip in the present invention.
The circuit structure is as follows：Chip use+45V and -45V dual power supplies, prime input signal after R98 and R99 by arriving
The input pin of high pressure amplifier chip adjusts the size of input voltage by resistance R100 in parallel.Waveform output terminal passes through
R104 resistance, the network-feedback of C159, C160, C163 parallel connection are conducive to the stable sine wave of output to input terminal.Pass through D21
By last output waveform clamper in more than 2V, clamp voltage is generated clamp diode by voltage-stabiliser tube, and it is mono- that FPGA unit three configures DAC
Member three generates 0V~5V clamp voltages, and the sine wave after clamper meets EMCCD frequency multiplied clock requirements.
EMCCD device bases include Dai Weinan termination units, EMCCD devices and emitter follower unit.EMCCD devices bottom
Seat placed the AMP connectors, DB25 connectors and two SMA connectors of 40PIN.Wherein, a SMA connector is used to connect
Sine-wave drive circuit；Another SMA connector connects correlated double sampling circuit.Meanwhile pass through 25PIN unmasked cable and can
Power circuit connection is programmed, is connected by 40PIN AMP shielded cables with low-voltage differential signal circuit.Low voltage difference level
The output signal of conversion circuit, programmable power supply circuit and sine-wave drive circuit is sent to EMCCD devices by cable carry on the back respectively
The input port of plate；Programmable bias voltage is then output to the transfer bias input pin of EMCCD devices.The figure of EMCCD outputs
Picture signal is output to correlated double sampling circuit by emitter follower unit.
Increase build-out resistor on the transmission line of signal, prevent clock signal in transmission process since impedance mismatch draws
Play the reflection of signal.Increase a Transient Suppression Diode at the power pin of EMCCD chips, prevent voltage from spike occur and leading
Cause chip breakdown.Under the common driving of horizontal transfer clock and vertical transfer clock, EMCCD output square wave analog signals.Width
Value is approximately 0~500mV.Since the process in transmission line has dielectric loss, so a reading can be added in EMCCD output signal ends
Go out circuit, reading circuit is mainly made of emitter follower, and emitter follower is a flow control flow pattern device, can be increased defeated
The driving force gone out, and late-class circuit and EMCCD output terminals are isolated, avoid the introducing of late-class circuit noise.
Correlated double sampling circuit includes FPGA unit four, analog front-end unit, SDRAM unit and CAMERALINK units.
The FPGA unit four is the core of correlated double sampling circuit, and analog front-end unit, SDRAM unit, CAMERALINK units are equal
It is connected with FPGA unit four.In addition, analog front-end unit is connected with SMA connectors, for gathering EMCCD picture signals；
CAMERALINk units are connected with 96PIN connectors, and the data-signal collected is transmitted to by 96PIN connectors on backboard
MDR-26 connectors, so as to by data signal transmission to CAMERALINK capture cards, transmission data-signal and be implemented as picture.
Analog front-end unit quantifies the ccd image signal of acquisition EMCCD device base outputs, outputs signals to FPGA unit four, passes through
CAMERALINK units are output to after two panels SDRAM caching image datas, CAMERALINK element output signals are connected to
It on 96PIN connectors, is connected to by the cabling on backboard on MDR-26 connectors, image data is transmitted by CAMERALINK
Line is connected on CAMERALINK boards.
During work, analog front-end unit carries out AC coupled, direct current recovery, preposition amplification, signal to EMCCD picture signals
6 groups of differential signals are generated after correlated-double-sampling, level signal amplification, analog-to-digital conversion, including 4 groups of data-signals and 2 groups of clock letters
Number, there is very strong antijamming capability.FPGA unit four receives the pixel synchronizing signal from NI6585 boards, and control FPGA is mono-
Member four receives effective viewdata signal, and two panels SDRAM unit is as Installed System Memory.With reference to Fig. 5, correlation of the invention is double to adopt
The sampling A/D chip that the analog front-end unit of sample circuit is selected is LM98640, which is the binary channels of TI companies, 14 40MSPS
AFE(analog front end) and the chip of LVDS outputs.The EMCCD chips exported for single channel and binary channels, it is only necessary to be added at bouncing pilotage
Corresponding jump cap.The sample clock frequency of the chip is divided in 5~40Mhz, sampling clock by the PLL of FPGA unit four
It arrives.Operating voltage is arranged to 3.3V, is communicated by SPI protocol and FPGA unit four, is SCLK, SDI, SDO, SEN respectively
Four lines, FPGA unit four can write data to configure chip operation by each register the inside toward LM98640.
The LVDS signals exported after LM98640 samplings, are not easy to be disturbed by outer signals, have very strong reliability.FPGA unit four-way
It crosses TXCLK and TXFRM samples data, serioparallel exchange is completed in FPGA unit four, coordinate FIFO IP kernels and SDRAM
It is rapidly completed image data caching.
The system signal trend of the present invention is as shown in Figure 6.Mainly include some rs 232 serial interface signals, EMCCD clock signals are synchronous
Signal and some debugging signals.The vertical transfer clock signal and horizontal transfer clock signal of EMCCD is by EMCCD chip handbooks
It writes.Sine wave trigger signal is according to EMCCD chips handbook and considers that the delay of transmission line provides afterwards.According to horizontal transfer
Clock signal, the delay of estimation transmission line and the delay of analog front circuit, provide the pixel synchronizing signal on correlated-double-sampling plate
And frame synchronizing signal.Above-mentioned signal is provided by NI6585 boards, is all that corresponding circuits are transferred in the form of differential signal
With reference to Fig. 7 and Fig. 8, imaging effect of the invention is as shown in the figure, the EMCCD models CCD65 that Fig. 7 is used；Fig. 8's
EMCCD models CCD216.Two pictures illustrate that the present invention can test different model EMCCD.
The present invention realizes universal EMCCD tests system, i.e. NI6585 on the basis of above-mentioned hardware circuit and NI boards
Board sends horizontal transfer clock signal and vertical transfer clock signal to low voltage difference level shifting circuit, turns through oversampling circuit
EMCCD chips are driven after changing.Rs 232 serial interface signal is sent to low-voltage differential signal plate by NI hosts, output clock letter can be changed
Number low and high level.Likewise, rs 232 serial interface signal can change the voltage of programmable power supply circuit output.Sine-wave drive circuit institute
The pixel synchronizing signal that the timing synchronization signal and correlated-double-sampling plate needed needs also is provided by NI6585 boards.To sum up institute
It states, which has very strong versatility, and the EMCCD chips that can be directed to different model set different running parameters, you can
Can the EMCCD chips be tested work normally and its imaging performance is analyzed.
Claims (6)
1. a kind of universal EMCCD test system, it is characterised in that including NI hosts, EMCCD device bases, serial ports pinboard,
Differential signal pinboard, VPC series connectors, low voltage difference level shifting circuit, sine-wave drive circuit, programmable power supply
Circuit, backboard, correlated double sampling circuit and power supply；
NI hosts include NI6585 boards, CAMERALINK boards and serial ports board, NI6585 boards and differential signal pinboard
Connection, serial ports board are connected with serial ports pinboard, and serial ports pinboard, differential signal pinboard connect respectively with VPC series connectors
It connects, VPC series connectors are connected to backboard；Wherein, 4 serial ports are shared on serial ports board, control low voltage difference level respectively
Conversion circuit, sine-wave drive circuit, programmable power supply circuit, correlated double sampling circuit；Low voltage difference is secured on backboard
Level shifting circuit, sine-wave drive circuit, programmable power supply circuit, correlated double sampling circuit, and fixed four on backboard
A circuit is connected by cable with EMCCD device bases；One MDR-26 connector of placement on the backboard, is used for
The connection of CAMERALINK boards.
2. universal EMCCD tests system according to claim 1, it is characterised in that programmable power supply circuit includes FPGA
Unit one, DAC units one, amplifying unit, TVS pipe protection location, electronic switch, the FPGA unit one connect 3 DAC units
One, each DAC units one connect an amplifying unit, which connects 4 electronic switches, and each electronic switch passes through connection
Device is connected with EMCCD device bases, so as to form 3 group of 12 paths；TVS pipe protection location is connected to the output of electronic switch
End；
DAC units one generate analog voltage according to the control signal and reference voltage of the FPGA unit one received, by rear class
The input pin of electronic switch is connected to after the gain of proportion operational amplifier, electronic switch makes according to what FPGA unit one was given
Energy signal switchs to control；The output of electronic switch is connected to male connector DB25, is the unmasked line of female DB25 by both ends
Cable is transferred to EMCCD device bases.
3. universal EMCCD tests system according to claim 1, it is characterised in that low voltage difference level shifting circuit
Turn TTL units, voltage conversion unit, amplifying unit and DAC units two, the FPGA unit two including FPGA unit two, LVTTL
4 DAC units two are connected, wherein 2 DAC units two generate 16 road low level voltages, voltage range is -5~0V, per road voltage
A low level amplifying unit is connected, voltage range is 0~15V after amplifying unit；Other 2 DAC units two generate height
Level voltage, voltage range are 0~5V, and a high level amplifying unit, the voltage model after amplifying unit are connected per road voltage
It encloses for 0~15V；LVTTL, which turns TTL units, can export 16 road TTL signals, TTL signal input FPGA unit two；TTL believes all the way
Number, high level voltage and low level voltage is connected to voltage conversion unit all the way all the way, generate EMCCD shifted clock signals and arrive
The 40PIN shielding plug-in units of AMP, EMCCD device bases are connected to by the dedicated shielded cables of AMP.
4. universal EMCCD tests system according to claim 1, it is characterised in that sine-wave drive circuit includes FPGA
Unit three, DAC units three, low pressure amplifier unit and high pressure amplifier unit, the FPGA unit three connect 2 DAC units three, often
A DAC units three connect a low pressure amplifier unit, and the output of low pressure amplifier unit is connected to high pressure amplifier unit, high pressure amplifier
Unit is connected again with a SMA connector, and sine wave signal is output to EMCCD device bases by cable.
5. universal EMCCD tests system according to claim 1, it is characterised in that EMCCD device bases include wearing dimension
Southern termination unit, EMCCD devices and emitter follower unit, EMCCD device bases placed AMP connectors, the DB25 of 40PIN
Connector and two SMA connectors；Wherein, a SMA connector is used to connect sine-wave drive circuit；Another SMA connection
Device connects correlated double sampling circuit；Meanwhile connected by 25PIN unmasked cable with programmable power supply circuit, pass through 40PIN
AMP shielded cables are connected with low-voltage differential signal circuit.
6. universal EMCCD tests system according to claim 1, it is characterised in that correlated double sampling circuit includes FPGA
Unit four, analog front-end unit, SDRAM unit and CAMERALINK units, the FPGA unit four is correlated double sampling circuit
Core, analog front-end unit, SDRAM unit, CAMERALINK units are connected with FPGA unit four；Analog front-end unit with
SMA connectors are connected, for gathering EMCCD picture signals；CAMERALINk units are connected with 96PIN connectors, will collect
Data-signal MDR-26 connectors on backboard are transmitted to by 96PIN connectors, so as to which data signal transmission be arrived
CAMERALINK capture cards transmit data-signal and are implemented as picture.
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