CN103763484A - Imaging and data transmission system of EMCCD camera - Google Patents
Imaging and data transmission system of EMCCD camera Download PDFInfo
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Abstract
The invention relates to an imaging and data transmission system of an EMCCD camera and belongs to the field of high-speed low-noise low-level light imaging technologies. The imaging and data transmission system comprises a Dewar flask interior circuit board, a clock driving circuit board and an imaging control and transmission circuit board. The Dewar flask interior circuit board comprises an EMCCD and a pre-amplifier. The clock driving circuit board comprises a level switching circuit and a clock driver. The imaging control and transmission circuit board comprises an FPGA, a peripheral circuit, an analog signal processor and a CameraLink interface circuit. The imaging and data transmission system can enable the EMCCD to carry out high-speed low-noise low-level light imaging at low temperature and transmits obtained low-level light image data to an image work station in real time; the transmitted image data can be original data and can also be corrected data processed by the FPGA in real time.
Description
Technical field
The present invention relates to a kind of EMCCD camera imaging and data transmission system, be especially applicable to the astronomy CCD camera imaging system based on Camera Link interface, belong to high-speed low-noise low-light level imaging technical field.
Background technology
Electron multiplication CCD(is designated as EMCCD conventionally) be a kind of low-light level imaging device with high speed readout ability, can at CCD chip internal, amplify faint light electronic signal.The difference of it and normal CCD is except having common serial shift register (being horizontal register), has also increased hundreds of and has adopted a high pressure clock and ordinary clock to combine the serial shift register driving.Under suitable high pressure clock driving effect, each assembled unit has certain electron avalanche ability.Like this, faint photoelectron signal is during by the output of this register, can amplify hundreds of to several thousand even up to ten thousand times.So it is very little that noise is read in the equivalence of whole ccd image, be approximately " zero noise ".Such serial shift register, is called as electron multiplication register.A hundreds of electron multiplication register has just formed an electron multiplication passage that is different from conventional CCD.Because every grade of avalanche multiplication is a random process, for an electronics input, after doubling register, output electron amount is a random number, but it obeys certain statistical law.Use when gain multiplication, it has some differences with operating state and the external characteristic of conventional CCD, is mainly manifested in voltage multiplication clock and the characteristic that doubles.Therefore, need a set of stable imaging and data transmission system.
Summary of the invention
The problem that the present invention solves is: a kind of EMCCD camera imaging and data transmission system are provided, effectively to control imaging process at low temperatures of EMCCD (as zero clearing, exposure, photoelectric image conversion, image are read, image analog-to-digital conversion), and by obtained digital picture high-speed transfer to image workstation.
Technical solution of the present invention is: a kind of EMCCD camera imaging and data transmission system, comprise Dewar bottle interior circuit board (being A plate), clock driver circuit plate (being B plate), imaging control and transmission circuit plate (being C plate), described clock driver circuit plate, imaging control and transmission circuit plate snap together from top to bottom by connector, Dewar bottle interior circuit board and clock driver circuit plate, imaging control is connected by wire and Dewar bottle vacuum socket with transmission circuit plate, preamplifier in Dewar bottle interior circuit board is connected by shielded signal line with the back buffer amplifier in transmission circuit plate with imaging control, imaging control is connected with the clock buffer in clock driver circuit plate with the FPGA timing sequencer in transmission circuit plate, clock driver in clock driver circuit plate is connected with current buffer with the resistance-capacitance network in Dewar bottle interior circuit board respectively with vacuum plug by wire, integrated linear voltage-stabilized power supply circuit in clock driver circuit plate was both connected with the electric source filter circuit in Dewar bottle interior circuit board, also be connected with digital power filter circuit with the analog power filter circuit in transmission circuit plate with imaging control.
Described Dewar bottle interior circuit board comprises electric source filter circuit, EMCCD device, loading resistor and block capacitor, preamplifier, resistance-capacitance network, current buffer, electric source filter circuit and EMCCD device, current buffer is connected with preamplifier, electric source filter circuit by vacuum socket with from the input power of clock driver circuit plate, be connected, EMCCD device is vertical, horizontal input end of clock drives clock to be connected by resistance-capacitance network and vacuum socket with the input from clock driver circuit plate, current buffer passes through vacuum socket and is connected from the vertical clock of clock driver circuit plate, EMCCD device simulation signal output part connects the loading resistor of 2.2k Ω, EMCCD device simulation signal output part is connected with block capacitor, to remove the DC component in video voltage signal, block capacitor is connected with the preamplifier that operational amplifier OPA642 forms, EMCCD device adopts the IMPACTRON CCD device of TI company, the analog video signal of CCD output, through block capacitor, enter the preamplifier being formed by operational amplifier OPA642.
Described clock driver circuit plate comprises integrated linear voltage-stabilized power supply circuit, level shifting circuit, clock buffer, clock driver, integrated linear voltage-stabilized power supply circuit comprises fixing and adjustable integrated linear voltage-stabilized power supply circuit and corresponding magnetic bead capacitor filter, level shifting circuit comprises the power circuit that different voltage levvls are provided that multiple integrated operational amplifiers form, clock driver comprises vertical clock, the drive circuit of horizontal clock and high pressure frequency multiplied clock, clock driver respectively with clock buffer, level shifting circuit connects, integrated linear voltage-stabilized power supply circuit respectively with level shifting circuit, clock buffer, clock driver connects, the vertical clock of clock driver output is connected with Dewar bottle interior circuit board current buffer, the horizontal clock of clock driver output, high pressure frequency multiplied clock is connected with Dewar bottle interior circuit board resistance-capacitance network, outside linear constant voltage dc source is connected with integrated linear voltage-stabilized power supply circuit.
Described imaging control and transmission circuit plate comprise analog power filter circuit, digital power filter circuit, back buffer amplifier, analogue signal processor, clock signal buffer, image data buffer, Camera Link interface circuit, programmable logic device FPGA and FPGA peripheral circuit, analog power filter circuit respectively with back buffer amplifier, analogue signal processor is connected with clock signal buffer, digital power filter circuit respectively with image buffers amplifier, Camera Link interface circuit, FPGA peripheral circuit is connected, back buffer amplifier, analogue signal processor, image data buffer, Camera Link interface circuit is connected successively, analogue signal processor adopts the AFE (analog front end) device AD9845B of a slice ADI company, Camera Link interface circuit comprises that Channel Link sends chip, Low Voltage Differential Signal LVDS transceiving device, the Channel Link that view data is uploaded sends chip and adopts DS90CR287, LVDS transceiving device adopts DS90LV048 and DS90LV047, Channel Link sends chip and is connected with the Camera Link image pick-up card in image workstation by Camera Link cable with LVDS transceiving device, programmable logic device FPGA comprises FPGA control logic circuit, Nios II soft nucleus CPU controller, FPGA timing sequencer and FPGA view data I/O circuit, FPGA peripheral circuit comprises master clock circuit, SRAM circuit and jtag interface circuit, FPGA control logic circuit and Nios II soft nucleus CPU controller respectively with FPGA peripheral circuit, FPGA timing sequencer, FPGA view data I/O circuit, image data buffer, Camera Link interface circuit is connected, FPGA timing sequencer is connected with analogue signal processor by clock signal buffer, the data input pin of FPGA view data I/O circuit and image data buffer is parallel-connected to analogue signal processor data output end, the data output end of FPGA view data I/O circuit and image data buffer is parallel-connected to Camera Link interface circuit data input pin, FPGA control logic circuit is connected with image workstation with outside Camera Link image pick-up card by the general serial data-interface in Camera Link interface circuit with Nios II soft nucleus CPU controller, the EMCCD of FPGA timing sequencer is vertical, horizontal output terminal of clock is connected with the clock buffer input of clock driver circuit plate, outside linear constant voltage dc source is connected with digital power filter circuit.
Equipment in described Dewar bottle interior circuit board, clock driver circuit plate, imaging control and transmission circuit plate is removed outside the gang socket, power supply base of EMCCD device and plate level signal, and other equipment are all selected the components and parts of Surface Mount encapsulation.
In the present invention, the effect of each circuit board is: Dewar bottle interior circuit board, this circuit board mainly realizes the output of EMCCD device power supply, clock access and CCD analog video signal, every the preposition amplification of direct sum.EMCCD device drives under the effect of signal with vertical, horizontal transfer clock at suitable DC offset voltage, convert optical imagery to charge image, then output amplifier and output pin thereof are sent to preamplifier with serial mode by analog video signal on sheet.The core component of this circuit is EMCCD, and the imageing sensor that camera system is used is TC285SPD, is operated under frame transfer pattern the output of single channel analog video signal.The frequency 1MHz of vertical drive clock, horizontal drive clock frequency can be set to 2.5MHz, 5MHz, 10MHz, and whole circuit is simple and practical, is suitable for the CCD imaging of frame transfer pattern.In conjunction with suitable place and route, can obtain having the low noise CCD analog output signal of certain multiplication factor.
Clock driver circuit plate: this main circuit will complete the level that the DC offset voltage of EMCCD device work is provided and drives clock signal and produce, and the 3.3V TTL signal of imaging control and output circuit output is carried out to level conversion, convert the positive and negative different level that can drive EMCCD work to.Mainly by integrated linear power module of voltage regulation, produced to the direct voltage of EMCCD device and the power supply of other device, drive the positive and negative different clock low and high level of clock signal by integrated operational amplifier circuit, to be produced.Produce and drive the circuit of EMCCD clock to be also called clock driver, clock driver is divided into vertical clock driver, horizontal clock driver and high pressure frequency multiplied clock driver.Vertical drive clock frequency is set to 1MHz, and horizontal drive clock and high pressure multiplication driving clock can choice for uses at 2.5MHz, 5MHz and 10MHz.The input clock signal of all driving clock circuits is Transistor-Transistor Logic levels of 3.3V, they are produced by the FPGA timing sequencer of imaging control and data transmission circuit plate, and by gang socket between plate, are connected to the 74AC541 clock buffer of 2 5V power supplies on clock driver circuit plate.
Imaging control and data transmission circuit plate: the course of work of this circuit board major control EMCCD, produce the needed various logic signal of EMCCD imaging, its core controller adopts Altera FPGA flush bonding processor (Nios II CPU) as core processor; Analogue signal processor is responsible for the analog video signal of back buffer amplifier output to carry out correlated double sampling (CDS) processing and AD conversion, and output image data, the initializing signal of its 3 line serial line interface and the clock signal for the processing of CCD vision signal all come from FPGA device; FPGA flush bonding processor carries out passing down of camera imaging instruction and uploading of camera status data by the general serial data-interface in Camera Link interface circuit and image workstation.The data channel of the view data collecting Camera Link interface by LVDS under the control of Nios II controller is uploaded to image workstation (or PC).The passage of uploading due to the transceiver channel of control command and view data is to separate, and can guarantee stable transfer of data real-time.
The specific implementation of EMCCD imaging control and transfer of data is as follows:
EMCCD timing sequencer.The operating process of EMCCD is divided into three states: zero clearing, expose, read, and then get back to cleared condition, need to design respectively the logical sequence under these three states.According to the requirement of EMCCD specification, 90 ° of vertical clock IAG1, IAG2 phase differences, duty ratio 50%.Therefore, the vertical clock of one-period produced with 4 or doubly several reference clock cycle of 4.Vertical clock SAG1, SAG2 and vertical clock IAG1, IAG2 are similar.From EMCCD specification, horizontal clock SRG1, SRG2 and frequency multiplied clock CMG duty ratio 50%; SRG1 and SRG2 are anti-phase, approximately 60 ° of the leading SRG2 of CMG; Reset clock RST rising edge aligns with SRG1, the about 1/6(16.7% of duty ratio).Therefore, the horizontal clock of one-period need to produce with 6 or doubly several reference clock cycle of 6.Because the highest read-out speed of camera is 30MHz, so reference clock frequency at least should reach 200MHz.The clock of FPGA is selected 50MHz, so its inner phase-locked loop pll need to adopt frequency multiplication to 200 mhz or faster.Timing sequencer is subject to the control of the soft nuclear control device of Nios II.
Nios II controller.The FPGA embedded software core processor Nios II of Altera is as the core controller of camera imaging and transfer of data, by the transmitting-receiving of RS232 Interface realization control command.Receiving after camera control commands, controller will carry out the parsing of order, and controls thus timing sequencer and produce the various logic signal of Channel Link interface chip and analogue signal processor under the sequential of EMCCD different operating state and corresponding states.When two field picture when output, Nios II imaging control system need to produce the effectively effectively effectively logical signal such as SHP, SHD, PBLK, CLPOB, CLPDM of (DVAL) and control simulation signal processor of (LVAL), data of (FVAL), row of frame.
EMCCD analogue signal processor.It receives EMCCD output, the analog signal after preamplifier and buffer amplifier amplification, under the control of FPGA timing sequencer, after clamp, program control amplification, correlated double sampling, carries out analog-to-digital conversion, finally exports 12 bit digital picture signals.This components interior includes DC restoration circuit (DC Restore), correlating double sampling circuit (CDS), gain amplifying circuit (VGA), clamp circuit (Clamp Level), 12 A/D converters (ADC), relevant digital register and control circuit, power supply etc.In the design, the only processor as ccd signal with a slice AFE (analog front end) device AD9845B, can reduce the outside link of CCD analog signal processing circuit, thereby reduce as much as possible the outside noise of introducing, effectively improved the performance of CCD camera, by suitable outside, connect and arrange, can be among astronomical EMCCD camera system.
Camera Link interface circuit.This transmission interface circuit can convert parallel view data to high-speed serial signals and go out by Double-strand transmission with LVDS form, and message transmission rate is high, good in anti-interference performance.Conversion and driving from CCD analogue signal processor data image signal out through DS90CR287 chip, by connector MDR26 and Camera Link cable, be transferred in the corresponding receiving circuit of the Camera Link image pick-up card in image workstation (or PC), image pick-up card also extracts LVAD, FVAD, DVAD signal from this cable, the synchronizing signal while recovering as high speed image data.
On imaging control and transmission circuit plate, there are two independent current source circuit: analog power filter circuit and digital power filter circuit.This is that by Low noise circuit design principle, analog circuit and digital circuit should design respectively power supply circuits because the circuit on this plate is a Digital Analog Hybrid Circuits.So, analog power filter circuit is low-noise simulation circuit (back buffer amplifier, analogue signal processor and the clock signal buffer) power supply on this plate, and digital power filter circuit is digital circuit (image buffers amplifier, Camera Link interface circuit, FPGA and the peripheral circuit thereof) power supply on this plate.
The invention has the beneficial effects as follows: can make EMCCD under low temperature (100 ℃) state, carry out the low-light level imaging of high-speed low-noise, and by obtained twilight image real-time data transmission in image workstation; The view data of transmission can be initial data, can be also through the real-time correction data after treatment of FPGA.
Accompanying drawing explanation
Fig. 1 is system construction drawing of the present invention;
Fig. 2 is module connection layout of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
Embodiment 1: as shown in Figure 1-2, a kind of EMCCD camera imaging and data transmission system, comprise Dewar bottle interior circuit board, clock driver circuit plate, imaging control and transmission circuit plate, described clock driver circuit plate, imaging control and transmission circuit plate snap together from top to bottom by connector, Dewar bottle interior circuit board and clock driver circuit plate, imaging control is connected by wire and Dewar bottle vacuum socket with transmission circuit plate, preamplifier in Dewar bottle interior circuit board is connected by shielded signal line with the back buffer amplifier in transmission circuit plate with imaging control, imaging control is connected with the clock buffer in clock driver circuit plate with the FPGA timing sequencer in transmission circuit plate, clock driver in clock driver circuit plate is connected with current buffer with the resistance-capacitance network in Dewar bottle interior circuit board respectively with vacuum plug by wire, integrated linear voltage-stabilized power supply circuit in clock driver circuit plate was both connected with the electric source filter circuit in Dewar bottle interior circuit board, also be connected with digital power filter circuit with the analog power filter circuit in transmission circuit plate with imaging control.
Described Dewar bottle interior circuit board comprises electric source filter circuit, EMCCD device, loading resistor and block capacitor, preamplifier, resistance-capacitance network, current buffer, electric source filter circuit and EMCCD device, current buffer is connected with preamplifier, electric source filter circuit by vacuum socket with from the input power of clock driver circuit plate, be connected, EMCCD device is vertical, horizontal input end of clock drives clock to be connected by resistance-capacitance network and vacuum socket with the input from clock driver circuit plate, current buffer passes through vacuum socket and is connected from the vertical clock of clock driver circuit plate, EMCCD device simulation signal output part connects the loading resistor of 2.2k Ω, EMCCD device simulation signal output part is connected with block capacitor, block capacitor is connected with the preamplifier that operational amplifier OPA642 forms, EMCCD device adopts the IMPACTRON CCD device of TI company, the analog video signal of CCD output, through block capacitor, enter the preamplifier being formed by operational amplifier OPA642.
Described clock driver circuit plate comprises integrated linear voltage-stabilized power supply circuit, level shifting circuit, clock buffer, clock driver, integrated linear voltage-stabilized power supply circuit comprises fixing and adjustable integrated linear voltage-stabilized power supply circuit and corresponding magnetic bead capacitor filter, level shifting circuit comprises the power circuit that different voltage levvls are provided that multiple integrated operational amplifiers form, clock driver comprises vertical clock, the drive circuit of horizontal clock and high pressure frequency multiplied clock, clock driver respectively with clock buffer, level shifting circuit connects, integrated linear voltage-stabilized power supply circuit respectively with level shifting circuit, clock buffer, clock driver connects, the vertical clock of clock driver output is connected with Dewar bottle interior circuit board current buffer, the horizontal clock of clock driver output, high pressure frequency multiplied clock is connected with Dewar bottle interior circuit board resistance-capacitance network, outside linear constant voltage dc source is connected with integrated linear voltage-stabilized power supply circuit.
Described imaging control and transmission circuit plate comprise analog power filter circuit, digital power filter circuit, back buffer amplifier, analogue signal processor, clock signal buffer, image data buffer, Camera Link interface circuit, programmable logic device FPGA and FPGA peripheral circuit, analog power filter circuit respectively with back buffer amplifier, analogue signal processor is connected with clock signal buffer, digital power filter circuit respectively with image buffers amplifier, Camera Link interface circuit, FPGA peripheral circuit is connected, back buffer amplifier, analogue signal processor, image data buffer, Camera Link interface circuit is connected successively, analogue signal processor adopts the AFE (analog front end) device AD9845B of a slice ADI company, Camera Link interface circuit comprises that Channel Link sends chip, Low Voltage Differential Signal LVDS transceiving device, the Channel Link that view data is uploaded sends chip and adopts DS90CR287, LVDS transceiving device adopts DS90LV048 and DS90LV047, Channel Link sends chip and is connected with the Camera Link image pick-up card in image workstation by Camera Link cable with LVDS transceiving device, programmable logic device FPGA comprises FPGA control logic circuit, Nios II soft nucleus CPU controller, FPGA timing sequencer and FPGA view data I/O circuit, FPGA peripheral circuit comprises master clock circuit, SRAM circuit and jtag interface circuit, FPGA control logic circuit and Nios II soft nucleus CPU controller respectively with FPGA peripheral circuit, FPGA timing sequencer, FPGA view data I/O circuit, image data buffer, Camera Link interface circuit is connected, FPGA timing sequencer is connected with analogue signal processor by clock signal buffer, the data input pin of FPGA view data I/O circuit and image data buffer is parallel-connected to analogue signal processor data output end, the data output end of FPGA view data I/O circuit and image data buffer is parallel-connected to Camera Link interface circuit data input pin, FPGA control logic circuit is connected with image workstation with outside Camera Link image pick-up card by the general serial data-interface in Camera Link interface circuit with Nios II soft nucleus CPU controller, the EMCCD of FPGA timing sequencer is vertical, horizontal output terminal of clock is connected with the clock buffer input of clock driver circuit plate, outside linear constant voltage dc source is connected with digital power filter circuit.
Equipment in described Dewar bottle interior circuit board, clock driver circuit plate, imaging control and transmission circuit plate is removed outside the gang socket, power supply base of EMCCD device and plate level signal, and other equipment are all selected the components and parts of Surface Mount encapsulation.
Embodiment 2: as shown in Figure 1-2, a kind of EMCCD camera imaging and data transmission system, comprise Dewar bottle interior circuit board, clock driver circuit plate, imaging control and transmission circuit plate, described clock driver circuit plate, imaging control and transmission circuit plate snap together from top to bottom by connector, Dewar bottle interior circuit board and clock driver circuit plate, imaging control is connected by wire and Dewar bottle vacuum socket with transmission circuit plate, preamplifier in Dewar bottle interior circuit board is connected by shielded signal line with the back buffer amplifier in transmission circuit plate with imaging control, imaging control is connected with the clock buffer in clock driver circuit plate with the FPGA timing sequencer in transmission circuit plate, clock driver in clock driver circuit plate is connected with current buffer with the resistance-capacitance network in Dewar bottle interior circuit board respectively with vacuum plug by wire, integrated linear voltage-stabilized power supply circuit in clock driver circuit plate was both connected with the electric source filter circuit in Dewar bottle interior circuit board, also be connected with digital power filter circuit with the analog power filter circuit in transmission circuit plate with imaging control.
Described Dewar bottle interior circuit board comprises electric source filter circuit, EMCCD device, loading resistor and block capacitor, preamplifier, resistance-capacitance network, current buffer, electric source filter circuit and EMCCD device, current buffer is connected with preamplifier, electric source filter circuit by vacuum socket with from the input power of clock driver circuit plate, be connected, EMCCD device is vertical, horizontal input end of clock drives clock to be connected by resistance-capacitance network and vacuum socket with the input from clock driver circuit plate, current buffer passes through vacuum socket and is connected from the vertical clock of clock driver circuit plate, EMCCD device simulation signal output part connects the loading resistor of 2.2k Ω, EMCCD device simulation signal output part is connected with block capacitor, block capacitor is connected with the preamplifier that operational amplifier OPA642 forms, EMCCD device adopts the IMPACTRON CCD device of TI company, the analog video signal of CCD output, through block capacitor, enter the preamplifier being formed by operational amplifier OPA642.
Described clock driver circuit plate comprises integrated linear voltage-stabilized power supply circuit, level shifting circuit, clock buffer, clock driver, integrated linear voltage-stabilized power supply circuit comprises fixing and adjustable integrated linear voltage-stabilized power supply circuit and corresponding magnetic bead capacitor filter, level shifting circuit comprises the power circuit that different voltage levvls are provided that multiple integrated operational amplifiers form, clock driver comprises vertical clock, the drive circuit of horizontal clock and high pressure frequency multiplied clock, clock driver respectively with clock buffer, level shifting circuit connects, integrated linear voltage-stabilized power supply circuit respectively with level shifting circuit, clock buffer, clock driver connects, the vertical clock of clock driver output is connected with Dewar bottle interior circuit board current buffer, the horizontal clock of clock driver output, high pressure frequency multiplied clock is connected with Dewar bottle interior circuit board resistance-capacitance network, outside linear constant voltage dc source is connected with integrated linear voltage-stabilized power supply circuit.
Described imaging control and transmission circuit plate comprise analog power filter circuit, digital power filter circuit, back buffer amplifier, analogue signal processor, clock signal buffer, image data buffer, Camera Link interface circuit, programmable logic device FPGA and FPGA peripheral circuit, analog power filter circuit is connected with back buffer amplifier, analogue signal processor and clock signal buffer respectively, is these analogue signal processor part power supplies, digital power filter circuit is connected with image buffers amplifier, Camera Link interface circuit, FPGA peripheral circuit respectively, is these digital signal processing circuit power supplies, back buffer amplifier, analogue signal processor, image data buffer, Camera Link interface circuit is connected successively, analogue signal processor adopts the AFE (analog front end) device AD9845B of a slice ADI company, Camera Link interface circuit comprises that Channel Link sends chip, Low Voltage Differential Signal LVDS transceiving device, it is DS90CR287 that the Channel Link that view data is uploaded sends chip, LVDS transceiving device adopts DS90LV048 and DS90LV047, Channel Link sends chip and LVDS transceiving device being connected by Camera Link cable and Camera Link image pick-up card in image workstation, programmable logic device FPGA comprises FPGA control logic circuit, Nios II soft nucleus CPU controller, FPGA timing sequencer and FPGA view data I/O circuit, FPGA peripheral circuit comprises master clock circuit, SRAM circuit and jtag interface circuit, FPGA control logic circuit is connected with FPGA peripheral circuit, FPGA timing sequencer, FPGA view data I/O, image data buffer, Camera Link interface circuit respectively with Nios II soft nucleus CPU controller, and FPGA timing sequencer is connected with analogue signal processor by clock signal buffer, although the data input pin of FPGA view data I/O circuit and image data buffer is parallel-connected to analogue signal processor data output end, the data output end of FPGA view data I/O circuit and image data buffer is parallel-connected to Camera Link interface circuit data input pin, but under the control of Nios II soft nucleus CPU controller, FPGA view data I/O circuit is externally in high-impedance state, and image data buffer data channel is opened simultaneously, view data does not process and directly outputs in Channel Link transmission chip DS90CR287, FPGA control logic circuit is connected with image workstation with outside Camera Link image pick-up card by the general serial data-interface in Camera Link interface circuit with Nios II soft nucleus CPU controller, vertical, the horizontal output terminal of clock of FPGA timing sequencer EMCCD is connected with the clock buffer input method end of clock driver circuit plate, and outside linear constant voltage dc source is connected with digital power filter circuit.
Equipment in described Dewar bottle interior circuit board, clock driver circuit plate, imaging control and transmission circuit plate is removed outside the gang socket, power supply base of EMCCD device and plate level signal, and other equipment are all selected the components and parts of Surface Mount encapsulation.
When this embodiment is applicable to when EMCCD imaging and transmits original view data.
Embodiment 3, as shown in Figure 1-2, a kind of EMCCD camera imaging and data transmission system, comprise Dewar bottle interior circuit board, clock driver circuit plate, imaging control and transmission circuit plate, described clock driver circuit plate, imaging control and transmission circuit plate snap together from top to bottom by connector, Dewar bottle interior circuit board and clock driver circuit plate, imaging control is connected by wire and Dewar bottle vacuum socket with transmission circuit plate, preamplifier in Dewar bottle interior circuit board is connected by shielded signal line with the back buffer amplifier in transmission circuit plate with imaging control, imaging control is connected with the clock buffer in clock driver circuit plate with the FPGA timing sequencer in transmission circuit plate, clock driver in clock driver circuit plate is connected with current buffer with the resistance-capacitance network in Dewar bottle interior circuit board respectively with vacuum plug by wire, integrated linear voltage-stabilized power supply circuit in clock driver circuit plate was both connected with the electric source filter circuit in Dewar bottle interior circuit board, also be connected with digital power filter circuit with the analog power filter circuit in transmission circuit plate with imaging control.
Described Dewar bottle interior circuit board comprises electric source filter circuit, EMCCD device, loading resistor and block capacitor, preamplifier, resistance-capacitance network, current buffer, electric source filter circuit and EMCCD device, current buffer is connected with preamplifier, electric source filter circuit by vacuum socket with from the input power of clock driver circuit plate, be connected, EMCCD device is vertical, horizontal input end of clock drives clock to be connected by resistance-capacitance network and vacuum socket with the input from clock driver circuit plate, current buffer passes through vacuum socket and is connected from the vertical clock of clock driver circuit plate, EMCCD device simulation signal output part connects the loading resistor of 2.2k Ω, EMCCD device simulation signal output part is connected with block capacitor, block capacitor is connected with the preamplifier that operational amplifier OPA642 forms, EMCCD device adopts the IMPACTRON CCD device of TI company, the analog video signal of CCD output, through block capacitor, enter the preamplifier being formed by operational amplifier OPA642.
Described clock driver circuit plate comprises integrated linear voltage-stabilized power supply circuit, level shifting circuit, clock buffer, clock driver, integrated linear voltage-stabilized power supply circuit comprises fixing and adjustable integrated linear voltage-stabilized power supply circuit and corresponding magnetic bead capacitor filter, level shifting circuit comprises the power circuit that different voltage levvls are provided that multiple integrated operational amplifiers form, clock driver comprises vertical clock, the drive circuit of horizontal clock and high pressure frequency multiplied clock, clock driver respectively with clock buffer, level shifting circuit connects, integrated linear voltage-stabilized power supply circuit respectively with level shifting circuit, clock buffer, clock driver connects, the vertical clock of clock driver output is connected with Dewar bottle interior circuit board current buffer, the horizontal clock of clock driver output, high pressure frequency multiplied clock is connected with Dewar bottle interior circuit board resistance-capacitance network, outside linear constant voltage dc source is connected with integrated linear voltage-stabilized power supply circuit.
Described imaging control and transmission circuit plate comprise electric source filter circuit, back buffer amplifier, analogue signal processor, clock signal buffer, image data buffer, Camera Link interface circuit, programmable logic device FPGA and FPGA peripheral circuit, described electric source filter circuit comprises analog-and digital-two parts, and analog power filter circuit is connected with back buffer amplifier, analogue signal processor and clock signal buffer, is these analogue signal processor part power supplies, digital power filter circuit is connected with image buffers amplifier, Camera Link interface circuit, FPGA peripheral circuit, is these digital signal processing circuit power supplies, back buffer amplifier, analogue signal processor, image data buffer, Camera Link interface circuit is connected successively, analogue signal processor adopts the AFE (analog front end) device AD9845B of a slice ADI company, Camera Link interface circuit comprises that Channel Link sends chip, Low Voltage Differential Signal LVDS transceiving device, it is DS90CR287 that the Channel Link that view data is uploaded sends chip, LVDS transceiving device adopts DS90LV048 and DS90LV047, Channel Link sends chip and LVDS transceiving device being connected by Camera Link cable and Camera Link image pick-up card in image workstation, programmable logic device FPGA comprises FPGA control logic circuit, Nios II soft nucleus CPU controller, FPGA timing sequencer and FPGA view data I/O circuit, FPGA peripheral circuit comprises master clock circuit, SRAM circuit and jtag interface circuit, FPGA control logic circuit and Nios II soft nucleus CPU controller respectively FPGA peripheral circuit, FPGA timing sequencer, FPGA view data I/O, image data buffer, Camera Link interface circuit are connected, and FPGA timing sequencer is connected with analogue signal processor by clock signal buffer, although the data input pin of FPGA view data I/O circuit and image data buffer is parallel-connected to analogue signal processor data output end, the data output end of FPGA view data I/O circuit and image data buffer is parallel-connected to Camera Link interface circuit data input pin, but under the control of Nios II soft nucleus CPU controller, open FPGA view data I/O circuit access road, and image data buffer data channel is closed simultaneously, view data enters inner data processing circuit from FPGA input port, data after treatment are sent to Channel Link through output port and send in chip DS90CR287, FPGA control logic circuit is connected with image workstation with outside Camera Link image pick-up card by the general serial data-interface in Camera Link interface circuit with Nios II soft nucleus CPU controller, vertical, the horizontal output terminal of clock of FPGA timing sequencer EMCCD is connected with the clock buffer input method end of clock driver circuit plate, and outside linear constant voltage dc source is connected with digital power filter circuit.
Equipment in described Dewar bottle interior circuit board, clock driver circuit plate, imaging control and transmission circuit plate is removed outside the gang socket, power supply base of EMCCD device and plate level signal, and other equipment are all selected the components and parts of Surface Mount encapsulation.
This embodiment is applicable to when the view data of EMCCD imaging transmission correction.
By reference to the accompanying drawings specific embodiments of the invention are explained in detail above, but the present invention is not limited to above-described embodiment, in the ken possessing those of ordinary skills, can also under the prerequisite that does not depart from aim of the present invention, makes various variations.
Claims (4)
1. EMCCD camera imaging and a data transmission system, is characterized in that: comprise Dewar bottle interior circuit board, clock driver circuit plate, imaging control and transmission circuit plate, described clock driver circuit plate, imaging control and transmission circuit plate snap together from top to bottom by connector, Dewar bottle interior circuit board and clock driver circuit plate, imaging control is connected by wire and Dewar bottle vacuum socket with transmission circuit plate, preamplifier in Dewar bottle interior circuit board is connected by shielded signal line with the back buffer amplifier in transmission circuit plate with imaging control, imaging control is connected with the clock buffer in clock driver circuit plate with the FPGA timing sequencer in transmission circuit plate, clock driver in clock driver circuit plate is connected with current buffer with the resistance-capacitance network in Dewar bottle interior circuit board respectively with vacuum plug by wire, integrated linear voltage-stabilized power supply circuit in clock driver circuit plate was both connected with the electric source filter circuit in Dewar bottle interior circuit board, also be connected with digital power filter circuit with the analog power filter circuit in transmission circuit plate with imaging control.
2. EMCCD camera imaging according to claim 1 and data transmission system, is characterized in that: described Dewar bottle interior circuit board comprises electric source filter circuit, EMCCD device, loading resistor and block capacitor, preamplifier, resistance-capacitance network, current buffer, electric source filter circuit and EMCCD device, current buffer is connected with preamplifier, electric source filter circuit by vacuum socket with from the input power of clock driver circuit plate, be connected, EMCCD device is vertical, horizontal input end of clock drives clock to be connected by resistance-capacitance network and vacuum socket with the input from clock driver circuit plate, current buffer passes through vacuum socket and is connected from the vertical clock of clock driver circuit plate, EMCCD device simulation signal output part connects the loading resistor of 2.2k Ω, EMCCD device simulation signal output part is connected with block capacitor, block capacitor is connected with the preamplifier that operational amplifier OPA642 forms, EMCCD device adopts the IMPACTRON CCD device of TI company, the analog video signal of CCD output, through block capacitor, enter the preamplifier being formed by operational amplifier OPA642.
3. EMCCD camera imaging according to claim 1 and data transmission system, is characterized in that: described clock driver circuit plate comprises integrated linear voltage-stabilized power supply circuit, level shifting circuit, clock buffer, clock driver, integrated linear voltage-stabilized power supply circuit comprises fixing and adjustable integrated linear voltage-stabilized power supply circuit and corresponding magnetic bead capacitor filter, level shifting circuit comprises the power circuit that different voltage levvls are provided that multiple integrated operational amplifiers form, clock driver comprises vertical clock, the drive circuit of horizontal clock and high pressure frequency multiplied clock, clock driver respectively with clock buffer, level shifting circuit connects, integrated linear voltage-stabilized power supply circuit respectively with level shifting circuit, clock buffer, clock driver connects, the vertical clock of clock driver output is connected with Dewar bottle interior circuit board current buffer, the horizontal clock of clock driver output, high pressure frequency multiplied clock is connected with Dewar bottle interior circuit board resistance-capacitance network, outside linear constant voltage dc source is connected with integrated linear voltage-stabilized power supply circuit.
4. EMCCD camera imaging according to claim 1 and data transmission system, is characterized in that: described imaging control and transmission circuit plate comprise analog power filter circuit, digital power filter circuit, back buffer amplifier, analogue signal processor, clock signal buffer, image data buffer, Camera Link interface circuit, programmable logic device FPGA and FPGA peripheral circuit, analog power filter circuit respectively with back buffer amplifier, analogue signal processor is connected with clock signal buffer, digital power filter circuit respectively with image buffers amplifier, Camera Link interface circuit, FPGA peripheral circuit is connected, back buffer amplifier, analogue signal processor, image data buffer, Camera Link interface circuit is connected successively, analogue signal processor adopts the AFE (analog front end) device AD9845B of a slice ADI company, Camera Link interface circuit comprises that Channel Link sends chip, Low Voltage Differential Signal LVDS transceiving device, the Channel Link that view data is uploaded sends chip and adopts DS90CR287, LVDS transceiving device adopts DS90LV048 and DS90LV047, Channel Link sends chip and is connected with the Camera Link image pick-up card in image workstation by Camera Link cable with LVDS transceiving device, programmable logic device FPGA comprises FPGA control logic circuit, Nios II soft nucleus CPU controller, FPGA timing sequencer and FPGA view data I/O circuit, FPGA peripheral circuit comprises master clock circuit, SRAM circuit and jtag interface circuit, FPGA control logic circuit and Nios II soft nucleus CPU controller respectively with FPGA peripheral circuit, FPGA timing sequencer, FPGA view data I/O circuit, image data buffer, Camera Link interface circuit is connected, FPGA timing sequencer is connected with analogue signal processor by clock signal buffer, the data input pin of FPGA view data I/O circuit and image data buffer is parallel-connected to analogue signal processor data output end, the data output end of FPGA view data I/O circuit and image data buffer is parallel-connected to Camera Link interface circuit data input pin, FPGA control logic circuit is connected with image workstation with outside Camera Link image pick-up card by the general serial data-interface in Camera Link interface circuit with Nios II soft nucleus CPU controller, the EMCCD of FPGA timing sequencer is vertical, horizontal output terminal of clock is connected with the clock buffer input of clock driver circuit plate, outside linear constant voltage dc source is connected with digital power filter circuit.
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