CN104581024B - The compatible color high-definition CCD front-end video collection modules of multi-mode and implementation method - Google Patents

Abstract

The invention discloses a kind of compatible color high-definition CCD front-end video collection modules of multi-mode and implementation method：Including probe control module, electrifying timing sequence control module, A/D control modules, detector Hardware drive module, power supply module, A/D Hardware drive modules, ccd image sensor and A/D modular converters, the final IMAQ for realizing high definition high-speed CCD imaging sensor, the bit digital vision signal of four tunnel 12 is exported, so that subsequent development person carries out Digital Video Processing to it.Advantage of the present invention is：2000000,4,000,000, the ccd image sensor of 8,000,000 three kind of pixel scale it is compatible；Interior synchronization, External synchronization mode are optional；Selected ccd image sensor sensitivity is high, frame frequency is fast, noise is low；Automatic exposure, automatic gain function can be achieved；Whole module stability is high, noise is small, small power consumption；Circuit board size is small, making sheet cost is low.

Description

The compatible color high-definition CCD front-end video collection modules of multi-mode and implementation method

Technical field

The invention belongs to the compatible color high-definition CCD head end videos collection skill of visual light imaging technology, particularly multi-mode Art and implementation method.

Background technology

With the increasingly maturation of appearance and the development of CCD and CMOS technology, camera video acquisition technique has more sufficient It is progressive.From black and white to color, from common gun type camera to integral type video camera, wide dynamic, low-light (level), resolution ratio, signal to noise ratio Lifted rapidly etc. technical indicator.Since 2009, video monitoring monitored the trend pickup of high-definition monitoring from SD.Depending on The resolution ratio of frequency monitoring image is sent out from the 4CIF or D1 in SD epoch resolution ratio, about 440,000 pixels, the tv line of definition 540 Open up and reach 1080i or 720p for high-definition monitoring epoch resolution ratio, pixel is up to more than million.As digital high-definition monitors coming for epoch Face, although foreign vendor has the ability to make the finished product scheme of digital high-definition camera, but can not also be inconvenient to be directed to a variety of differences Application scenario develop a series of rear end schemes such as corresponding high definition NVR, mixing DVR, high definition decoder.External network is high The solution of clear video camera manufacturer it is supporting with low-light (level) in terms of shortcoming, cause to apply limited with sales volume, add it is artificial into This height, so holding at high price.For such phenomenon, the wound with developing " low-cost high-quality " is being sought always by domestic manufacturers New product.In addition to being greatly lowered by high-definition camera unit price, more pressing close to consumer, high-definition monitoring can also be in many-side It is that engineering business and user save expense.

Although domestic and international video monitoring manufacturer studies and provides the solution of some more ripe digital high-definition camera systems Certainly scheme, but with the development of front end CCD and cmos image sensor technology, imaging sensor speed of weeding out the old and bring forth the new constantly is carried Rise.Some imaging sensors newly developed do not obtain good marketing.Wherein cmos image sensor shines low The lower imaging performance of degree is not fully up to expectations, make its can not some specific occasions use, it is such as medical to detect and night monitoring, By contrast, ccd image sensor is more suitable for the undertaking video monitoring of the task.Truesense Imaging companies (former Kodak Company) full HD progressive scan interline transfer type ccd image sensor-KAI- of 2,000,000 pixels was proposed in 2009 02150, its high sensitivity, high frame per second output speed and low-noise structural under low-light (level) causes it to be monitored in security protection video, Industry Control and imaging of medical etc. can show one's capabilities in field.Then, the said firm has released one after another 4,000,000 Hes of homologous series again 800 pixel ccd image sensors：KAI-04050 and KAI-08050.At present, sensed for this three sections of high speed high definition ccd images The research of the video capture technology of device almost blank.

The content of the invention

It is an object of the invention to provide a kind of compatible color high-definition CCD front-end video collection modules of multi-mode and realization Method, is realized to 2,000,000 pixels, 4,000,000 pixels and 8,000,000 pixel homologous series ccd image sensor front-end video collection modules The compatibility of software and hardware, so as to realize the IMAQ of the sensor of different pixels rank.

The technical solution for realizing the object of the invention is：A kind of compatible color high-definition CCD head end videos of multi-mode are adopted Collect module, including probe control module, electrifying timing sequence control module, A/D control modules, detector Hardware drive module, confession Electric module, A/D Hardware drive modules, ccd image sensor and A/D modular converters；Detector Hardware drive module respectively with spy Device control module, power supply module and ccd image sensor connection are surveyed, A/D Hardware drive modules are powered with A/D control modules respectively Module and A/D modular converters connection, power supply module again with electrifying timing sequence control module, ccd image sensor and A/D modular converters Connection, ccd image sensor and the connection of A/D modular converters, probe control module produce ccd image sensor institute by FPGA The driver' s timing and integrated signal of need simultaneously deliver to detector Hardware drive module, are allowed to produce specific drive signal and level and send To ccd image sensor, make its normal work；Electrifying timing sequence control module controls power supply module successively to each module for power supply；A/D Control module produces suitable configuration signal and gain signal by FPGA and delivers to A/D Hardware drive modules, A/D hardware drivings The driving chip of module receives configuration signal and gain signal is driven ability amplification to it, transmits to A/D modular converters, drives Move A/D chips normal work therein；Ccd image sensor normal work produces four road analog video signals and delivers to A/D conversions Module, A/D modular converters carry out correlated-double-sampling and analog-to-digital conversion, the digital video of 4 tunnel of final output 12 to the analog video signal Signal；Wherein, probe control module includes module-synchronous mode selecting module, 2,000,000 detector driver modules, 400 Ten thousand detector driver modules, 8,000,000 detector driver modules and detector drive signal output module, 2,000,000 visit Survey device driver module, 4,000,000 detector driver modules, 8,000,000 detector driver modules respectively with module-same Step mode selecting module and the connection of detector drive signal output module, detector drive signal output module are hard with detector again Part drive module is connected, and module-synchronous mode selecting module judges that Current detector module and inside/outside are same according to host computer instruction Mode of operation is walked, and exports the corresponding signal that enables to 2,000,000,4,000,000 or 8,000,000 detector driver modules, has been received Detector drive signal needed for the corresponding module detector driver module of effect enable signal produces the module by FPGA, i.e., Driver' s timing and integrated signal, deliver to detector drive signal output module, complete correct module, the drive of accurate synchronization pattern Dynamic clock signal and integrated signal are exported to detector Hardware drive module；Electrifying timing sequence control module is produced by FPGA to be met It is required that two groups of enable signals, this enable signal output one in front and one in back to power supply module completed to each mould by power supply module The control of block electrifying timing sequence；A/D control modules include module selecting module, 2,000,000 A/D driver modules, 4,000,000 A/D and driven Dynamic program module, 8,000,000 A/D driver modules and A/D drive signal output modules, 2,000,000 A/D driver modules, 400 Ten thousand A/D driver modules, 8,000,000 A/D driver modules respectively with module selecting module and A/D drive signal output modules Connection, A/D drive signals output module is connected with A/D Hardware drive modules again, and module selecting module is sentenced according to host computer instruction Disconnected Current detector module, the corresponding signal that enables of output has been received to 2,000,000,4,000,000 or 8,000,000 A/D driver modules The register configuration of A/D chips needed for the corresponding module A/D driver modules of effect enable signal produce the module by FPGA Signal and gain signal, and A/D drive signal output modules are delivered to, complete A/D required during by correspondence module detector work Drive signal is exported to A/D Hardware drive modules.

Wherein 2,000,000 ccd image sensors, 4,000,000 ccd image sensors and 8,000,000 ccd image sensors use pad Overlay structure, it is achieved thereby that the hardware compatibility of three kinds of different pixels ccd image sensor video acquisition modules.

A kind of implementation method of the compatible color high-definition CCD front-end video collection modules of multi-mode, method and step is as follows：

It is electric in step 1, start, receive module-synchronous mode selecting module in host computer instruction, probe control module Current module and synchronous mode are judged by FPGA, output correspondence enables signal.

Step 2, electrifying timing sequence control module by FPGA produce electrifying timing sequence control signal input it is each to power supply module Power supply chip Enable Pin：EN1, EN2, the upper electric first step are first had to the VSUB electronic shutters end of ccd image sensor and ESD Electrostatic protection end provides direct current biasing：Controlled to produce the power supply chip of this two voltages with EN1, it is vertical to VCLK again after stable Driving clock direct current biasing, HCLK horizontal drive clock direct current biasings are powered：Controlled to produce the power supply of these voltages with EN2 Chip.

Corresponding module detector driver module Enable Pin in step 3, probe control module is set to ' 1 ', passes through FPGA produces each road driver' s timing signal and integrated signal met needed for corresponding module detector work：Horizontal drive signals P5、P6、P7；Vertical driving signal P1B (T)~P4B (T)；Integrated signal VSUB, these signals are defeated by detector drive signal Go out module and this group of drive signal is sent to detector Hardware drive module；Meanwhile, the corresponding module A/D in A/D control modules Drive module Enable Pin is set to ' 1 ', and producing A/D chips by FPGA configures signal SL, SDATA, SCK, clamping level signal CLPOB, blanking signal PBLK, data clock signal DATACLK, are sent to A/D hardware via A/D drive signal output modules and drive Dynamic model block.

Step 4, after power supply module normal table is powered, in detector Hardware drive module to step 3 produce level Drive signal P5, P6, P7 are driven ability amplification and drive level conversion；Simultaneously to the vertical driving signal P1B (T) of entrance ~P4B (T) is driven ability amplification and drive level conversion；Drive signal after conversion enters ccd image sensor, together When, configuration signal SL, SDATA, SCK that A/D Hardware drive modules are produced to step 3, clamping level signal CLPOB, blanking letter Number PBLK, data clock signal DATACLK are driven ability amplification and drive level conversion, and the signal after conversion enters A/D Modular converter.

Step 5, by power supply module provide burning voltage after, ccd image sensor receiving step 4 produce drive signal and Integrated signal, normal work, four-way exports analog video signal to A/D modular converters.

Step 6, by power supply module provide burning voltage after, A/D modular converters receiving step 4 produce configuration signal, pincers Bit level signal, blanking signal and data clock signal, normal work carry out phase to the 4 road analog video signals from step 5 Double sampled and analog-to-digital conversion is closed, the bit digital vision signal of 4 tunnel 12 is produced.

The present invention compared with prior art, its remarkable advantage：(1) three kind of ccd image sensor module is compatible, 2,000,000, 4000000,8,000,000 modules are optional, and interior synchronization, External synchronization mode are optional；(2) ccd image sensor sensitivity selected by is high, frame frequency Hurry up, noise it is low, highest can realize 64 frames/second image output；(3) vertical drive level reaches that -9V arrives 12V scope, can be real Existing three level change, horizontal drive rising edge is short, and instantaneous driving force is big, and horizontal drive chip can be operated in 40MHz；(4) may be used Automatic exposure, automatic gain function are realized, A/D conversion chips can be operated in 40MHz, gain ranging：6~40dB controllables；(5) Selected chip is easily manipulated, stable work in work, and whole module noise is small, small power consumption, and circuit board size is small, making sheet cost is low.

Brief description of the drawings

Fig. 1 is the CCD front-end video collection module overall structure diagrams of the present invention.

Fig. 2 is 2,000,000 detector driver module structural representations of the probe control module of the present invention.

Fig. 3 is 2,000,000 A/D driver module structural representations of the A/D control modules of the present invention.

Embodiment

The present invention is described in further detail below in conjunction with the accompanying drawings.

With reference to Fig. 1, i.e. CCD front-end video collection module overall structure diagrams of the invention, in order to realize high sensitivity, The image output of high frame per second output speed, low noise, the KAI systems of selection Truesense Imaging companies (former Kodak Company) Row ccd image sensor, be specially：2000000 pixels：KAI-02150；4000000 pixels：KAI-08050；8000000 pixels：KAI- 08050.By taking the KAI-02150 of 2,000,000 pixels as an example, KAI-02150 is 2/ that a resolution ratio is 1080p (1920 × 1080) The progressive scan interline transfer formula ccd image sensor of 3 inches of sizes, its principal character has：Noise is low, wide dynamic range, into As performance remarkably, signal reading out structure flexibly, supports 1,2 or 4 channel signals to gather simultaneously, the collection of full resolution image highest Speed can reach 64 frames/second.Spilling discharge structure in vertical direction can prevent image overexposure, and can use electronics Shutter carries out accurately spectrum assignment.KAI-02150 is when horizontal clock frequency reaches 40MHz, and its four-way output frame rate can To reach 64 frames/second, the need for fully meeting common safety monitoring.In addition, with the KAI-04050 of KAI-02150 homologous series and The valid pixel number of KAI-08050CCD imaging sensors is respectively 2336 × 1752 and 3296 × 2472, KAI-02150's On the basis of, it is possible to achieve the higher IMAQ of apparent, sensitivity, more high-end, more accurate safety monitoring can be completed and appointed Business, for the Design of Compatibility of this three sections of imaging sensors, can meet different occasions, different consumer demands.

The present invention is carried out by following module：Probe control module, electrifying timing sequence control module, A/ D control modules, detector Hardware drive module, power supply module, A/D Hardware drive modules, ccd image sensor, A/D moduluss of conversion Block, wherein, hardware circuit includes five parts：Detector Hardware drive module, power supply module, A/D Hardware drive modules, CCD figures As sensor, A/D modular converters, detector Hardware drive module is connected with ccd image sensor and power supply module respectively, A/D Hardware drive module is connected with power supply module and A/D modular converters respectively, ccd image sensor respectively with power supply module and A/D Modular converter is connected, and power supply module is connected with A/D modular converters again.Five part embodiments are as follows：

(1) detector Hardware drive module：Include 3 vertical drive chip CXD3400,4 horizontal drive chips EL7156.CXD3400：There are three level fan-out capabilities, high level can reach 15V, low level -10V, meet vertical drive chip Use requirement.EL7156：Instant drive current ability is strong, there is plurality of level scope, and rise time and fall time are short, meets The requirement of horizontal drive chip high speed.The module receives each road drive signal from probe control module, passes through chip CXD3400 produces field drive signal P1B, P2B, P3B, P4B, P1T, P2T, P3T, P4T, and row driving is produced by chip EL7156 Signal H2SL, P5, P6, P7, complete the configuration of ccd image sensor drive level and the generation of row field drive signal, and deliver to Ccd image sensor, makes ccd image sensor normal work.

(2) power supply module：Power supply module mainly completes the supply of each module voltage, it is contemplated that module for power supply quality and chip Job stability, the power supply chip of this module uses the product of LINEAR companies, reduces noise, and in circuit board hardware design During avoid interference between digital power chip and analog power chip as far as possible.Power supply module is by 3 power supply chips LT1964,3 LT1761,2 LT1963EFE and 1 LT1963EFE-3.3 compositions.Power supply module by connector reception come From-the 5V of external power source, -4V, -2V, several voltages of 3.3V, 16V, -12V, 4V, 5V.Wherein, -5V, -4V, -2V, 5V are direct Powered for the chip EL7156 in detector Hardware drive module；3.3V is directly the chip AD9945 numbers in A/D modular converters The chip in chip EL7156, CXD3400, A/D Hardware drive module in word end, detector Hardware drive module 74LVC245A powers；- 4V is converted to -2V through chip LT1964, is that ccd image sensor is powered；16V turns through chip LT1761 15V is changed to, is that ccd image sensor is powered, is ccd image sensor while producing 12V through chip LT1761 using this 15V Power supply, in addition, above-mentioned 16V is also converted to 12V by chip LT1963, it is the chip in detector Hardware drive module CXD3400 powers, and is converted to the substrate level SUB-SUB of ccd image sensor concrete numerical value and to be packed according to detector Numerical computations on box show that the 16V is also converted to XSHT voltages through chip LT1761, in being detector Hardware drive module Chip CXD3400 powers；- 12V is converted to -9V through chip LT1964, is the chip CXD3400 in detector Hardware drive module Power supply, while being also converted to the electrostatic screen level VESD of ccd image sensing；4V is converted to 3.3V through chip LT1963, is A/D Chip AD9945 analog ends in modular converter are powered.In addition, the pass of chip LT1963, LT1761, LT1964 in the module Disconnected control signal is all the electrifying timing sequence according to needed for chip, is controlled by electrifying timing sequence control module.

(3) A/D Hardware drive modules：Include chip 74LVC245A.The module receives each road from A/D control modules A/D drive signals, it is driven ability amplification, produce A/D modular converters needed for register configuration signal SCK, SDATA, SL, clamping level signal CLPOB, blanking signal PBLK, correlated-double-sampling signal SHD, SHP and clock signal DATACLK, and A/D modular converters are delivered to, so that A/D modular converter normal works.

(4) ccd image sensor：Include ccd image sensor KAI-02150：2,000,000 pixel modules of correspondence, KAI- 04050：4,000,000 pixel modules of correspondence, KAI-08050：8,000,000 pixel modules of correspondence, voltage needed for being obtained by power supply module, External optical signals are received under the effect of detector Hardware drive module, four road analog video signals is converted thereof into and is transferred to A/D Modular converter.In addition, the compatibility in order to realize hardware system, during PCB design, using by this three kinds of detector pads The method of overlapping placement.

(5) A/D modular converters：The module is made up of four AD9945 chips, receives four tunnels from ccd image sensor Analog video signal CCDINA~CCDIND, under the driving of A/D Hardware drive modules, each AD9945 chips are respectively to wherein A/D conversions are carried out all the way, and the bit digital video signal transmission of tetra- tunnels of conversion Hou 12 is subjected to digital processing to follow-up.AD9945： 40MHZ can be operated in, and there are CDS and VGA functions, use requirement is met.

In addition, KAI-02150, KAI-04050 and KAI-08050 are as high-speed CCD imaging sensor, to electrostatic ten Divide sensitivity, and each pin is also harsher to the level demand of required DC offset voltage and AC signal, so well Circuit design be to ensure the important guarantee that normally runs of module.Due to there is multichannel key signal, and numeral letter in the present invention Number, analog signal exist simultaneously, so increased using multi-layer PCB design anti-interference and ensure circuit performance.In view of into This factor, this circuit board is designed using six layer stackups.Horizontal drive chip EL7156 heat used in ccd image sensor compared with Greatly, plank overheat is easily caused, would become hard to test by high/low temperature if radiating treatment is improper.Therefore, in circuit board hardware design During use following scheme：A closure cabling for enclosing 40mils is designed in circuit board surrounding, the cabling is the earth, not with system Ground is connected, and a 0.1 μ F electric capacity is systematically connected between the earth, and the cabling is exclusively used in the radiating of this circuit board.

With reference to Fig. 2, Fig. 3, i.e., detector driver module structural representation of the invention is (with 2,000,000 pixel detectors Exemplified by driver module, 4,000,000 pixel detector driver modules and 8,000,000 pixel detector driver module principles It is identical with 2,000,000 pixel detector driver modules), A/D driver modules structural representation (drives with 2,000,000 pixel As/D Exemplified by dynamic program module, 4,000,000 pixel As/D driver modules and 8,000,000 pixel As/D driver modules principle and 2,000,000 Pixel detector driver module is identical), it is necessary to be carried out to FPGA soft after the design and making of module hardware circuit is completed Part is developed, and customization turns into the special head end video acquisition chip of the present invention.FPGA mainly needs to complete the controlling of detector, upper electricity The control of sequential, A/D control, the program structure of above three function are described as follows：

(1) probe control module：Including module-synchronous mode selecting module, 2,000,000 detector driver modules, 4000000 detector driver modules, 8,000,000 detector driver modules and detector drive signal output module, 2,000,000 Detector driver module, 4,000,000 detector driver modules, 8,000,000 detector driver modules respectively with module- Synchronous mode selecting module and detector drive signal output module connection, detector drive signal output module again with detector Hardware drive module is connected, and module-synchronous mode selecting module judges Current detector module and inside/outside according to host computer instruction Synchronous working pattern, and the corresponding signal that enables is exported to 2,000,000,4,000,000 or 8,000,000 detector driver modules, receive The corresponding module detector driver module for effectively enabling signal meets corresponding module detector work institute by FPGA generations Each road driver' s timing signal and integrated signal needed, detector driver module includes counting module, drive signal and produces mould Block, integrated signal generation module, counting module by synchronizing signal synchronous effect, it is and final according to ccd image sensor Chip data control drive signal generation module produces each driver' s timing of detector；Integrated signal generation module is received from the external world Light exposure, calculate the associated quad time, produce the integrated signal corresponding with the light exposure, input to ccd image sensor SUB pins, the above driving and integrated signal be sent to detector drive signal output module.Detector drive signal is exported Module is judged and selected according to current module, and the driving and integrated signal that enter the module are exported to detector hardware and driven Dynamic model block.

(2) electrifying timing sequence control module：The chip data requirement of the control Main Basiss CCD chip of electrifying timing sequence is to power supply Module is controlled, and the upper electric first step first has to the VSUB electronic shutters end and ESD electrostatic protections end to ccd image sensor Direct current biasing is provided, after stable again to VCLK vertical drive clocks direct current biasing, HCLK horizontal drive clock direct current biasings and APS amplifier power supply is powered.The input signal of this module is clock signal, and output signal is that power supply module enables signal, the group Enable signal and enter power supply module Enable Pin, so as to complete the control to electrifying timing sequence.

(3) A/D control modules：Including module selecting module, 2,000,000 A/D driver modules, 4,000,000 A/D drivers Module, 8,000,000 A/D driver modules, A/D drive signal output modules.2000000 A/D driver modules, 4,000,000 A/D drive Dynamic program module, 8,000,000 A/D driver modules are connected with module selecting module and A/D drive signal output modules respectively, A/ D drive signals output module is connected with A/D Hardware drive modules again, and module selecting module judges current visit according to host computer instruction Device module is surveyed, the corresponding signal that enables of output receives to 2,000,000,4,000,000 or 8,000,000 A/D driver modules and effectively enables letter Number corresponding module A/D driver modules the module is produced by FPGA needed for A/D chips register configuration signal and increasing Beneficial signal, and A/D drive signal output modules are delivered to, complete A/D drive signals required during by correspondence module detector work Export to A/D Hardware drive modules.A/D driver modules include configuration module, counting module, clamping level blanking signal mould Block, PLL modules, configuration module reception gain data produce configuration signal SCK, SL, SDATA；Counting module receiving module is selected The enable signal of module, controls clamping level signal CLPOB and blanking signal PBLK generation；PLL modules produce related pair and adopted Sample signal SHD, SHP and data clock DATACLK, above-mentioned configuration signal, clamping level signal, blanking signal, CDS signal sums A/D drive signal output modules are sent to according to clock.A/D drive signals output module is judged to current module, to defeated Enter signal to make a choice and export to A/D Hardware drive modules.

In addition, the phase requirements between CDS and horizontal drive clock it is strict and it is more difficult control, it is necessary to when writing program energy Enough using regulation phase accurate PLL, therefore, there is specific requirement to the PLL quantity that FPGA can be provided, the requirement of this module PLL is 1 enhanced PLL.

By above-mentioned embodiment, the present invention has just reached that offer one kind can select module, control synchronous mode, with steady Fixed performance and less power consumption accurately realize compatible tri- kinds of ccd image sensings of KAI-02150, KAI-04050, KAI-08050 The front-end video collection module of device, can realize automatic gain and automatic exposure, and frame frequency is high, definition is good, noise is small.

Claims (3)

1. a kind of compatible color high-definition CCD front-end video collection modules of multi-mode, it is characterised in that：Mould is controlled including detector Block, electrifying timing sequence control module, A/D control modules, detector Hardware drive module, power supply module, A/D Hardware drive modules, Ccd image sensor and A/D modular converters；Detector Hardware drive module respectively with probe control module, power supply module and Ccd image sensor is connected, and A/D Hardware drive modules are connected with A/D control modules power supply module and A/D modular converters respectively, Power supply module is connected with electrifying timing sequence control module, ccd image sensor and A/D modular converters again, ccd image sensor and A/ D modular converters are connected, and probe control module produces the driver' s timing and integrated signal needed for ccd image sensor by FPGA And detector Hardware drive module is delivered to, it is allowed to produce specific drive signal and level and delivers to ccd image sensor, makes it just Often work；Electrifying timing sequence control module controls power supply module successively to each module for power supply；A/D control modules produce conjunction by FPGA Suitable configuration signal and gain signal simultaneously deliver to A/D Hardware drive modules, and the driving chip of A/D Hardware drive modules receives configuration Signal and gain signal are driven ability amplification to it, transmit to A/D modular converters, drive the normal work of A/D chips therein Make；Ccd image sensor normal work produces four road analog video signals and delivers to A/D modular converters, and A/D modular converters are to the mould Intend vision signal and carry out correlated-double-sampling and analog-to-digital conversion, the digital video signal of 4 tunnel of final output 12；Wherein, detector control mould Block include module-synchronous mode selecting module, 2,000,000 detector driver modules, 4,000,000 detector driver modules, 8000000 detector driver modules and detector drive signal output module, 2,000,000 detector driver modules, 4,000,000 Detector driver module, 8,000,000 detector driver modules respectively with module-synchronous mode selecting module and detector Drive signal output module is connected, and detector drive signal output module is connected with detector Hardware drive module again, module-same Step mode selecting module judges Current detector module and inside/outside synchronous working pattern according to host computer instruction, and exports corresponding Signal is enabled to 2,000,000,4,000,000 or 8,000,000 detector driver modules, the corresponding module spy for effectively enabling signal is received Detector drive signal, i.e. driver' s timing and integrated signal needed for device driver module produces the module by FPGA are surveyed, is sent To detector drive signal output module, complete correct module, the driver' s timing signal and integrated signal of accurate synchronization pattern Export to detector Hardware drive module；Electrifying timing sequence control module produces satisfactory two groups of enable signals by FPGA, This enable signal output one in front and one in back completes the control to each module electrifying timing sequence to power supply module by power supply module；A/D Control module includes module selecting module, 2,000,000 A/D driver modules, 4,000,000 A/D driver modules, 8,000,000 A/D and driven Dynamic program module and A/D drive signal output modules, 2,000,000 A/D driver modules, 4,000,000 A/D driver modules, 800 Ten thousand A/D driver modules are connected with module selecting module and A/D drive signal output modules respectively, the output of A/D drive signals Module is connected with A/D Hardware drive modules again, and module selecting module judges Current detector module according to host computer instruction, exports The corresponding signal that enables receives the corresponding module for effectively enabling signal to 2,000,000,4,000,000 or 8,000,000 A/D driver modules The register configuration signal and gain signal of A/D chips needed for A/D driver modules produce the module by FPGA, and deliver to A/D drive signal output modules, complete A/D drive signals required during by correspondence module detector work and export to A/D hardware Drive module.

2. the compatible color high-definition CCD front-end video collection modules of multi-mode according to claim 1, it is characterised in that： 2000000 ccd image sensors, 4,000,000 ccd image sensors and 8,000,000 ccd image sensors use pad overlay structure, from And realize the hardware compatibility of three kinds of different pixels ccd image sensor video acquisition modules.

3. a kind of realization side of the color high-definition CCD front-end video collection module compatible based on the multi-mode described in claim 1 Method, it is characterised in that method and step is as follows：

Electric in step 1, start, the module-synchronous mode selecting module received in host computer instruction, probe control module passes through FPGA is judged to current module and synchronous mode, and output correspondence enables signal；

Step 2, electrifying timing sequence control module produce electrifying timing sequence control signal by FPGA and inputted to each power supply of power supply module Chip Enable Pin：EN1, EN2, the upper electric first step first have to the VSUB electronic shutters end and ESD electrostatic to ccd image sensor Protection end provides direct current biasing：Controlled to produce the power supply chip of this two voltages with EN1, again to VCLK vertical drive after stable Clock direct current biasing, HCLK horizontal drive clock direct current biasings are powered：Controlled to produce the power supply core of these voltages with EN2 Piece；

Corresponding module detector driver module Enable Pin in step 3, probe control module is set to ' 1 ', passes through FPGA Produce and meet corresponding module detector work required each road driver' s timing signal and integrated signal：Horizontal drive signals P5, P6, P7；Vertical driving signal P1B (T)~P4B (T)；Integrated signal VSUB, these signals pass through detector drive signal output module This group of drive signal is sent to detector Hardware drive module；Meanwhile, the corresponding module A/D driving moulds in A/D control modules Block Enable Pin is set to ' 1 ', and producing A/D chips by FPGA configures signal SL, SDATA, SCK, and clamping level signal CLPOB disappears Hidden signal PBLK, data clock signal DATACLK, A/D Hardware drive modules are sent to via A/D drive signal output modules；

Step 4, after power supply module normal table is powered, in detector Hardware drive module to step 3 produce horizontal drive Signal P5, P6, P7 are driven ability amplification and drive level conversion；Simultaneously to the vertical driving signal P1B (T) of entrance~ P4B (T) is driven ability amplification and drive level conversion；Drive signal after conversion enters ccd image sensor, meanwhile, Configuration signal SL, SDATA, SCK that A/D Hardware drive modules are produced to step 3, clamping level signal CLPOB, blanking signal PBLK, data clock signal DATACLK are driven ability amplification and drive level conversion, and the signal after conversion turns into A/D Change the mold block；

Step 5, by power supply module provide burning voltage after, ccd image sensor receiving step 4 produce drive signal and integration Signal, normal work, four-way exports analog video signal to A/D modular converters；

Step 6, by power supply module provide burning voltage after, A/D modular converters receiving step 4 produce configuration signal, clamper electricity Ordinary mail number, blanking signal and data clock signal, normal work are carried out related double to the 4 road analog video signals from step 5 Sampling and analog-to-digital conversion, produce the bit digital vision signal of 4 tunnel 12.