CN218214115U

CN218214115U - ATE equipment of extension circuit board and MCU

Info

Publication number: CN218214115U
Application number: CN202221910189.4U
Authority: CN
Inventors: 钟晓雄; 张吉红
Original assignee: Zhuhai Geehy Semiconductor Co Ltd
Current assignee: Zhuhai Geehy Semiconductor Co Ltd
Priority date: 2022-07-19
Filing date: 2022-07-19
Publication date: 2023-01-03
Anticipated expiration: 2032-07-19

Abstract

The utility model discloses an extension circuit board and MCU's ATE equipment. The extended circuit board is used for connecting the test module with the measuring device and transmitting a test result to the measuring device for analysis, and comprises the test module and a short-circuit connecting piece; the test module comprises sub test modules with different functions, and the output end of each sub test module is connected with a corresponding first connecting piece; the short circuit connecting piece is used for short circuit the first connecting piece corresponding to the sub-test module and the input end of the measuring device, and connection between the sub-test module corresponding to the first connecting piece and the measuring device is achieved. The utility model discloses an every sub-detection module is independent separately, and the mutual noninterference test just can realize being connected of sub-test module and measuring device through the first connecting piece that the sub-test module of short circuit connecting piece short circuit corresponds and measuring device's input to gather output result, the existence of the wire jumper that has significantly reduced has improved test system's stability.

Description

ATE equipment of extension circuit board and MCU

Technical Field

The utility model relates to an embedded test technical field especially relates to an extension circuit board and MCU's ATE equipment.

Background

Programmable integrated circuits, such as MCU, MPU, CPLD, FPGA, etc., are widely required to perform software simulation debugging and function test of circuit boards for the integrated circuits and the circuit boards on which the integrated circuits are mounted in application. In the testing process, multifunctional verification is required, and in the prior art, peripheral extension testing circuits with various functions are generally required to be matched with the MCU to be tested for connection testing respectively.

The prior art has the following defects:

(1) Only the external interface can be expanded and a peripheral circuit required by the test needs to be built by the user;

(2) The built peripheral circuit also needs additional connecting wires and has the problem of frequent plugging, which can directly cause the instability of the test system or be difficult to troubleshoot.

SUMMERY OF THE UTILITY MODEL

Not enough to prior art exists, the utility model aims at providing an extension circuit board and MCU's ATE equipment for need extra connecting wire and the technical problem who exists frequent plug among the solution prior art.

According to a first aspect of the present invention, there is provided an extension circuit board for connecting a test module with a measurement device and transmitting a test result to the measurement device for analysis, comprising the test module and a short connection connector;

the test module comprises sub test modules with different functions, and the output end of each sub test module is connected with a corresponding first connecting piece;

the short circuit connecting piece is used for short circuit the first connecting piece corresponding to the sub-test module and the input end of the measuring device, and connection between the sub-test module corresponding to the first connecting piece and the measuring device is achieved.

The utility model discloses an extension circuit board, every sub-test module is independent separately, and the mutual noninterference test just can realize being connected of sub-test module and measuring device through the first connecting piece that the sub-test module of short circuit connecting piece short circuit corresponds and measuring device's input to gather output result, the existence of the wire jumper that has significantly reduced has improved test system's stability.

In some embodiments, the first connector is a double pin arrangement and the shorting connector is a jumper cap or jumper.

In some embodiments, the first connection element of at least one of the sub-test modules is further configured to connect to an IO port of the MCU to be tested, and the first connection element of at least one of the sub-test modules is further configured to connect to a test host to communicate with the MCU to be tested.

In some embodiments, the sub-test modules with different functions comprise at least two of a GPIO test module, an I2C test module, an SPI test module, a CAN test module, a USART test module, and a key module.

In some embodiments, the measuring device is connected with the first connecting piece corresponding to one of the sub-test modules, and the other sub-test modules are connected with the measuring device by short-circuiting the first connecting piece corresponding to the other sub-test module with the first connecting piece connected to the measuring device through the short-circuit connecting piece, so that the sub-test modules corresponding to the other sub-test modules are connected with the measuring device.

In some embodiments, the measuring device is connected with a first connecting piece corresponding to the GPIO testing module, and the first connecting piece corresponding to the GPIO testing module is used for being connected with an IO port of the testing chip; the GPIO test module is provided with an extension connecting piece, and the extension connecting piece is used for being connected with other extension test modules so that the measuring device is connected with other extension test modules.

In some embodiments, at least one corresponding first connecting piece in the other sub-test modules is provided with a first matching connecting piece for matching with the first connecting piece, the first matching connecting piece comprises two ends in an open circuit state, the two ends of the first matching connecting piece are respectively connected with the first connecting piece connected with the measuring device and the first connecting piece matched with the first matching connecting piece, and the short circuit connecting piece realizes the connection between the sub-test module corresponding to the first matching connecting piece and the measuring device by short-circuiting the two ends of the first matching connecting piece.

In some embodiments, the device is further provided with an IO port pull-up and pull-down module, two ends of the IO port pull-up and pull-down module are respectively connected with a second connecting piece, a third connecting piece, a fourth connecting piece connected with a VCC end, and a fifth connecting piece connected with a GND end, the short-circuit connecting piece is connected with the first connecting piece connected with the measuring device through the short-circuit second connecting piece, and the short-circuit connecting piece is connected with the fourth connecting piece or the fifth connecting piece through the short-circuit third connecting piece, so that pull-up or pull-down of the IO port is realized.

In some embodiments, a second matching connecting piece matched with the second connecting piece is further arranged, the second matching connecting piece is connected with the first connecting piece connected with the measuring device, and the short circuit connecting piece realizes the pull-up or pull-down of the IO port through the short circuit second connecting piece and the second matching connecting piece.

In some embodiments, the device further comprises a sixth connecting piece and a seventh connecting piece, the sixth connecting piece is connected with the eight high bits of the first connecting piece connected with the measuring device, the seventh connecting piece is connected with the eight low bits of the first connecting piece connected with the measuring device, and the short-circuit connecting piece realizes the floating input and the push-pull output of the IO port by short-circuit the sixth connecting piece and the seventh connecting piece.

According to a second aspect of the present invention, there is provided an ATE device of MCU, comprising a test host, a measurement device and the above-mentioned extension circuit board;

the measuring device is connected with at least one sub-test module of the extended circuit board to analyze the measuring result;

the test host is connected with at least one sub-test module of the extended circuit board to communicate with the MCU to be tested.

Compared with the prior art, the utility model discloses an extension circuit board and MCU's ATE equipment, every sub test module is independent separately, and the mutual noninterference test just can realize being connected of sub test module and measuring device through the first connecting piece that the sub test module of short circuit connecting piece short circuit corresponds and measuring device's input to gather the output result, the existence of the wire jumper that has significantly reduced has improved test system's stability.

Drawings

Fig. 1 is a schematic diagram of a module composition of an extended circuit board according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a modular composition of the pin header of the extended circuit board according to an embodiment of the present invention.

The reference numbers illustrate: the testing module 100, the first connecting piece 101, the measuring device 200, the short connecting piece 300, the IO port pull-down pin header 1, the IO port pull-up pin header 2, the 3.3V pin header 3, the IO port and pull-up and pull-down resistor butt-joint pin header 4, the GPIO testing pin header 5, the GPIO reserved port pin header 51, the IO port and key butt-joint pin header 6, the IO port high 8 and low 8 butt-joint pin header 7, the I2C connection logic analyzer pin header 8, the I2C pin header 9, the SPI connection logic analyzer pin header 10, the SPI pin header 11, the serial pin header 12, the serial connection logic analyzer pin header 13, the pull-up reserved key pin header 14, the pull-down key pin header 15, the pull-up key pin header 16, the CAN connection logic analysis pin header 17, the CAN communication pin header 18, and the CAN communication pin header 19.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

According to a first aspect of the present invention, fig. 1-2 schematically show an extension circuit board according to an embodiment of the present invention. As shown in fig. 1-2, the expansion circuit board is used for connecting the test module 100 with the measurement device 200, and transmitting the test result to the measurement device 200 for analysis, and includes the test module 100 and the shorting connector 300; the test module 100 comprises sub-test modules with different functions, and the output end of each sub-test module is connected with a corresponding first connecting piece 101; the short-circuit connecting piece 300 is used for short-circuit the input ends of the first connecting piece 101 and the measuring device 200 corresponding to the sub-test module, and connection between the sub-test module corresponding to the first connecting piece 101 and the measuring device 200 is achieved. Each sub-detection module of the embodiment is independent and separate, the test is not interfered with each other, the input ends of the first connecting piece 101 and the measuring device 200 corresponding to the sub-detection module can be short-circuited through the short-circuit connecting piece 300, the sub-detection module is connected with the measuring device 200, so that the output result can be collected, the existence of jumper wires is greatly reduced, and the stability of the test system is improved.

The measurement device 200 is a logic analyzer that functions as a logic display and performs analysis and fault diagnosis of system operation.

The sub-test modules with different functions comprise a GPIO test module, an I2C test module, an SPI test module, a CAN test module, a USART test module and a key module.

The measuring device 200 is connected with the first connecting piece 101 corresponding to one of the sub-test modules, and the other sub-test modules are in short circuit with the first connecting piece 101 corresponding to the first connecting piece 101 and the measuring device 200 through the short circuit connecting piece 300, so that the sub-test modules corresponding to the other first connecting pieces 101 are connected with the measuring device 200.

The MCU to be tested is connected to a certain sub-test module through the first connector 101, and of course, an independent lead-out port can be set to access the MCU to be tested.

For better illustration, in the embodiment, the first connecting element 101 is a double-row pin structure, and the short-circuit connecting element 300 is a jumper cap or a jumper wire, where the number of single-row pins of the double-row pin structure is the same as the number of output ends of the sub-test modules, one row of pins of the double-row pin structure is connected to each sub-test module (each module test host), the other row of pins of the double-row pin structure is connected to the MCU chip to be tested, and the connection and communication between each sub-test module and the MCU chip to be tested are realized by short-connecting the two rows of pins of the double-row pin structure. Of course, in other embodiments, the first connector 101 may be a slot, the corresponding connection portion of the short-circuit connector 300 and the first connector 101 is a pin, and the connection portion of the short-circuit connector 300 and the measurement device 200 may be selected according to whether the output end of the measurement device 200 is the slot or the pin; the short-circuit connector 300 may also be a switch, two ends of the switch are respectively connected to the first connector 101 and the input end of the measurement device 200, and the connection between the sub-test module and the measurement device 200 is completed by opening or closing the switch, it should be understood that when the input ends of the measurement device 200 are multiplexed, a plurality of corresponding switches are also provided.

For better description, in the present embodiment, the measurement device 200 is connected to the GPIO TEST pin header 5 corresponding to the GPIO TEST module (i.e., the first connection device 101 corresponding to the GPIO TEST module), the GPIO TEST pin header 5 corresponding to the GPIO TEST module is used to be connected to an IO port of a TEST chip, and the TEST chip is a TEST _ MCU chip (i.e., an MCU chip to be tested). Because GPIO has 16 IO, and logic analysis appearance has 16 IO, and the GPIO test row needle 5 that corresponds is double needle, and the first row needle of GPIO test row needle 5 is connected with 16 IO of GPIO (being connected with the IO mouth of MCU chip that awaits measuring promptly), and the second row needle of GPIO test row needle 5 is connected with 16 IO of logic analysis appearance, and the first row needle of GPIO test row needle 5 is arranged the needle with the second and is connected corresponding the position. Wherein, GPIO test pin header 5 still is connected with GPIO reserved port pin header 51 (GPIO test module is provided with the extension connecting piece promptly), GPIO reserved port pin header 51 is double needle, the corresponding position of two rows of pin headers of GPIO reserved port pin header 51 is connected, the second row pin header of GPIO reserved port pin header 51 is connected with the first row pin header corresponding position of GPIO test pin header 5, when other tests need logic analyzer, be connected to one of them row pin header of GPIO reserved port pin header 51 through the jumper wire can (promptly the extension connecting piece is used for being connected so that other extension test modules are connected to the measuring device with other extension test modules). In other embodiments, the GPIO reserved port pin header 51 may be a single pin header, or a plurality of pin headers, where each pin header in the plurality of pin headers is connected to a corresponding position, and one pin header in the plurality of pin headers is connected to a corresponding position of the first pin header in the GPIO testing pin header 5.

In this embodiment, the sub-test module is further configured to be connected to a test host, and configured to communicate with the MCU to be tested, and if the serial port communication is performed, the sub-test module may be connected to the serial pin, and if the I2C communication is performed, the sub-test module may be connected to the I2C module.

The pin arrangement structure that other sub-test modules correspond (namely the first connecting piece 101 that sub-test module corresponds) is equipped with the first cooperation connecting piece of cooperation pin arrangement structure, first cooperation connecting piece is including the both ends that are the state of opening circuit, the pin arrangement structure that the both ends of first cooperation connecting piece are connected with measuring device 200 respectively, be connected with first cooperation connecting piece complex pin arrangement structure (namely the first connecting piece 101 that sub-test module corresponds), the short circuit connecting piece passes through the both ends of the first cooperation connecting piece of short circuit, realize being connected of sub-test module that the pin arrangement structure corresponds and measuring device. Specifically, other sub-test modules are I2C test module, SPI test module, CAN test module, USART test module, button module, and first cooperation connecting piece is double pin structure.

The first matching connecting piece corresponding to the key module is an IO port and key butt joint pin header 6, the IO port and key butt joint pin header 6 is an IO port and key butt joint pin header 6, the second pin header of the IO port and key butt joint pin header 6 is connected with the corresponding position of the first pin header of the GPIO reserved port pin header 51, the key module comprises an upper pull key, a lower pull key and an upper pull reserved key, the upper pull key, the lower pull key and the upper pull reserved key are respectively connected with an upper pull key pin header 16, a lower pull key pin header 15 and an upper pull reserved pin header 14, specifically, the upper pull key pin header 16 is a double pin header, the first pin header of the upper pull key pin header 16 is connected with the upper pull key, the second pin header of the upper pull key pin header 16 is connected with the IO port and the corresponding position of the first end of the key butt joint pin header 6, the lower pull key pin header 15 is a double pin header, the first pin header of the lower pull key pin header 15 is connected with the lower pull key, when testing EXTI/PWR, a jump cap is used to connect the second row pins of the pull-down key pin header 15 with the corresponding positions of the first row pins of the pull-down key pin header 15, and a jump cap is used to connect the pull-up key pin header 16/pull-down key pin header 15, and an IO port is used to connect with the pin header port corresponding to the key butt pin header 6, and the corresponding pull-down key is pressed to generate a falling edge or the pull-up key is pressed to generate a falling edge, so that the triggering test of EXTI (external interrupt) or the awakening test of PWR (low power consumption) can be realized, the pull-up key pin header 14 is a pull-up key reserved interface, when the pull-up key is pressed, a falling edge signal can be generated, and the method can be used for some special scenes, such as: a trigger signal that can be used for an external interrupt, etc.

The I2C test module corresponds to an I2C pin header 9, the I2C pin header 9 is mainly used for testing a pull-up circuit (a pull-up resistor is 4.7K) required by I2C communication, the I2C pin header 9 is a double-row pin, a first pin header of the I2C pin header 9 is connected with a corresponding position of a second pin header, a first matching connecting piece corresponding to the I2C pin header 9 is an I2C connecting logic analyzer pin header 8, the I2C connecting logic analyzer pin header 8 is a double-row pin, the first pin header of the I2C connecting logic analyzer pin header 8 is connected with a corresponding position of the second pin header of the I2C pin header 9, the second pin header of the I2C connecting logic analyzer pin header 8 is connected with a corresponding position of an IO port and a second pin header of the key butt joint pin header 6, the GPIO port and the first pin header of the key butt joint pin header 6 are connected by using a cap, and the GPIO signal acquisition of the I2C pin header can be realized by using the GPIO pin header.

The row needle that SPI test module corresponds is SPI row needle 11, SPI row needle is mainly used in testing SPI communication, SPI row needle 11 includes three groups of double-row needles, the first row needle of the first group of double-row needle of SPI row needle 11 corresponds the position with the second row needle and is connected, the first row needle of the second group of double-row needle of SPI row needle 11 corresponds the position with the first row needle of the first group of double-row needle of SPI row needle 11 and is connected, the second row needle of the second group of double-row needle of SPI row needle 11 corresponds the position with the first row needle of the third group of double-row needle of SPI row needle 11 and is connected, the first row needle of the third double-row needle of SPI row needle 11 corresponds the position with the second row needle and is connected, SPI test module corresponds first cooperation connecting piece and connects logic analysis appearance row needle 10 for SPI, SPI connection logic analysis appearance row needle 10 is for SPI row needle, SPI connection logic analysis appearance row needle is connected through SPI row needle and is connected to SPI row needle 8, SPI row needle is connected to SPI analysis appearance row needle and is connected to the use second row needle and is connected to SPI analysis appearance.

The pins corresponding to the USART test module are serial pins 12 (i.e., the first connector 101 corresponding to the USART test module), the serial pins 12 are mainly used in testing serial communication, the serial pins 12 include two sets of double pins, the second pins of the first set of double pins of the serial pins 12 are connected to the corresponding positions of the first pins of the second set of double pins of the serial pins 12, the first pins of the second set of double pins of the serial pins 12 are connected to the corresponding positions of the second pins, the first mating connector corresponding to the USART test module is a serial logic analyzer pin 13, the serial logic analyzer pin 13 is a double pin, the first pin of the serial logic analyzer pin 13 is connected to the corresponding positions of the second set of double pins of the serial pins 12, the second pin of the serial logic analyzer pin 13 is connected to the corresponding positions of the second pin of the I2C logic analyzer pin 8, GPIO signal acquisition can be performed by connecting the serial pins with the serial analyzer pin through the serial pin cap, thereby the serial pin 13 can be connected to the serial analyzer pin through the serial pin.

The pins corresponding to the CAN TEST module are CAN communication pins 18, the CAN communication pins 18 are connected with the corresponding positions of CAN _ TX and CAN _ RX, the corresponding positions of CAN _ TX and CAN _ RX of the TEST _ MCU CAN be connected with the corresponding positions of CAN communication pins 18 by using jumpers, and the TEST of the CAN module CAN be realized through the CAN module; the first matching connecting piece corresponding to the CAN testing module is a CAN connection logic analysis pin header 17, the CAN connection logic analysis pin header 17 is a double-pin header, a first pin header of the CAN connection logic analysis pin header 17 is connected with a position corresponding to a CAN communication pin header 18, a second pin header of the CAN connection logic analysis pin header 17 is connected with a position corresponding to a second pin header of a serial port connection logic analyzer pin header 13, because the GPIO testing pin header 5 is connected with the logic analyzer, a jump cap is used to connect the first pin header of the CAN connection logic analysis pin header 17 with the position corresponding to the second pin header, the CAN communication pin header 18 CAN be connected with the logic analyzer, and signals CAN be collected by using the logic analyzer. The CAN test module is also connected with a reserved CAN communication pin 19, and the CAN _ TX and CAN _ RX of the MCU CAN be correspondingly connected with the reserved CAN communication pin 19 by using a jumper wire.

The expansion circuit board is also provided with an IO port pull-up and pull-down module, two ends of the IO port pull-up and pull-down module are respectively connected with a second connecting piece, a second matching connecting piece matched with the second connecting piece, a third connecting piece, a fourth connecting piece connected with a VCC end and a fifth connecting piece connected with a GND end, the second connecting piece and the second matching connecting piece form double rows of pins (namely, the IO port is connected with the pin 4 of the pull-up and pull-down resistor in an abutting mode), the second connecting piece is a second row of pins of the pin 4 of which the IO port is connected with the pull-up and pull-down resistor in an abutting mode, the second matching connecting piece is a first row of pins of the pin 4 of which the IO port is connected with the pull-up and pull-down resistor in an abutting mode, and the first row of the pin 4 of which the IO port is connected with the pull-up and pull-down resistor in a position corresponding to the second row of the GPIO test pin 5, the IO port is connected with a first end of an IO port up-down pulling module through a second row of pins of a first row of pins of a pin 4 butted with a up-down pulling resistor, a third connecting piece comprises the first row of pins and the second row of pins, the first row of pins and a fourth connecting piece of the third connecting piece form a double row of pins (namely, IO port up-down pulling pins 2), the first row of pins of the IO port up-down pulling pins 2 are connected with a second end of the IO port up-down pulling module, the second row of pins of the IO port up-down pulling pins 2 are connected with a VCC end, the second row of pins and a fifth connecting piece of the third connecting piece form an IO port down-down pulling pins 1, the first row of pins of the IO port down-down pulling pins 1 are connected with the position corresponding to the first row of the IO port up-down pulling pins 2, and the second row of the IO port down-down pulling pins 1 is connected with a GND end; the IO port pull-down pin header 1 is a pin header reserved for pulling down an IO port and a pin header 4 butted with a pull-up resistor, the corresponding positions of a first pin header and a second pin header of the IO port pull-down pin header 1 can be connected by using a jumper or a jumper cap, the IO port and the pin header 4 butted with the pull-up resistor can be pulled down, a GPIO has a special mode to be pulled down, the IO port and the pin header 4 butted with the pull-up resistor are provided with pull-down pins, the second pin header of the pin header 4 butted with the IO port and the pull-up resistor is connected with the corresponding position of the first pin header by using the jumper or the jumper cap, and the corresponding GPIO of a TEST _ MCU chip can be pulled down; the IO port pull-up pin 2 is a pin which pulls up the pin 4 (the pull-up resistor is 10K) with the IO port and the pull-up resistor in butt joint, a jumper or a jump cap can be used for connecting the corresponding positions of the first pin and the second pin of the IO port pull-up pin 2, and the second pin of the pin 4 with the IO port and the pull-up resistor in butt joint is connected with the corresponding position of the first pin through the jumper or the jump cap, so that the test of the MCU open-drain mode output is realized. The VCC end is also connected with a reserved 3.3V pin header 3, and the reserved 3.3V pin header 3 can be used for power supply of some external modules (external test module communication modules and the like). Certainly, in other embodiments, a jumper or a jumper cap may be directly used to connect the second row of pins of the pin header 4 where the IO port is butted with the pull-up and pull-down resistor and the corresponding position of the second row of pins of the pin header 4 where the IO port is butted with the pull-down and pull-up resistors, and the jumper or the jumper cap connects the corresponding position of the first row of pins and the corresponding position of the second row of pins of the pin header 2 of the IO port or connects the corresponding position of the first row of pins and the corresponding position of the second row of pins of the pin header 1 of the IO port, so as to implement pull-up or pull-down of the IO port.

The extension circuit board further comprises a sixth connecting piece and a seventh connecting piece, the sixth connecting piece is connected with the eight high bits of the GPIO test pin header 5, the seventh connecting piece is connected with the eight low bits of the GPIO test pin header 5, and floating input and push-pull output of an IO port are achieved by using a jumper or a jumper cap through short-circuit of the sixth connecting piece and the seventh connecting piece. Specifically, the sixth connecting piece and the seventh connecting piece form an IO port high 8-bit and low 8-bit butt joint pin header 7, the IO port high 8-bit and low 8-bit butt joint pin header 7 is a double-row pin header and is mainly used for testing floating input and push-pull output of an IO port, when the jump cap is used for connection, low eight bits and high eight bits of the IO port can be connected, high eight-bit push-pull output can be tested through low eight-bit floating input, and a function of mutual testing of high and low bits is achieved.

According to a second aspect of the present invention, there is provided an ATE device of MCU, which comprises a test host, a measurement device and the above-mentioned extension circuit board; the measuring device is connected with at least one sub-test module of the extended circuit board to analyze the measuring result; the test host is connected with at least one sub-test module of the extended circuit board to communicate with the MCU to be tested.

What has been described above are only some embodiments of the invention. For those skilled in the art, without departing from the inventive concept, several modifications and improvements can be made, which are within the scope of the invention.

Claims

1. An expansion circuit board for connecting a test module with a measurement device and transmitting a test result to the measurement device for analysis, comprising:

and the short circuit connecting piece is used for short circuit of the first connecting piece corresponding to the sub-test module and the input end of the measuring device, so that the sub-test module corresponding to the first connecting piece is connected with the measuring device.

2. The extension circuit board of claim 1, wherein the first connector is a double pin arrangement and the shorting connector is a jumper cap or jumper.

3. The extension circuit board of claim 2, wherein the first connector of at least one of the sub-test modules is further configured to connect to an IO port of an MCU to be tested, and the first connector of at least one of the sub-test modules is further configured to connect to a test host to communicate with the MCU to be tested.

4. The extension circuit board of claim 1 or 2, wherein the sub-test modules with different functions comprise at least two of a GPIO test module, an I2C test module, an SPI test module, a CAN test module, a USART test module, and a key module.

5. The extension circuit board of claim 4, wherein the measurement device is connected to the first connecting member corresponding to one of the sub-test modules, and the other sub-test modules are connected to the measurement device by shorting the first connecting member corresponding to the other sub-test modules to the first connecting member connected to the measurement device via the shorting connecting member.

6. The expansion circuit board according to claim 5, wherein the measurement device is connected with the first connector corresponding to the GPIO test module, and the first connector corresponding to the GPIO test module is used for being connected with an IO port of an MCU to be tested; the GPIO test module is provided with an extension connecting piece, and the extension connecting piece is used for being connected with an extension test module so that the measuring device is connected with the extension test module.

7. The extension circuit board of claim 6, wherein at least one corresponding first connector of the other sub-test modules is provided with a first mating connector for mating with the first connector, the first mating connector includes two ends in an open circuit state, the two ends of the first mating connector are respectively connected with the first connector of the measurement device and the first connector mated with the first mating connector, and the short circuit connector realizes connection between the sub-test module corresponding to the first mating connector and the measurement device by short-circuiting the two ends of the first mating connector.

8. The extension circuit board of any one of claims 6 or 7, further comprising an IO port pull-up and pull-down module, wherein two ends of the IO port pull-up and pull-down module are respectively connected with a second connecting piece, a third connecting piece, a fourth connecting piece connected with a VCC end, and a fifth connecting piece connected with a GND end, the short-circuit connecting piece is connected with the first connecting piece connected with the measuring device through the short-circuit connecting piece, and the short-circuit connecting piece is connected with the fourth connecting piece or the fifth connecting piece through the short-circuit connecting piece to realize pull-up or pull-down of the IO port.

9. The expansion circuit board of claim 8, further comprising a second mating connector mated with the second connector, wherein the second mating connector is connected to the first connector connected to the measurement device, and the short connector is configured to pull up or pull down the IO port by short-connecting the second connector to the second mating connector.

10. The expansion circuit board according to claim 6 or 7, further comprising a sixth connecting member and a seventh connecting member, wherein the sixth connecting member is connected to the upper eight bits of the first connecting member connected to the measurement device, the seventh connecting member is connected to the lower eight bits of the first connecting member connected to the measurement device, and the shorting connecting member realizes floating input and push-pull output of an IO port by shorting the sixth connecting member and the seventh connecting member.

11. An MCU ATE device comprising a test host, a measurement device, and an expansion board according to any one of claims 1 to 10;