CN108809275B - Signal generating circuit and DC converter - Google Patents
Signal generating circuit and DC converter Download PDFInfo
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- CN108809275B CN108809275B CN201811002928.8A CN201811002928A CN108809275B CN 108809275 B CN108809275 B CN 108809275B CN 201811002928 A CN201811002928 A CN 201811002928A CN 108809275 B CN108809275 B CN 108809275B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
- H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
- H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Dc-Dc Converters (AREA)
Abstract
The embodiment of the invention provides a signal generating circuit and a direct current converter, which comprise a first switch and a second switch, wherein one end of the first switch is connected with a power supply respectively, the other end of the first switch is connected with one end of a third switch, the other end of the second switch is connected with one end of a fourth switch, and the other end of the third switch is connected with the other end of the fourth switch; one end of the first capacitor is connected with the common end of the first switch and the third switch, and the other end of the first capacitor is grounded; one end of the second capacitor is connected with the common end of the second switch and the fourth switch, and the other end of the second capacitor is grounded; the output end of the operational amplifier is connected with the common end of the third switch and the fourth switch, and the output end of the operational amplifier is grounded through a third capacitor; and the level signal generating unit is used for controlling the on-off of the first switch, the second switch, the third switch and the fourth switch. The invention can realize the sawtooth wave with adjustable starting point value, so that the pulse width modulation signal obtained by the pulse width modulation comparator can be suitable for the scene with small duty ratio.
Description
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a signal generating circuit and a dc converter.
Background
In the DC converter of the voltage die control mode, the difference between the feedback voltage and the set target value is amplified by an error amplifier to obtain an analog control signal; the analog control signal and the sawtooth wave pass through a pulse width modulation comparator to obtain a pulse width modulation signal for controlling the on-off of the switching tube.
Currently, the value of the starting point of the sawtooth wave generated by the signal generating circuit is fixed, and is generally zero. And the analog control signal obtained by the error amplifier cannot be reduced to zero again. In this way, the duty cycle of the pwm signal obtained by the pwm comparator through the analog control signal and the sawtooth wave is relatively high, and the pwm signal cannot be adapted to a small duty cycle scene.
Disclosure of Invention
Based on the shortcomings of the prior art, the invention provides a signal generating circuit and a direct current converter to realize generation of sawtooth waves with adjustable initial points.
In order to solve the above problems, the following solutions have been proposed:
the first aspect of the present invention discloses a signal generating circuit, comprising:
one end of the first switch is connected with a first switch and one end of the second switch is connected with one end of a third switch, the other end of the second switch is connected with one end of the fourth switch, and the other end of the third switch is connected with the other end of the fourth switch;
a first capacitor with one end connected to the common end of the first switch and the third switch, and the other end of the first capacitor is grounded;
one end of the second capacitor is connected with the common end of the second switch and the fourth switch, and the other end of the second capacitor is grounded;
the output end of the operational amplifier is connected with the common end of the third switch and the fourth switch, the non-inverting input end of the operational amplifier inputs reference voltage, the inverting input end of the operational amplifier is connected with the output end, and the output end is grounded through a third capacitor;
the level signal generation unit is used for outputting a first level signal and a second level signal which are opposite, and the first level signal is used for controlling the on-off of the second switch and the third switch; the second level signal is used for controlling the on-off of the first switch and the fourth switch.
Preferably, in the above signal generating circuit, the level signal generating unit includes: d flip-flop, wherein:
the data input end of the D trigger is connected with the first output end; the clock input end of the D trigger receives a level signal; the second output end of the D trigger is connected with an NOT gate branch, and the NOT gate branch comprises a first NOT gate and a second NOT gate which are connected in series; and the common end of the first NOT gate and the second NOT gate is used for outputting the first level signal, and the port of the NOT gate branch circuit which is not connected with the D trigger is used for outputting the second level signal.
Preferably, in the signal generating circuit, the second switch and the third switch are controlled to be turned on when the first level signal is at a high level, and the first switch and the fourth switch are controlled to be turned off when the second level signal is at a low level;
and when the first level signal is at a low level, the second switch and the third switch are controlled to be turned on, and when the second level signal is at a high level, the first switch and the fourth switch are controlled to be turned off.
Preferably, in the signal generating circuit, the first switch, the second switch, the third switch and the fourth switch include switching transistors, wherein the first level signal is used for inputting control terminals of the second switch and the third switch, and the second level signal is used for inputting control terminals of the first switch and the fourth switch.
The second aspect of the present invention discloses a dc converter comprising:
the error amplifier, wherein, the reverse input end of the said error amplifier connects the feedback resistance, the same-direction input end receives the standard voltage;
a signal generating circuit as described above; wherein, in the signal generating circuit, the common end of the first switch, the second switch and the power supply is used as the output end of the signal generating circuit;
the positive input end is connected with the output end of the error amplifier, the negative input end is connected with the pulse width modulation comparator of the output end of the signal generating circuit, and the pulse width modulation comparator is used for outputting a pulse width modulation signal to control the on-off of a switching tube in the direct current converter.
Preferably, in the dc converter, the level signal generating unit includes: d flip-flop, wherein:
the data input end of the D trigger is connected with the first output end; the clock input end of the D trigger receives a level signal; the second output end of the D trigger is connected with an NOT gate branch, and the NOT gate branch comprises a first NOT gate and a second NOT gate which are connected in series; and the common end of the first NOT gate and the second NOT gate is used for outputting the first level signal, and the port of the NOT gate branch circuit which is not connected with the D trigger is used for outputting the second level signal.
Preferably, in the dc converter, the second switch and the third switch are controlled to be turned on when the first level signal is at a high level, and the first switch and the fourth switch are controlled to be turned off when the second level signal is at a low level;
and when the first level signal is at a low level, the second switch and the third switch are controlled to be turned on, and when the second level signal is at a high level, the first switch and the fourth switch are controlled to be turned off.
Preferably, in the dc converter, the first switch, the second switch, the third switch and the fourth switch include switching transistors, wherein the first level signal is used for inputting control ends of the second switch and the third switch, and the second level signal is used for inputting control ends of the first switch and the fourth switch.
According to the technical scheme, in the signal generation circuit provided by the invention, the reference voltage is input from the non-inverting input end of the operational amplifier, the inverting input end is connected with the output end, and the output end is grounded through the third capacitor; the operational amplifier is a voltage follower, that is, the voltage at the output end is equal to the voltage at the input end, so that the voltage at the two ends of the third capacitor is always the reference voltage after being clamped by the operational amplifier, and the reference voltage is adjustable. The first level signal and the second level signal are output in the opposite direction, the first level signal controls the on-off of the second switch and the third switch, the second level signal controls the on-off of the first switch and the fourth switch, when the first level signal controls the second switch and the third switch to be conducted, the second level signal controls the first switch and the fourth switch to be turned off, at the moment, one end of the second capacitor is connected to a power supply of the signal generating circuit through the second switch, the other end of the second capacitor is grounded, and the current charges the second capacitor; at the moment, one end of the first capacitor is connected with the third capacitor and the common end of the output end of the operational amplifier through the third switch, the other end of the first capacitor is grounded, and the first capacitor is set to be a reference voltage by the third capacitor; when the first level controls the second switch and the third switch to be turned off, when the second level controls the first switch and the fourth switch to be turned on, one end of the first capacitor is connected with a power supply of the signal generating circuit through the first switch, the other end of the first capacitor is grounded, current charges the first capacitor, and the starting point of voltage at two ends of the first capacitor is reference voltage; at this time, one end of the second capacitor is connected with the third capacitor and the common end of the output end of the operational amplifier through the fourth switch, the other end of the second capacitor is grounded, the second capacitor is set as the reference voltage by the third capacitor, and the process is repeated continuously, so that sawtooth waves with adjustable initial point values can be generated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a circuit diagram of generating a sawtooth wave for a dc converter according to an embodiment of the present invention;
FIG. 2 is a graph showing magnitude relation between an analog control signal and a sawtooth wave according to another embodiment of the present invention;
FIG. 3 is a diagram of a sawtooth signal generating circuit with adjustable starting point values according to an embodiment of the present invention;
FIG. 4 is a diagram showing a relationship among clock signals, first level signals and second level signals according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of a DC converter capable of generating a PWM signal with a small duty cycle according to another embodiment of the present invention;
fig. 6 is a diagram showing magnitude relation between an analog control signal and a sawtooth signal with a starting point being a reference voltage according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the conventional sawtooth wave generating circuit applied to the dc converter, as shown in fig. 1, a positive input terminal of a comparator, an output terminal of a power supply, and an input terminal of a switching tube M1 are connected to each other, and a connection point thereof is used as an output terminal of the sawtooth wave generating circuit.
The starting state of the sawtooth wave generating circuit, the switching tube M1 is disconnected, the current I charges the capacitor C, the voltage of the output end of the sawtooth wave generating circuit rises according to the slope of the I/C, when the voltage rises to Vp, the comparator turns high, after delay, the signal of the control end of the switching tube M1 becomes high, the switching tube M1 is conducted to discharge the charge of the capacitor C, the voltage of the output end of the sawtooth wave generating circuit becomes zero, the comparator turns low, the signal of the control end of the switching tube M1 becomes low, the switching tube M1 is closed, the current I restarts to charge the capacitor C, and the process is repeated continuously to generate a sawtooth wave signal.
The inventors found that: the sawtooth wave generated by the sawtooth wave generating circuit has a starting point voltage value which is generated by charging the capacitor C with a current, and thus the starting point voltage value is fixed to zero.
In the dc converter, the analog control signals obtained by the sawtooth wave and the error amplifier are input to pulse width modulation comparators, respectively. However, the inventors also found that: the output signal Vc of the error amplifier is limited by the common mode output voltage of the error amplifier, and cannot be reduced to zero (Vc is too small to enable the error amplifier to enter the linear region). Therefore, as shown in fig. 2, the magnitude relation between the analog control signal of the error amplifier and the sawtooth wave is that the analog control signal Vc of the error amplifier is larger than the current value of the starting point of the sawtooth wave. Based on this, the duty ratio of the pwm signal obtained by the pwm comparator is relatively large as shown in fig. 2.
In view of the foregoing, an embodiment of the present application proposes a signal generating circuit to implement generating a sawtooth wave with an adjustable starting point value.
Referring to fig. 3, an embodiment of the present invention discloses a signal generating circuit, which includes: one end is respectively connected with a first switch S1 and a second switch S2 of the power supply VDD, the other end of the first switch S1 is connected with one end of a third switch S3, the other end of the second switch S2 is connected with one end of a fourth switch S4, and the other end of the third switch S3 is connected with the other end of the fourth switch S4.
One end of the first capacitor C1 is connected to the common end of the first switch S1 and the third switch S3, and the other end of the first capacitor C1 is grounded.
And one end of the second capacitor C2 is connected to the common end of the second switch S2 and the fourth switch S4, and the other end of the second capacitor C2 is grounded.
An operational amplifier 301 with an output terminal connected to the common terminal of the third switch S3 and the fourth switch S4, and a reference voltage V is input to the non-inverting input terminal of the operational amplifier 301 ref The inverting input end is connected with the output end, and the output end is grounded through a third capacitor C3; the voltage value of the voltage at two ends of the third capacitor is always the reference voltage V after being clamped by the operational amplifier 301 ref 。
A level signal generating unit 302, where the level signal generating unit 302 is configured to output a first level signal Q1 and a second level signal Q2, which are inverted, and the first level signal Q1 is configured to control on/off of the second switch S2 and the third switch S3; the second level signal Q2 is used to control the on-off of the first switch S1 and the fourth switch S4.
In the signal generating circuit provided by the present invention, the reference voltage V is input to the non-inverting input terminal of the operational amplifier 301 ref The inverting input end is connected with the output end, and the output end is grounded through a third capacitor C3; the operational amplifier 301 is a voltage follower, i.e. the voltage at the output end is equal to the voltage at the input end, so that the voltage at the two ends of the third capacitor C3 is always the reference voltage V after being clamped by the operational amplifier 301 ref And this reference voltage V ref Is adjustable.
When the first level signal Q1 controls the second switch S2 and the third switch S3 to be turned on, the second level signal Q2 controls the first switch S1 and the fourth switch S4 to be turned off, at this time, one end of the first capacitor is connected to the third capacitor C3 and the common end of the output end of the operational amplifier 301 through the third switch S3, the other end is grounded, the third capacitor C3 charges the first capacitor C1, and the first capacitor C1 is set as the reference voltage V by the third capacitor C3 ref At this time, one end of the second capacitor C2 is connected to the power supply VDD of the signal generating circuit through the second switch S2, and the other end is grounded, so that the current I charges the second capacitor C2.
When the first level signal Q1 controls the second switch S2 and the third switch S3 to turn off, the second level signal Q2 controls the first switch S1 and the fourth switch S4 to turn on, at this time, one end of the first capacitor C1 is connected to the power supply VDD of the signal generating circuit through the first switch S1, the other end is grounded, the current I charges the first capacitor C1, and the starting point of the voltage at two ends of the first capacitor C1 is the reference voltage V ref The method comprises the steps of carrying out a first treatment on the surface of the At this time, one end of the second capacitor C2 is connected to the third capacitor C3 and the common end of the output end of the operational amplifier 301 through the fourth switch S4, and the other end is grounded, and the second capacitor C2 is set as the reference voltage V by the third capacitor C3 ref The method comprises the steps of carrying out a first treatment on the surface of the The above process is repeated to generate a sawtooth wave Ramp with a starting point as a reference voltage, and the reference voltage V ref Can be set arbitrarily according to the requirements.
Alternatively, in a specific embodiment of the present invention, the level signal generating unit may be a D flip-flop, wherein:
the data input end of the D trigger is connected with the first output end; the clock input end of the D trigger receives the level signal; the second output end of the D trigger is connected with an NOT gate branch, and the NOT gate branch comprises a first NOT gate and a second NOT gate which are connected in series; the common end of the first NOT gate and the second NOT gate is used for outputting a first level signal, and the NOT gate branch is not connected with the port of the D trigger and is used for outputting a second level signal.
It should be noted that, the clock signal CLK is input to the clock input end in the D flip-flop, the signal output by the second output end of the D flip-flop outputs the first level signal Q1 after passing through the first not gate, the first level signal Q1 outputs the second level signal Q2 after passing through the second not gate, the first level signal Q1 and the second level signal Q2 are two opposite signals, the relationship between the clock signal CLK and the first level signal Q1 and the second level signal Q2 is shown in fig. 4, where the first level signal is used for controlling the on-off of the second switch and the third switch, and the second level signal is used for controlling the on-off of the first switch and the fourth switch.
Optionally, in an embodiment of the present invention, when the high level signal controls the switch to be turned on and the low level signal controls the switch to be turned off: when the first level signal is at a high level, the second switch and the third switch are controlled to be turned on, and when the second level signal is at a low level, the first switch and the fourth switch are controlled to be turned off.
When the low-level signal control switch is turned on and the high-level signal control switch is turned off: and when the second level signal is high level, the first switch and the fourth switch are controlled to be turned off.
Optionally, in a specific embodiment of the present invention, the first switch, the second switch, the third switch and the fourth switch may be switching tubes, and it should be noted that a control end of the first switch is connected to the first level signal, an input end of the first switch is connected to a power supply, and an output end of the first switch is connected to a common end of the first capacitor and the third switch; the control end of the second switch is connected with the first level signal, the input end of the second switch is connected with a power supply, and the output end of the second switch is connected with the common end of the second capacitor and the fourth switch; the control end of the third switch is connected with the first level signal, the input end of the third switch is connected with the common end of the first capacitor and the first switch, and the output end of the third switch is connected with the common end of the output end of the operational amplifier and the third point capacitor.
Referring to fig. 5, another embodiment of the present invention discloses a dc converter, which includes: an error amplifier 501, wherein an inverting input terminal of the error amplifier 501 is connected with a feedback resistor R2, and an inverting input terminal receives a feedback voltage V fb Voltage V fed back by feedback resistor fb And a set standard voltage V ref The difference between the two signals is amplified by an error amplifier 501, and the amplified voltage is an analog control signal V C 。
A signal generating circuit 502; the specific implementation process of the signal generating circuit is consistent with the implementation principle and the signal generating circuit shown in fig. 3, and will not be described herein. In the signal generating circuit, a common terminal of the first switch, the second switch and the power supply is used as an output terminal of the signal generating circuit 502.
It should be further noted that the output end of the signal generating circuit outputs a sawtooth signal with an adjustable starting point value.
In the signal generating circuit 502, a reference voltage is input to a non-inverting input end of the operational amplifier, an inverting input end of the operational amplifier is connected with an output end, and the output end is grounded through a third capacitor; the operational amplifier is a voltage follower, that is, the voltage at the output end is equal to the voltage at the input end, so that the voltage at the two ends of the third capacitor is always the reference voltage after being clamped by the operational amplifier, and the reference voltage is adjustable.
When the first level signal controls the second switch and the third switch to be turned on, the second level signal controls the first switch and the fourth switch to be turned off, so that the third capacitor charges the first capacitor, the voltage at two ends of the first capacitor is the reference voltage, and the current charges the second capacitor.
When the first level signal controls the second switch and the third switch to be turned off, the second level signal controls the first switch and the fourth switch to be turned on, so that the current charges the first capacitor, the charging starting point is the reference voltage, the third capacitor charges the second capacitor, and the voltage at two ends of the second capacitor is the reference voltage; the above process is repeated continuously, so that a sawtooth wave with a starting point as a reference voltage can be generated, and the reference voltage can be set arbitrarily according to the requirement.
The positive input end is connected with the output end of the error amplifier 501, the negative input end is connected with the pulse width modulation comparator 503 of the output end of the signal generating circuit, and the pulse width modulation comparator 503 is used for outputting a pulse width modulation signal DRV to control the on-off of the switching tube M in the direct current converter.
It should be noted that the positive input of the pwm comparator 503 is an analog control signal V C The output signal Vc of the error amplifier 501 is limited by the common mode output voltage of the error amplifier (Vc is too small to make the error amplifier enter the linear region), and the Vc signal cannot be reduced to zero. The negative input terminal of the pwm comparator 503 is input with a sawtooth wave whose starting point is the reference voltage generated by the signal generating circuit 502. Since the starting point of the sawtooth wave can be adjusted at will, the analog control signal Vc of the error amplifier 501 may be approximately equal to the starting point voltage of the sawtooth wave, and the magnitude relationship between the analog control signal and the sawtooth wave signal with the starting point being the reference voltage is shown in fig. 6, so that the pwm comparator 503 can obtain the pwm signal with a small duty ratio to adapt to the application situation of the signal with a small duty ratio.
Alternatively, in a specific embodiment of the present invention, the level signal generating unit may be a D flip-flop, wherein: the data input end of the D trigger is connected with the first output end; the clock input end of the D trigger receives the level signal; the second output end of the D trigger is connected with an NOT gate branch, and the NOT gate branch comprises a first NOT gate and a second NOT gate which are connected in series; the common end of the first NOT gate and the second NOT gate is used for outputting a first level signal, and the NOT gate branch is not connected with the port of the D trigger and is used for outputting a second level signal.
It should be noted that, the clock signal CLK is input to the clock input end of the D flip-flop, the signal output from the second output end of the D flip-flop outputs the first level signal Q1 after passing through the first not gate, and outputs the second level signal Q2 after passing through the second not gate, the first level signal Q1 and the second level signal Q2 are two opposite signals, the relationship between the clock signal CLK and the first level signal Q1 and the relationship between the clock signal CLK and the second level signal Q2 are shown in fig. 4, and fig. 4 is a graph of the relationship among the clock signal, the first level signal and the second level signal; the first level signal Q1 output by the first NOT gate and the second level signal Q2 output by the second NOT gate are two signals in opposite directions, wherein the first level signal is used for controlling the on-off of the second switch and the third switch, and the second level signal is used for controlling the on-off of the first switch and the fourth switch.
Optionally, in an embodiment of the present invention, when the high level signal controls the switch to be turned on and the low level signal controls the switch to be turned off: when the first level signal is at a high level, the second switch and the third switch are controlled to be turned on, and when the second level signal is at a low level, the first switch and the fourth switch are controlled to be turned off.
When the low-level signal control switch is turned on and the high-level signal control switch is turned off: and when the second level signal is high level, the first switch and the fourth switch are controlled to be turned off.
Optionally, in a specific embodiment of the present invention, the first switch, the second switch, the third switch and the fourth switch may be switching tubes, and it should be noted that a control end of the first switch is connected to the first level signal, an input end of the first switch is connected to a power supply of the signal generating circuit, and an output end of the first switch is connected to a common end of the first capacitor and the third switch; the control end of the second switch is connected with the first level signal, the input end of the second switch is connected with a power supply of the signal generating circuit, and the output end of the second switch is connected with the common end of the second capacitor and the fourth switch; the control end of the third switch is connected with the first level signal, the input end of the third switch is connected with the common end of the first capacitor and the first switch, and the output end of the third switch is connected with the common end of the output end of the operational amplifier and the third point capacitor.
Those skilled in the art will be able to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A signal generating circuit, comprising:
one end of the first switch is connected with a first switch and one end of the second switch is connected with one end of a third switch, the other end of the second switch is connected with one end of a fourth switch, and the other end of the third switch is connected with the other end of the fourth switch;
a first capacitor with one end connected to the common end of the first switch and the third switch, and the other end of the first capacitor is grounded;
one end of the second capacitor is connected with the common end of the second switch and the fourth switch, and the other end of the second capacitor is grounded;
the output end of the operational amplifier is connected with the common end of the third switch and the fourth switch, the non-inverting input end of the operational amplifier inputs reference voltage, the inverting input end of the operational amplifier is connected with the output end, and the output end is grounded through a third capacitor;
the level signal generation unit is used for outputting a first level signal and a second level signal which are opposite, and the first level signal is used for controlling the on-off of the second switch and the third switch; the second level signal is used for controlling the on-off of the first switch and the fourth switch.
2. The signal generating circuit according to claim 1, wherein the level signal generating unit includes: d flip-flop, wherein:
the data input end of the D trigger is connected with the first output end; the clock input end of the D trigger receives a level signal; the second output end of the D trigger is connected with an NOT gate branch, and the NOT gate branch comprises a first NOT gate and a second NOT gate which are connected in series; and the common end of the first NOT gate and the second NOT gate is used for outputting the first level signal, and the port of the NOT gate branch circuit which is not connected with the D trigger is used for outputting the second level signal.
3. The signal generating circuit according to claim 1, wherein the second switch and the third switch are controlled to be turned on in a case where the first level signal is high level, and the first switch and the fourth switch are controlled to be turned off in a case where the second level signal is low level;
and when the first level signal is at a low level, the second switch and the third switch are controlled to be turned on, and when the second level signal is at a high level, the first switch and the fourth switch are controlled to be turned off.
4. The signal generating circuit of claim 1, wherein the first switch, the second switch, the third switch, and the fourth switch comprise switching transistors, wherein the first level signal is used to input control terminals of the second switch and the third switch, and wherein the second level signal is used to input control terminals of the first switch and the fourth switch.
5. A dc converter, comprising:
the error amplifier, wherein, the reverse input end of the said error amplifier connects the feedback resistance, the same-direction input end receives the standard voltage;
the signal generating circuit of claim 1; wherein, in the signal generating circuit, the common end of the first switch, the second switch and the power supply is used as the output end of the signal generating circuit;
the positive input end is connected with the output end of the error amplifier, the negative input end is connected with the pulse width modulation comparator of the output end of the signal generating circuit, and the pulse width modulation comparator is used for outputting a pulse width modulation signal to control the on-off of a switching tube in the direct current converter.
6. The dc converter according to claim 5, wherein the level signal generating unit includes: d flip-flop, wherein:
the data input end of the D trigger is connected with the first output end; the clock input end of the D trigger receives a level signal; the second output end of the D trigger is connected with an NOT gate branch, and the NOT gate branch comprises a first NOT gate and a second NOT gate which are connected in series; and the common end of the first NOT gate and the second NOT gate is used for outputting the first level signal, and the port of the NOT gate branch circuit which is not connected with the D trigger is used for outputting the second level signal.
7. The dc converter of claim 5, wherein the second switch and the third switch are controlled to be turned on when the first level signal is at a high level, and the first switch and the fourth switch are controlled to be turned off when the second level signal is at a low level;
and when the first level signal is at a low level, the second switch and the third switch are controlled to be turned on, and when the second level signal is at a high level, the first switch and the fourth switch are controlled to be turned off.
8. The dc converter of claim 5, wherein the first switch, the second switch, the third switch, and the fourth switch comprise switching transistors, wherein the first level signal is used to input control terminals of the second switch and the third switch, and wherein the second level signal is used to input control terminals of the first switch and the fourth switch.
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