CN108807272A - 用于n型掩埋层集成的穿过屏蔽层的高剂量锑注入 - Google Patents

用于n型掩埋层集成的穿过屏蔽层的高剂量锑注入 Download PDF

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CN108807272A
CN108807272A CN201810382043.9A CN201810382043A CN108807272A CN 108807272 A CN108807272 A CN 108807272A CN 201810382043 A CN201810382043 A CN 201810382043A CN 108807272 A CN108807272 A CN 108807272A
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layer
top surface
substrate
semi
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CN108807272B (zh
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B·胡
A·H·卡哈兹-斯耶德
S·阿尔莎德
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Texas Instruments Inc
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Texas Instruments Inc
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  • Element Separation (AREA)

Abstract

本申请公开了用于N型掩埋层集成的穿过屏蔽层的高剂量锑注入。通过在衬底(104)的顶表面(106)上形成薄屏蔽层(108)来形成具有n型掩埋层(NBL)的微电子器件(100)。锑(114)穿过由注入掩模(110)暴露的屏蔽层(108)被注入到衬底(104)中；注入掩模(110)阻挡锑(114)到NBL区域(112)外侧的衬底(104)。注入掩模(110)被移除，留下屏蔽层(108)在表面(106)上，该屏蔽层在NBL区域(112)上方以及在NBL外侧的区域上方具有相同的厚度。在退火/驱动工艺期间，在NBL区域(112)中以及在NBL区域外侧都形成二氧化硅。在NBL区域(112)中形成稍微多一些的二氧化硅，在该区域中消耗更多的硅并因此形成浅的硅凹槽。在衬底(104)的顶表面(106)上生长外延层。还公开了微电子器件(100)的结构。

Description

用于N型掩埋层集成的穿过屏蔽层的高剂量锑注入
技术领域
本公开涉及微电子器件领域。特别地，本公开涉及微电子器件中的掩埋层。
背景技术
具有模拟部件的微电子器件可以具有掺杂有锑(Sb)的n型掩埋层(NBL)。由于锑的低扩散系数，其通常是用于NBL的优选掺杂剂；用锑掺杂实现高掺杂剂密度(并且因此实现用于NBL的低薄层电阻)而不会扩散到其它部件中。通常由开始于p型硅衬底并且在该衬底的顶表面上生长几百纳米厚的厚热氧化层形成NBL。将厚氧化物上方的光致抗蚀剂掩模图案化，暴露出NBL的区域。在NBL的区域中蚀刻掉厚氧化物，暴露出硅，之后移除光致抗蚀剂掩模。以高剂量(例如超过1×1015cm-2)将锑注入到硅中以提供期望的低薄层电阻。厚的热氧化物阻挡锑进入NBL区域外侧的衬底。需要厚氧化物来阻挡锑，因为光致抗蚀剂会在以这种高剂量注入期间硬化，使得其在不损坏NBL区域中的暴露的硅表面的情况下难以移除。通常在退火/驱动步骤之前的温度斜坡期间，厚氧化物保留在原处，同时在衬底上生长附加热氧化物(通常几百埃)。需要附加热氧化物来减少在退火/驱动期间的锑逸出。锑逸出可能不合期望地降低NBL中的掺杂物密度并且可能不合期望地掺杂NBL外侧的区域。在厚氧化物处于原地的情况下生长附加热氧化物导致在衬底的顶表面中的凹槽(通常大于10纳米深)，因为注入区域中的硅被氧化生长消耗，而厚氧化物下方的硅以低得多的速度消耗。退火/驱动步骤使衬底退火并且使锑激活且更深地扩散到衬底中，以形成NBL的一部分。随后从衬底的顶表面移除氧化物，在NBL区域的上方留下硅凹槽。在衬底上生长p型硅外延层(通常3微米到10微米厚)。锑在外延层生长时向上扩散到外延层，但是不延伸到外延层的顶表面。衬底中和外延层中的锑提供NBL。硅凹槽被复制到外延层的顶表面中。在随后在外延层中或在外延层上方形成部件期间，硅凹槽可能降低工艺宽容度(latitude)。在某些情况下，由于存在硅凹槽，制造某些部件可能是不切实际或成本过高的。
发明内容
本公开介绍了一种在微电子器件中形成n型掩埋层(NBL)的方法。在一种实施方式中，所公开的方法在锑注入和随后的退火/驱动操作中使用均匀的薄屏蔽层。使用均匀的薄屏蔽层有利地产生浅硅凹槽，其可以兼容随后的微电子器件中的部件的形成。
具有NBL的微电子器件通过提供衬底而形成，该衬底包括在顶表面处的半导体材料。在衬底的顶表面上形成薄屏蔽层。在屏蔽层上形成注入掩模，暴露出在NBL区域中的屏蔽层。将锑通过屏蔽层注入到衬底中；注入掩模阻挡锑进入NBL区域外侧的衬底。在注入锑后，移除注入掩模。屏蔽层被留在表面上。在退火/驱动工艺中加热衬底，这使衬底中的注入损伤退火并扩散注入的锑。在NBL区域中以及在NBL区域外侧由环境中的氧气在退火/驱动工艺期间形成二氧化硅。在NBL区域中形成稍微多一些的二氧化硅，在该区域中消耗更多的硅并且因此形成浅硅凹槽。额外的二氧化硅以及屏蔽层被从衬底的顶表面移除，并且外延层在衬底的顶表面上生长。还公开了微电子器件的结构。
附图说明
图1A至图1M是以示例形成方法的阶段描绘的微电子器件的横截面图。
具体实施方式
参考附图描述本公开。附图并未按照比例绘制，并且它们仅供图示说明本公开。参考图示的示例应用描述本公开的几个方面。应该理解，阐述了许多具体细节、关系以及方法以提供对本公开的理解。本公开不受所示出的动作或事件的顺序限制，因为一些动作可以以不同顺序发生和/或与其它动作或事件同时发生。此外，并非所有示出的动作或事件均是实现根据本公开的方法所必需的。
为了本公开的目的，术语“横向”应理解为指的是平行于微电子器件或衬底的即时顶表面的平面的方向。类似地，术语“竖直”应理解为指的是垂直于微电子器件或衬底的即时顶表面的平面的方向。
应注意的是本公开可能使用诸如顶部、底部、前方、后方、上方、以上、下方和以下等术语。这些术语不应被解释为限制结构或元件的位置或取向，而应该用于提供结构或元件之间的空间关系。
图1A至图1M是以示例形成方法的阶段描绘的微电子器件的横截面图。参考图1A，微电子器件100包括具有半导体材料104的衬底102，该半导体材料104具有顶表面106。微电子器件100可以是例如集成电路或分立部件。衬底102可以包括例如体硅晶圆、绝缘体上硅(SOI)晶圆、具有外延层的硅晶圆或适于形成微电子器件100的其它衬底。半导体材料104可以包括(例如由硼)p型掺杂的硅。半导体材料104可以包括体硅晶圆的硅，可以包括外延层的硅或者可以包括转移层的硅。
屏蔽层108被形成在半导体材料104的顶表面106上方。屏蔽层108包括二氧化硅。屏蔽层108可以在形成后具有例如6.5纳米至30纳米的厚度范围。测试已经表明小于6.5纳米厚的屏蔽层108可能不能在随后的工艺步骤期间充分保护在顶表面106处的半导体材料104。进一步的测试已经表明大于30纳米厚的屏蔽层108可能导致：在随后形成的n型掩埋层(NBL)中的不期望的薄层电阻的变化、(例如通过用于注入锑以形成NBL的离子注入机实现的)低生产能力或者用于形成注入掩模的光致抗蚀剂的硬化。可以通过顶表面106附近的半导体材料104中的硅的热氧化来形成屏蔽层108的至少一部分。应该认识到，通过热氧化工艺形成屏蔽层108会消耗顶表面106处的硅。为了本公开的目的，顶表面106将被理解为指的是在所讨论的步骤期间存在的半导体材料104的即时顶表面106。在形成微电子器件100期间，即时顶表面106可以逐步改变。
在屏蔽层108上方形成注入掩模110。注入掩模110暴露出NBL区域112中的屏蔽层108并且覆盖NBL区域112外侧的屏蔽层108。注入掩模110可以包括由光刻操作形成的光致抗蚀剂。注入掩模110可以进一步包括诸如底部抗反射涂层(BARC)的抗反射材料。注入掩模110足够厚以在随后的锑注入工艺期间吸收影响注入掩模110的锑原子，从而防止微电子器件100的性能参数退化。注入掩模110也足够厚以维持与氧化元件的反应性，从而在不损坏屏蔽层108的情况下移除注入掩模110。例如，注入掩模110可以不含无机材料，因为无机材料可能降低与氧化元件的反应性。在一个实施方式中，注入掩模110可以是至少500纳米厚以提供这些功能。尽管存在前述的厚度范围，但光致抗蚀剂规划和光刻工艺的未来发展以及光刻抗蚀剂移除工艺的未来发展可以支持较低的厚度范围。
参考图1B，将锑原子114注入到微电子器件100中。当开始注入锑原子时，NBL区域112中的屏蔽层108的厚度等于与NBL区域112相邻的屏蔽层108的厚度。大多数锑原子114穿过屏蔽层108以在屏蔽层108下方的半导体材料104中的NBL区域112中形成注入区域116。少数锑原子114被屏蔽层108吸收。期望获得随后形成的NBL的低薄层电阻(例如小于30Ω/□)以获得电路性能目标，可以由半导体材料104中的大约1×1015cm-2或更大剂量的锑原子114形成注入区域116来实现该目标。通过增加锑原子114的注入能量增加形成注入区域116的锑原子114的分数(fraction)有利地提高随后形成的NBL的薄层电阻的一致性和再现性。注入能量还可以是在注入锑原子114之后移除注入掩模110的考虑因素以及注入装备的生产能力的考虑因素的函数。许多高电流注入机受限于最大可用电子束功率，该电子束功率被理解为注入能量(以伏特表示)与电子束电流的乘积，从而增加注入能量必然降低电子束电流并且因此降低生产能力。可以用足够的能量注入锑原子114，以使得60％至85％的锑原子114穿过屏蔽层108并且进入半导体材料104中，这有利地为随后形成的NBL提供一致的薄层电阻。可以通过考虑关于在注入锑原子114之后移除注入掩模110的工艺能力来确定注入能量。例如，在其中屏蔽层108是15纳米至25纳米厚的本实例的版本中，可以以2×1015cm-2的剂量以及25千电子伏(keV)至50keV的注入能量注入锑原子114。
参考图1C，可以可选地通过使用氧自由基118的干法工艺移除注入掩模110的至少一部分。可以例如通过灰化工艺、下游灰化工艺、臭氧工艺来提供氧自由基118。选择干法工艺的参数(例如氧自由基118的动能)以避免屏蔽层108(尤其是在NBL区域112中)的不可接受的退化。
参考图1D，可以可选地通过湿法工艺120移除至少一部分注入掩模110。在一个示例中，湿法工艺120可以包括过氧化氢和硫酸的含水混合物，接着是过氧化氢和氢氧化铵的含水混合物。在另一个示例中，湿法工艺120可以包括诸如磺酸和苯酚的有机试剂。由图1C的干法工艺或者由湿法工艺120或两者的组合完全移除注入掩模110。在完全移除注入掩模110之后，NBL区域112中的屏蔽层108的厚度基本上等于与NBL区域112相邻的屏蔽层108的厚度，即在例如使用椭圆偏光法、扫描电子显微镜(SEM)横截面、透射电子显微镜(TEM)横截面等测量氧化层厚度时遇到的测量公差内，NBL区域112中的屏蔽层108的厚度等于与NBL区域112相邻的屏蔽层108的厚度。
参考图1E，通过斜坡热氧化工艺在半导体材料104的顶表面106上方形成额外的二氧化硅以形成扩散覆盖层122，该扩散覆盖层包括图1D的屏蔽层108和额外的二氧化硅。扩散覆盖层122可以在与注入区域116横向相邻的半导体材料104上方具有例如50纳米至65纳米厚的厚度范围。斜坡热氧化工艺是退火/扩散工艺的一部分，该工艺在注入区域116中使半导体材料104退火并且使注入的锑更深地扩散到衬底102中。在斜坡热氧化工艺期间，衬底102的温度从500℃以下增加到1000℃以上。扩散覆盖层122减少穿过半导体材料104的顶表面106的注入的锑的损失。由于锑注入，图1D的注入区域116中的硅可以是部分非晶态。部分非晶硅以比单晶硅更高的速率氧化。因此可以在注入区域116中比在与注入区域116相邻的半导体材料104中以更高的速率形成额外的二氧化硅，从而导致与NBL区域112的横向边界交叠的小的硅凹槽台阶124。执行热氧化工艺使得硅凹槽台阶124小于5纳米。这可以例如通过具有主要为惰性气体(在图1E中标记为“惰性气体”，例如氮气(N2)，具有2％至10％干氧气(O2)(在图1E中标记为“O2”))的氧化环境来完成。该氧化环境有利地基本上不含水蒸气(H2O)，即水蒸气的浓度小于干氧气的浓度的1％并且可以基本上为零。氧化环境中的水蒸气倾向于突出(accentuate)硅凹槽台阶124，因为水蒸气以比干氧以更快的速率形成二氧化硅(尤其是在900℃以下的温度下且注入区域116中的硅仍然是部分非晶态时)。执行斜坡热氧化工艺使得衬底102的温度在小于45分钟内从低于约800℃转变到高于约1000℃，从而在注入区域116中的半导体材料104仍然是非晶态时减少额外的热氧化物的形成。在1000℃以上的温度下，来自注入的锑的半导体材料104中的晶格损伤被修复，使得额外的二氧化硅在注入区域116中的形成以及在与注入区域116横向相邻的半导体材料104的区域中的形成以更相等的速率进行。因此，与在约800℃与约1000℃之间的温度下具有更长时间的斜坡热氧化工艺相比，在小于45分钟内从约800℃转变到高于约1000℃有利地减少在该温度范围内额外的二氧化硅的形成，在该温度范围内额外的二氧化硅在注入区域116中以更高的速率形成。可以通过考虑对衬底102的热应力损伤来确定从约800℃到约1000℃的转变时间。该转变时间的示例(小于45分钟)适用于300毫米直径的硅晶圆的衬底。较小直径的硅晶圆(例如200毫米直径的晶圆)的衬底可以有利地使用较短的转变时间。较大直径的硅晶圆(例如预期的500毫米直径的晶圆)可以使用较长的转变时间以避免热应力损伤。
参考图1F，在1000℃以上对衬底102继续进行退火/扩散工艺。在图1E的注入区域116中的注入的锑更深地扩散到半导体材料104中，以形成n型扩散层126。诸如氮气的惰性气体(在图1F中标记为“惰性气体”)在即时步骤期间流入到环境中。干氧气(在图1F中标记为“O2”)也可以流入到环境中，并且可以在退火/扩散工艺中半途中断。在退火/扩散工艺期间硅凹槽台阶124维持小于5纳米。退火/扩散工艺的示例热曲线图可以包括在1000℃以上持续400分钟到500分钟的时间(其中250分钟到350分钟是在1100℃以上，并且20分钟到50分钟是处于约1200℃)。
参考图1G，以维持硅凹槽台阶122小于5纳米的方式移除图1F的扩散覆盖层122。可以例如通过包括稀缓冲氢氟酸的水溶液的湿法蚀刻工艺128移除扩散覆盖层122。移除扩散覆盖层122的其它方法在本实例的范围内。
可以在此时形成其它结构的额外注入区域(例如p型掩埋层)。这种结构可能需要半导体材料104的顶表面106上方的一个或多个额外的二氧化硅层。也可以以维持硅凹槽台阶124小于5纳米的方式移除这些额外的二氧化硅层。可以以与当前步骤的扩散覆盖层122类似的方式移除额外的二氧化硅层。
参考图1H，在衬底102的半导体材料104的顶表面106上形成p型半导体材料的外延层130。外延层130可以具有与在顶表面106处的半导体材料104类似的半导体材料成分。例如，在顶表面106处的外延层130和半导体材料104都具有含有硼掺杂物的晶体硅。外延层130可以具有与顶表面106处的半导体材料104类似的掺杂物密度。可以例如通过加热衬底102到1000℃至1200℃的温度、移除顶表面106处的100纳米至200纳米的半导体材料104并且随后流动在图1H中标记为“硅源”的硅源(例如甲硅烷(SiH4)或乙硅烷(Si2H6))来在衬底102上方形成外延层130。形成外延层130的其它方法(例如分子束外延)在本实例的范围内。
在外延层130的形成期间，图1G的n型扩散层126中的锑更深地扩散到衬底102的半导体材料104中，并且还向上扩散到外延层130中以形成NBL 132。NBL 132不延伸到外延层130的顶表面134。外延层130可以具有例如3微米至10微米的厚度范围。如果外延层130小于3微米厚，则NBL 132可能延伸得非常接近顶表面134而不允许随后形成组件(例如NBL 132上方的MOS晶体管)。如果外延层130大于10微米厚，则例如由重掺杂区域(已知为汇流端(sinker))实现与NBL 132的电连接将不合期望地影响微电子器件100的制造成本和复杂性。如参考图1B所公开的，NBL 132有利地具有由于注入的锑的剂量所产生的小于30Ω/□的薄层电阻。
在衬底102的半导体材料104的顶表面106中的硅凹槽台阶124可以像外延层130的顶表面134中的表面凹槽台阶136一样被复制。表面凹槽台阶136有利地小于5纳米。表面凹槽台阶136位于NBL 132的横向周长之上。
参考图1I，浅沟槽隔离(STI)结构138被形成在外延层130中并延伸到顶表面134。图1I描绘了部分完成的STI结构138。通过在外延层130的顶表面134上方形成化学机械抛光(CMP)停止层140来形成STI结构138，其中CMP停止层140中的开口用于STI结构138。CMP停止层140中的第一开口位于表面凹槽台阶136内侧的NBL 132上方，并且CMP停止层140中的第二开口位于NBL 132外侧。例如，CMP停止层140可以包括氮化硅等，并且可以是100纳米至200纳米厚。CMP停止层140在NBL 132正上方的外延层130上方以及在与NBL 132横向相邻的外延层130上方具有均匀的厚度。沟槽142形成在CMP停止层140中的开口中的外延层130中，所述沟槽包括位于表面凹槽台阶136内侧的NBL 132上方的第一沟槽142a，以及位于NBL132外侧的第二沟槽142b。隔离填充材料层144被形成在CMP停止层140上方以及沟槽142中。隔离填充材料层144包括介电材料(例如二氧化硅或基于二氧化硅的材料)，并且可以例如通过使用原硅酸四乙酯(TEOS)的等离子体增强化学气相沉积(PECVD)工艺、高密度等离子体(HDP)工艺、使用TEOS和臭氧的高纵横比工艺(HARP)、使用甲硅烷的大气压化学气相沉积(APCVD)工艺或使用二氯硅烷的次大气压化学气相沉积(SACVD)工艺来形成。
参考图1J，如在图1J中由CMP垫146示意性示出的，通过CMP工艺从CMP停止层140上方移除隔离填充材料144。CMP工艺移除CMP停止层140的顶部部分，并且将CMP停止层140的底部部分留在外延层130的顶表面134上方。CMP工艺将CMP停止层140得到的顶表面留下来平坦地横跨表面凹槽台阶136，使得CMP停止层140在表面凹槽台阶136的一侧上比在表面凹槽台阶136的相反侧上更厚。形成NBL 132使得表面凹槽台阶136小于5纳米可以有利地为CMP工艺提供期望的工艺宽容度。已经证明了大于5纳米的表面凹槽台阶降低了CMP工艺的工艺产量。在CMP工艺完成之后，移除CMP停止层140，将隔离填充材料144留在沟槽142中以形成STI结构138。
参考图1K，在外延层130的顶表面134上方和STI结构138上方形成栅极材料层148。栅极材料层148可以包括例如通过甲硅烷的热分解形成的多晶硅。栅极材料层148复制表面凹槽台阶136，使得NBL 132上方的栅极材料层148的顶表面比NBL 132外侧的栅极材料层148的顶表面低大约表面凹槽台阶136的高度(即小于5纳米)。
在栅极材料层148上方形成栅极蚀刻掩模150。栅极蚀刻掩模150限定用于随后形成的MOS晶体管栅极的区域。栅极蚀刻掩模150的第一栅极掩模元件150a位于表面凹槽台阶136内侧的NBL 132上方，并且栅极蚀刻掩模150的第二栅极掩模元件150b位于NBL 132的外侧。栅极蚀刻掩模150的线宽受到用于曝光光致抗蚀剂以形成栅极蚀刻掩模150的光刻系统的聚焦的影响。维持表面凹槽台阶136小于5纳米有利地提供了栅极材料层148的顶表面的充足平坦性，使得NBL 132上方的光致抗蚀剂和NBL 132外侧的光致抗蚀剂可以在暴露光致抗蚀剂的光刻操作期间同时聚焦，从而在NBL 132上方和NBL 132外侧提供期望的线宽均匀性。该优点对于制造具有低于250纳米的栅极长度的MOS晶体管是重要的，并且对于制造具有更短栅极长度的MOS晶体管更为重要。
参考图1L，在由栅极蚀刻掩模150暴露的区域中通过栅极蚀刻工艺152移除图1K的栅极材料层148的栅极材料，以在外延层130的顶表面134上方形成栅极结构154。栅极蚀刻工艺152可以包括使用卤素自由基(例如氟自由基或溴自由基)的反应离子蚀刻(RIE)工艺。由栅极蚀刻工艺152产生的栅极结构154的线宽的均匀性对栅极材料层148的局部厚度变化敏感。局部厚度变化受到栅极结构154下方的外延层130的顶表面134与紧邻(immediatelyadjacent)相应的栅极结构154的STI结构138中的隔离填充材料144的顶部之间的局部高度差的影响。其中紧邻STI结构138的栅极结构154的实例具有较大高度差，其倾向于具有较厚的栅极材料并且从而产生更宽的栅极。维持表面凹槽台阶136小于5纳米可以有利地提供栅极结构154的可接受的线宽均匀性(也被称为栅极长度均匀性或栅极临界尺寸(CD)均匀性)。这一优点对于制造具有低于250纳米的栅极长度的MOS晶体管也很重要，并且对于制造具有更短栅极长度的MOS晶体管更为重要。
参考图1M，MOS晶体管156被形成在合并有栅极结构154的微电子器件100中，所述MOS晶体管包括第一MOS晶体管156a和第二MOS晶体管156b，该第一MOS晶体管位于NBL 132上方并且位于表面凹槽台阶136内侧，该第二MOS晶体管位于NBL 132的外侧。MOS晶体管156包括侧壁间隔件158以及源极/漏极区域160，这些侧壁间隔件形成在栅极结构154的横向表面上，这些源极/漏极区域160形成在与栅极结构154相邻的外延层130中。维持表面凹槽台阶136小于5纳米可以通过提供栅极结构154的均匀栅极长度来有利地提供MOS晶体管156的性能参数(例如驱动电流)的期望的均匀性。
虽然已经在上面描述了本公开的各种实施例，但应该理解已经仅通过示例而非限制地呈现各种实施例。在不背离本公开的精神或范围的情况下，可以根据本文公开内容对所公开的实施例进行各种变化。因此，本发明的广度和范围不应限于任何上面描述的实施例。相反，应当根据随附的权利要求书及其等同物来限定本公开的范围。

Claims (20)

1.一种方法，其包括：
提供包括半导体材料的衬底，所述半导体材料具有顶表面，所述半导体材料是p型的并且包括硅；
在所述半导体材料的所述顶表面上方形成包括二氧化硅的屏蔽层；
在所述屏蔽层上方形成注入掩模，所述注入掩模在所述屏蔽层的一个区域中暴露所述屏蔽层；
将锑注入到所述区域下方的所述半导体材料中的注入区域中；
移除所述注入掩模，其中在移除所述注入掩模之后，用于所述NBL的区域中的所述屏蔽层的厚度基本等于与所述NBL相邻的所述屏蔽层的厚度；
在所述衬底的所述顶表面上方形成额外的二氧化硅；
使所述注入区域中的锑扩散到所述半导体材料中，以形成n型掩埋层即NBL；
从所述衬底的所述顶表面移除所述额外的二氧化硅与所述屏蔽层；以及
在所述衬底的所述顶表面上形成包括硅的外延层。
2.根据权利要求1所述的方法，其中所述屏蔽层中的所述二氧化硅具有6.5纳米至30纳米的厚度范围。
3.根据权利要求1所述的方法，其中形成所述屏蔽层包括热氧化工艺。
4.根据权利要求1所述的方法，其中所述注入掩模包括光致抗蚀剂。
5.根据权利要求1所述的方法，其中所述注入掩模不含无机材料。
6.根据权利要求1所述的方法，其中用足够的能量注入锑以使60％至85％的锑原子穿过所述屏蔽层并进入所述半导体材料中。
7.根据权利要求1所述的方法，其中用足以将至少1×1015cm-2置于所述半导体材料中的剂量注入锑。
8.根据权利要求1所述的方法，其中移除所述注入掩模包括利用氧自由基的干法工艺。
9.根据权利要求1所述的方法，其中移除所述注入掩模包括湿法蚀刻工艺。
10.根据权利要求1所述的方法，其中所述额外的二氧化硅通过热氧化工艺来形成。
11.根据权利要求10所述的方法，其中所述热氧化工艺的环境包括2％至10％的干氧气。
12.根据权利要求11所述的方法，其中在所述热氧化工艺的所述环境中的任何水蒸汽具有小于所述干氧气的浓度的1％的浓度。
13.根据权利要求1所述的方法，其中所述额外的二氧化硅的至少一部分是在热斜坡工艺期间形成的。
14.根据权利要求13所述的方法，其中所述热斜坡工艺包括在小于45分钟内将所述衬底从低于约800℃加热到高于约1000℃。
15.根据权利要求1所述的方法，其进一步包括形成浅沟槽隔离结构即STI结构，所述方法包括：
在所述外延层的所述顶表面上方形成化学机械抛光停止层即CMP停止层，所述CMP停止层具有位于所述NBL上方的第一开口以及位于所述NBL外侧的第二开口；
在所述第一开口中的所述外延层中形成第一沟槽并且在所述第二开口中的所述外延层中形成第二沟槽；
在所述CMP停止层上方并且在所述第一沟槽中和所述第二沟槽中形成隔离填充材料；
通过CMP工艺从所述CMP停止层上方移除所述隔离填充材料，其中所述CMP工艺移除所述CMP停止层的顶部部分并且留下所述CMP停止层的底部部分；以及
随后移除所述CMP停止层。
16.根据权利要求1所述的方法，其进一步包括形成金属氧化物半导体晶体管即MOS晶体管，所述方法包括：
在所述外延层的所述顶表面上方形成栅极材料层；
通过光刻工艺在所述栅极材料层上方形成栅极蚀刻掩模，其中所述栅极蚀刻掩模包括位于所述NBL上方的第一栅极掩模元件和位于所述NBL外侧的第二栅极掩模元件；以及
从由所述栅极蚀刻掩模暴露出的所述栅极材料层移除栅极材料。
17.一种微电子器件，其包括：
包括半导体材料的衬底，所述半导体材料具有顶表面，所述半导体材料是p型的并且包括硅；
位于所述衬底的所述顶表面上的外延层，所述外延层包括p型半导体材料，所述p型半导体材料包含硅；以及
位于所述衬底与所述外延层之间的边界附近的NBL，所述NBL延伸到所述衬底中并且延伸到所述外延层中，其中所述外延层具有在所述NBL上方的表面凹槽台阶，并且所述表面凹槽台阶在1纳米到5纳米的范围内。
18.根据权利要求17所述的微电子器件，其中所述外延层具有3微米至10微米的厚度范围。
19.根据权利要求17所述的微电子器件，其进一步包括第一STI结构和第二STI结构，所述第一STI结构位于所述NBL上方的所述外延层中，所述第二STI结构位于所述NBL外侧的所述外延层中。
20.根据权利要求17所述的微电子器件，其进一步包括第一MOS晶体管和第二MOS晶体管，所述第一MOS晶体管位于所述NBL上方的所述外延层中，所述第二MOS晶体管位于所述NBL外侧的所述外延层中。
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