CN108807192A - 一种ic封装工艺 - Google Patents
一种ic封装工艺 Download PDFInfo
- Publication number
- CN108807192A CN108807192A CN201711361080.3A CN201711361080A CN108807192A CN 108807192 A CN108807192 A CN 108807192A CN 201711361080 A CN201711361080 A CN 201711361080A CN 108807192 A CN108807192 A CN 108807192A
- Authority
- CN
- China
- Prior art keywords
- package
- electrode
- light
- technique according
- glue
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 claims abstract description 21
- 239000003292 glue Substances 0.000 claims abstract description 16
- 238000005538 encapsulation Methods 0.000 claims abstract description 14
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 238000005259 measurement Methods 0.000 claims abstract description 4
- 238000012545 processing Methods 0.000 claims abstract description 4
- 230000011218 segmentation Effects 0.000 claims abstract description 4
- 239000000839 emulsion Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 239000011889 copper foil Substances 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- 239000002390 adhesive tape Substances 0.000 claims description 6
- 238000013461 design Methods 0.000 claims description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- 230000003628 erosive effect Effects 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 230000005693 optoelectronics Effects 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000005286 illumination Methods 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 238000012546 transfer Methods 0.000 claims description 2
- 238000004020 luminiscence type Methods 0.000 claims 1
- 239000011135 tin Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000012536 packaging technology Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 11
- 239000003153 chemical reaction reagent Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000010970 precious metal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
本公开揭示了一种IC封装工艺，包括：S1、利用胶将电极粘附在透光基片以构成IC封装载板；S2、对所述IC封装载板进行IC封装形成封装体；S3、降低所述胶的粘性，以使得所述透光基片与所述封装体分离；S4、对封装体进行表面处理、电测、分割或包装，完成IC封装制程。本公开优化了封装工艺，产品封装后,透光基片与封装后的集成电路易于剥离，有利于节约成本和绿色生产。
Description
技术领域
本公开属于电子技术领域，特别涉及一种IC封装工艺。
背景技术
方形扁平无引脚封装（Quad Flat No-lead Package，QFN）技术是一种重要的集成电路封装工艺，具有表面贴装式封装，焊盘尺寸小、体积小、占有PCB区域小、元件厚度薄、非常低的阻抗、自感，可满足高速或者微波的应用等优点。由于底部中央的大面积裸露焊盘被焊接到PCB的散热焊盘上，使得QFN具有极佳的电和热性能。但缺点在于QFN中部向四周连续布线，线宽受限于铜厚、且难以设计孤岛电极，增加I/0数会带来的生产成本和可靠性问题，限制了芯片和PCB板的设计自由度。相比较而言球栅阵列芯片封装技术（Ball Grid Array.BGA）可增加I/O数和间距，在设计上较QFN更为灵活，但工艺检修困难，对PCB板工艺要求更高，不适用于可靠性要求高的器件的封装及产业效率的提高。
受蚀刻能力的限制， LED EMC支架与倒装基板的生产精度和密度都会有所限制。而 LED 被要求高度集成，低的光成本及高可靠性，EMC支架及倒装CSP基板的加工能力受到较大的挑战。
发明内容
针对现有技术的不足，本公开提出了一种IC封装工艺，所述工艺包括以下步骤：
S1、利用胶将电极粘附在透光基片上以构成IC封装载板；
S2、对所述IC封装载板进行IC封装形成封装体；
S3、降低所述胶的粘性，以使得所述透光基片与所述封装体分离；
S4、对封装体进行表面处理、电测、分割或包装，完成IC封装制程。
本公开具有以下有益效果：
1、可以使载板与IC封装体较容易地分离，同时不会由于使用传统技术中的蚀刻工艺而造成金属的损失。从整体上降低蚀刻的药剂成本、贵金属损失成本以及对于蚀刻废弃物处理的成本。
2、本公开优化了封装工艺，产品封装后,透光基片与封装后的集成电路易于剥离，有利于节约成本和绿色生产，不需在封装厂和基板厂两者间反复的工件流转，从而缩短加工周期，工序间的控制更加顺畅。
3、产品可在封装后再剥离，固晶不需特殊治具，极大提高了工作效率和良品率。
附图说明
图1 为本公开的一个实施例中IC分切后的封装载板截面图；
图2为本公开的一个实施例中蚀刻后的封装载板截面图；
图3为本公开的一个实施例中打线封装后的封装载板截面图；
图4 为本公开的一个实施例中紫外光照射示意图；
图5为本公开的另一个实施例中IC分切后的封装载板截面图；
图6 为本公开的另一个实施例中蚀刻后的封装载板截面图；
图7 为本公开的另一个实施例中打线封装后的封装载板截面图；
图8为本公开的另一个实施例中紫外光照射示意图；
图9为本公开的另一个实施例中光电封装的示意图；
其中：1-芯片，2-封装树脂，3-键合线，4-IC底座，5-I型电极，5’-T型电极，6-光敏胶，7-透光基片，8-防止光照射保护层。
具体实施方式
下面结合附图和具体的实施例对本公开进行具体的说明：
在一个实施例中，本公开提出了一种IC封装工艺，所述工艺包括以下步骤：
S1、利用胶将电极粘附在透光基片以构成IC封装载板；
S2、对所述IC封装载板进行IC封装形成封装体；
S3、降低所述胶的粘性，以使得所述透光基片与所述封装体分离；
S4、对封装体进行表面处理、电测、分割或包装，完成IC封装制程。
通过上述过程，可以使载板与IC封装体分离，同时不会由于使用传统技术中的蚀刻工艺而造成金属的损失。整体上，降低了蚀刻的药剂成本、贵金属损失成本以及对于蚀刻废弃物处理的成本。能够理解，透光基片用以构成IC封装载板时，需要满足封装载板所要求的支撑强度和尺寸稳定性。
在另一个实施例中，所述透光基片具备透光能力并能够耐受封装过程中的温度。能够理解，所述透光能力可以用于降低所述胶的粘性；至于耐受封装过程中的温度，则是不言自明的。
在另一个实施例中，所述胶包括如下任一或者其混合：双面胶、光敏胶。就该实施例而言，其对胶的选型作出了较佳的示例。
在另一个实施例中，所述电极包括通过图形转移、或电镀、或蚀刻所形成的电极。能够理解，本实施例意在示例所述电极的形成方式。
在另一个实施例中，所述电极包括I型或T型结构的电极。下文将会示例这两种结构的电极。此实施例用于对电极结构进行选型。
在另一个实施例中，步骤S3中降低所述胶的粘性，包括通过加热的方式或者通过光照的方式以降低粘性。显然，本实施例提供了一种便捷的分离基片的方式。
在另一个实施例中，所述胶为紫外光照后容易剥离的光敏胶。如此，可以利用紫外光照射来分离基片。
在另一个实施例中，所述电极包括铜箔，且铜箔的一面或者两面镀有金、钯、银、锡、镍中任一或任意组合。就该实施例而言，其限定了电极的一种具体实施方式。
在另一个实施例中，步骤S2中所述的IC封装为能够把一种或一种以上的IC实现并联或串联的电连接封装结构。能够理解，本实施例能够用于不同的电连接封装结构。
在另一个实施例中，步骤S2中所述IC封装的IC包括两个或两个以上电极的发光芯片或集成电路芯片。
在另一个实施例中，参照图1至图4：
如图1所示，其展示了本实施例中的IC封装（SIM卡）工作状态示意图，所述工艺包括(见图2至图4)：
S1、在铜箔两面印刷感光油墨（线路油），烘烤后曝光，显影，再次烘烤，镀镍。铜箔一面整面镀金，一面用掩膜版镀金，刻蚀镍金，退膜。将铜箔电极用双面胶（或光敏胶）和耐高温透光基片压合在一起，并采取措施防止光敏胶曝光。然后再次刻蚀得到IC封装载板（如图2所示）。
S2、产品交付IC厂商封装IC形成封装体（如图3所示）。
S3、用光（或紫外光）对透光基片照射，然后将透光基片以及双面胶（或光敏胶）和封装好的IC剥离（如图4所示）。
S4、进行IC分切，经过包装后完成IC封装制作（如图1所示）。
通过上述过程，可以使载板与IC封装体分离，同时不会由于使用传统技术中的蚀刻工艺而造成金属的损失。从整体上降低蚀刻的药剂成本、贵金属损失成本以及对于蚀刻废弃物处理的成本。
在另一个实施例中：
如图5所示，其展示了本实施例中的IC封装（灯丝）工作状态示意图，所述工艺包括(见图6至图8)：
S1、在铜箔一面印刷感光油墨（线路油），烘烤后曝光，显影，再次烘烤，镀镍；镀金、银等，刻蚀镍金，退膜。将铜箔电极用双面胶（或光敏胶）和耐高温透光基片压合在一起，并采取措施防止光敏胶曝光。再次刻蚀得到IC封装载板（如图6所示）。
S2、产品交付IC厂商封装IC形成封装体（如图7所示）。
S3、用光（或紫外光）对透光基片照射，然后将透光基片以及双面胶（或光敏胶）和封装好的IC剥离（如图8所示）。
S4、进行IC分切，经过包装后完成IC封装制作（如图5所示）。
通过上述过程，可以使载板与IC封装体分离，同时不会由于使用传统技术中的蚀刻工艺而造成金属的损失。从整体上降低蚀刻的药剂成本、贵金属损失成本以及对于蚀刻废弃物处理的成本。本实施例为T型电极与前一个实施例I型电极有所区别。
在另一个实施例中，如图9所示，当用于光电封装时，当所述工艺用于光电封装时，外接电极和近临的芯片电极的引线按曲线设计。例如曲线采用图9所示的回型引线方式，这是为了有利于热传递的阻隔。
本公开能够使得IC封装后的载板与IC封装体分离，优化了封装工艺，有利于节约成本和绿色生产。本公开可应用在IC行业、LED行业，包括：EMC支架、CSP基板、灯丝灯及软灯条板的制造和封装。
以上所述仅为本公开的优选实施例，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
Claims (10)
1.一种IC封装工艺，其特征在于，所述工艺包括以下步骤：
S1、利用胶将电极粘附在透光基片以构成IC封装载板；
S2、对所述IC封装载板进行IC封装形成封装体；
S3、降低所述胶的粘性，以使得所述透光基片与所述封装体分离；
S4、对封装体进行表面处理、电测、分割或包装，完成IC封装制程。
2.根据权利要求1所述的工艺，其特征在于，优选的，所述透光基片具备透光能力并能够耐受封装过程中的温度。
3.根据权利要求1所述的工艺，其特征在于：所述胶包括如下任一或者其混合：双面胶、光敏胶。
4.根据权利要求1所述的工艺，其特征在于：所述电极包括通过图形转移、或电镀、或蚀刻所形成的电极。
5.根据权利要求1所述的工艺，其特征在于：所述电极包括I型或T型结构的电极。
6.根据权利要求1所述的工艺，其特征在于：步骤S3中降低所述胶的粘性，包括通过加热的方式或者通过光照的方式以降低粘性。
7.根据权利要求1所述的工艺，其特征在于：所述胶为紫外光照后容易剥离的光敏胶。
8.根据权利要求1所述的工艺，其特征在于：所述电极包括铜箔，且铜箔的一面或者两面镀有金、钯、银、锡、镍中任一或任意组合。
9.根据权利要求1所述的工艺，其特征在于：
步骤S2中所述的IC封装为能够把一种或一种以上的IC实现并联或串联的电连接封装结构；步骤S2中所述IC封装的IC包括两种或两种以上电极的发光芯片或集成电路芯片。
10.根据权利要求1所述的工艺，其特征在于：当所述工艺用于光电封装时，外接电极和近临的芯片电极的引线按曲线设计。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711361080.3A CN108807192A (zh) | 2017-12-18 | 2017-12-18 | 一种ic封装工艺 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711361080.3A CN108807192A (zh) | 2017-12-18 | 2017-12-18 | 一种ic封装工艺 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108807192A true CN108807192A (zh) | 2018-11-13 |
Family
ID=64095020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711361080.3A Pending CN108807192A (zh) | 2017-12-18 | 2017-12-18 | 一种ic封装工艺 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108807192A (zh) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110707131A (zh) * | 2019-09-05 | 2020-01-17 | 武汉华星光电半导体显示技术有限公司 | 柔性显示面板及其制备方法 |
| US11264579B2 (en) | 2019-09-05 | 2022-03-01 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Flexible display panel and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105161598A (zh) * | 2015-07-27 | 2015-12-16 | 广州市鸿利光电股份有限公司 | 一种基于注塑件的csp封装结构及制造工艺 |
| CN106128965A (zh) * | 2016-07-27 | 2016-11-16 | 桂林电子科技大学 | 一种无基板封装器件的制作方法 |
| CN107342354A (zh) * | 2017-06-28 | 2017-11-10 | 深圳市环基实业有限公司 | 一种ic封装工艺 |
| CN107481945A (zh) * | 2017-08-16 | 2017-12-15 | 华进半导体封装先导技术研发中心有限公司 | 一种晶圆级扇出型堆叠封装工艺方法 |
-
2017
- 2017-12-18 CN CN201711361080.3A patent/CN108807192A/zh active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105161598A (zh) * | 2015-07-27 | 2015-12-16 | 广州市鸿利光电股份有限公司 | 一种基于注塑件的csp封装结构及制造工艺 |
| CN106128965A (zh) * | 2016-07-27 | 2016-11-16 | 桂林电子科技大学 | 一种无基板封装器件的制作方法 |
| CN107342354A (zh) * | 2017-06-28 | 2017-11-10 | 深圳市环基实业有限公司 | 一种ic封装工艺 |
| CN107481945A (zh) * | 2017-08-16 | 2017-12-15 | 华进半导体封装先导技术研发中心有限公司 | 一种晶圆级扇出型堆叠封装工艺方法 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110707131A (zh) * | 2019-09-05 | 2020-01-17 | 武汉华星光电半导体显示技术有限公司 | 柔性显示面板及其制备方法 |
| WO2021042478A1 (zh) * | 2019-09-05 | 2021-03-11 | 武汉华星光电半导体显示技术有限公司 | 柔性显示面板及其制备方法 |
| US11264579B2 (en) | 2019-09-05 | 2022-03-01 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Flexible display panel and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105990265B (zh) | 功率转换电路的封装模块及其制造方法 | |
| US8354688B2 (en) | Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump | |
| US7884472B2 (en) | Semiconductor package having substrate ID code and its fabricating method | |
| KR100685177B1 (ko) | 보드 온 칩 패키지 및 그 제조 방법 | |
| US20110059578A1 (en) | Method of making a semiconductor chip assembly with a post/base heat spreader, a signal post and a cavity | |
| JP2013033910A (ja) | 発光素子搭載用基板、ｌｅｄパッケージ、及びｌｅｄパッケージの製造方法 | |
| KR20010064907A (ko) | 와이어본딩 방법 및 이를 이용한 반도체패키지 | |
| KR970030203A (ko) | Bga 반도체 패키지의 pcb캐리어 프레임 및 그 제조방법 | |
| TWI419272B (zh) | 具有凸柱／基座之散熱座及訊號凸柱之半導體晶片組體 | |
| JP5940799B2 (ja) | 電子部品搭載用パッケージ及び電子部品パッケージ並びにそれらの製造方法 | |
| CN103474406A (zh) | 一种aaqfn框架产品无铜扁平封装件及其制作工艺 | |
| US20130200400A1 (en) | Pcb having individual reflective structure and method for manufacturing light emitting diode package using the same | |
| US8415703B2 (en) | Semiconductor chip assembly with post/base/flange heat spreader and cavity in flange | |
| JP2002033011A (ja) | 発光装置 | |
| CN108807192A (zh) | 一种ic封装工艺 | |
| TWI462351B (zh) | 發光二極體發光模組及其製造方法 | |
| CN107342354B (zh) | 一种ic封装工艺 | |
| CN104900780B (zh) | Led卷对卷封装模组 | |
| JP2013033912A (ja) | 発光素子搭載用基板及びｌｅｄパッケージ | |
| CN106058031B (zh) | 一种集成式高功率紫外led散热板 | |
| CN101640245A (zh) | 发光二极管的芯片倒装焊封装方法 | |
| TW463394B (en) | Chip-type light emitting diode and its manufacturing method | |
| CN211238244U (zh) | 板上芯片型光电器件 | |
| CN112992839B (zh) | 一种用于芯片封装的引线框架及制备方法 | |
| CN212517231U (zh) | 一种半导体芯片封装结构和uv-led灯板 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20181113 |