CN108766491B - A kind of track loop single-particle inversion errors repair method in SRAM type FPGA piece - Google Patents
A kind of track loop single-particle inversion errors repair method in SRAM type FPGA piece Download PDFInfo
- Publication number
- CN108766491B CN108766491B CN201810557018.XA CN201810557018A CN108766491B CN 108766491 B CN108766491 B CN 108766491B CN 201810557018 A CN201810557018 A CN 201810557018A CN 108766491 B CN108766491 B CN 108766491B
- Authority
- CN
- China
- Prior art keywords
- track loop
- track
- error
- loop
- type fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
- G11C11/4125—Cells incorporating circuit means for protecting against loss of information
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
- G06F11/186—Passive fault masking when reading multiple copies of the same data
Abstract
The invention discloses a kind of track loop single-particle inversion errors repair methods in SRAM type FPGA piece, compared to the method for directly directly carrying out three mould votings to three track loop output results, it is not corrected immediately after can malfunctioning to avoid single track loop, accumulation, which occurs, for mistake causes multiple track loops to malfunction, and then the problem of correct result cannot be exported, it is ensured that the mistake of three track loops will not accumulate；Meanwhile error-detection error-correction is synchronized to the channel data of error, it realizes to FPGA track loop without restoration designing is interrupted, ensure that the consistency of three track loop working conditions；It is designed by track loop triplication redundancy and using the anti-fuse type FPGA tri- mould error detection/correction circuit insensitive to single-particle inversion, can reliably find the single-particle inversion mistake of track loop in time.Triplication redundancy and judgement are all made of FPGA software realization, and three moulds implementation method hard compared to FPGA can save circuit resource.
Description
Technical field
The invention belongs to reliability design technology fields, and in particular to track loop single-particle in a kind of SRAM type FPGA piece
Overturn errors repair method.
Background technique
The application fields such as space-based detection, satellite navigation, space flight measurement and control, in order to obtain the target measurement information of needs, signal
Processing system is by needing that received radio signal is captured and tracked.SRAM type field programmable gate array (FPGA)
Since logic gate, multiplier, memory etc. are resourceful in its piece, it is widely used in capturing radio signal and tracks complexity
It is realized in the piece of algorithm.With the raising of SRAM type FPGA integrated level, single-particle inversion effect easily occurs under space radiation environment
It answers, causes circuit function mistake and failure, seriously affect electronic system functional reliability and safety using SRAM type FPGA.
Track loop especially in SRAM type FPGA piece is the closed loop periodically updated that band is fed back, generally comprise correlator,
Loop discriminator, loop filter, local signal generator etc. realize the processing links of signal processing, turn over once single-particle occurs
Turn mistake, wrong data will be by steady spread, it is difficult to by restoring tracking ring to means such as assembly line circuit data emptyings
The normal function on road.
Zhang Lu et al. was in 2011 " microprocessor " page 18 to page 20 of 6 phases " fault-tolerant skills in the space FPGA delivered of volume 32
In an art research " text, the SRAM type FPGA anti-single particle method for turning that a kind of pair of configuration memory carries out dynamic refresh is proposed.
Yang Yuchen et al. is in page 34 to page 37 " triplication redundancy feedback error corrections delivered of 2017 " space electronic technology " 2 phases of volume 14
In application of the technology in a spaceborne circuit Design of Reinforcement and realization " text, a kind of triplication redundancy feedback error correction method is proposed, is mentioned
The anti-single particle of high circuit overturns ability.
The shared deficiency of the above method is: (1) due to particularity of the Closed loop track circuit with memory function in piece, only
SRAM type FPGA configuration memory is carried out to refresh the reparation that can not achieve to Closed loop track circuit single-particle inversion mistake；(2)
The single-particle inversion mistake of Closed loop track circuit in its piece can be removed by the methods of reloading to SRAM type FPGA, but can be interrupted
The normal work of circuit.
Summary of the invention
In view of this, the object of the present invention is to provide track loop single-particle inversion mistakes in a kind of SRAM type FPGA piece to repair
Compound method, do not interrupt track loop operate normally under the premise of, effectively solve single-particle inversion capability error, it is undistorted restore with
The normal work of track loop.
A kind of track loop single-particle inversion errors repair method, includes the following steps:
Step 1 replicates three parts of exampleization to track loop inside SRAM type FPGA, receives external input signal respectively and divides
Step is handled；One processing links of every completion, obtained intermediate processing results are stored to corresponding distributor；
Step 2, for 3 track loops the corresponding distributor storage of each processing links intermediate treatment knot
Fruit makes decisions, and obtains court verdict；
Step 3 is proceeded as follows according to court verdict:
If a), the intermediate processing results error of only one track loop, centre corresponding to the track loop of error
Register carries out error correcting；
B), if there is the intermediate processing results of two or more track loops malfunction, then SRAM type FPGA is carried out
It resets and resets；
If c) occurring without any mistake, without any error-correction operation.
Preferably, making decisions in the step 2 to intermediate processing results, court verdict is obtained method particularly includes:
The intermediate processing results of 3 track loops are indicated with A, B, C distribution；S indicates three moduluses according to court verdict；By A, B,
Step-by-step asks with after that step-by-step is asked or, obtain court verdict S again to C two-by-two, that is, indicates are as follows:
S=AB+AC+BC；
To be obtained after A, B, C two-by-two step-by-step exclusive or again 1 bit interlocutory judgment result again two two-phases with, obtained several tracking
Loop fault, the then logic that state is adjudicated are as follows:
Wherein, T1Indicate whether the data of track loop 1 and track loop 2 are completely the same, T2Indicate track loop 1 and with
Whether the data of track loop 3 are completely the same, T3Indicate whether the data of track loop 2 and track loop 3 are completely the same, 0 indicates
Unanimously, 1 indicate inconsistent；
The serial number of finally judgement error track loop, logical expression are as follows:
E1=T1T2
E2=T1T3
E3=T2T3
Wherein, E1Indicate whether track loop 1 malfunctions, E2Indicate whether track loop 2 malfunctions, E3Indicating track loop 3 is
No error；1 indicates error, and 0 indicates not malfunction.
Preferably, the step 2 and step 3 are realized in anti-fuse type FPGA.
Further, the anti-fuse type FPGA carries out dynamic refresh to SRAM type FPGA configuration data.
The invention has the following beneficial effects:
1) proposed by the present invention compared to the method for directly directly carrying out three mould votings to three track loop output results
Method is not corrected immediately after can malfunctioning to avoid single track loop, and accumulation, which occurs, for mistake causes multiple track loops to malfunction,
And then the problem of correct result cannot be exported, it is ensured that the mistake of three track loops will not accumulate；Meanwhile error is led to
Track data synchronizes error-detection error-correction, realizes to FPGA track loop without restoration designing is interrupted, ensure that three tracking rings
The consistency of road working condition.
2) the anti-fuse type FPGA tri- insensitive to single-particle inversion is designed and utilized by track loop triplication redundancy
Mould error detection/correction circuit can reliably find the single-particle inversion mistake of track loop in time.Triplication redundancy is all made of with judgement
FPGA software realization, three moulds implementation method hard compared to FPGA, can save circuit resource.
3) SRAM type FPGA configuration data dynamic refresh and track loop work independently, and solve SRAM type FPGA configuration and deposit
The cumulative effect of reservoir single-particle inversion, and will not influence track loop normal work.
Detailed description of the invention
Fig. 1 is that the present invention is based on track loop errors repair method schematics in SRAM type FPGA piece.
Specific embodiment
The present invention will now be described in detail with reference to the accompanying drawings and examples.
One kind of the invention is based on track loop errors repair method in SRAM type FPGA piece, as shown in Figure 1, using SRAM
Type FPGA realizes the signal processing function of radio system track loop, using the anti-fuse type insensitive to single-particle inversion
FPGA puts to the vote to the processing result of SRAM type FPGA internal trace loop, when noting abnormalities to the inside number of track loop
According to being corrected；In addition, anti-fuse type FPGA also completes to carry out dynamic refresh to SRAM type FPGA configuration data.Wherein, SRAM
Track loop in type FPGA is designed using triplication redundancy, that is, includes track loop 1,2 and 3；The composition electricity of anti-fuse type FPGA
Road includes loading control circuit, dynamic refresh control circuit and track loop error-detection error-correction processing circuit completely.Wherein, completely plus
Carry control circuit to radio system power on or system reset after the configuration data of SRAM type FPGA load；Dynamic refresh
Control circuit carries out periodical dynamic refresh to the configuration data of SRAM type FPGA；Track loop error-detection error-correction processing circuit pair
The track loops of three redundancies in SRAM type FPGA carries out error-detection error-correction processing, comprising track loop data error detection unit and with
Track loop data error correction unit.
By taking the SRAM type FPGA XC5VFX130T of the anti-fuse type FPGA and Xilinx company of Actel company as an example, this hair
Bright track loop errors repair method specifically comprises the following steps:
(1) after powering on, the complete load control unit of anti-fuse FPGA generates configurable clock generator and configuration control signal, from matching
It sets and reads configuration data stream in memory, SRAM type FPGA is loaded completely.
(2) completely after the completion of load, control unit generation load complement mark completely is loaded completely and is exported to dynamic refresh
Control unit starts dynamic refresh.Dynamic refresh control unit reads configuration data stream from configuration memory, and therefrom separates
The control command of SRAM type FPGA and configuration data part out, to the configuration data in addition to Block RAM of SRAM type FPGA
Refreshed.This operation is realized by the write-in data length in change configuration data stream.By taking XC5VFX130T as an example, configuration
The 235th~238 byte initial data is 0x50177910 in data flow, and characterization write-in data length is that 0x177910 word is (every
A word includes 4 bytes), the first designated length 0x1040DC (corresponding 1065180 words) are changed to, are only written with realizing
Configuration data in addition to Block RAM.Consideration configuration data stream length is that (each word includes 4 to the byte of L=1065180 × 4
Byte), configured rate v=8.192Mbyte/s can then calculate the acquisition minimum dynamic refresh time are as follows:
Consider certain time allowance, the dynamic refresh period is set as T > 0.751s.
(3) completely after the completion of load, 3 track loops inside SRAM type FPGA are started to work, respectively to external input
Signal is handled step by step, one processing links of every completion, and obtained intermediate processing results are saved in corresponding intermediate deposit
In device；Another aspect track loop error detection/correction circuit tracks complement mark according to loop update cycle and starts to work simultaneously, with
Track loop error checking unit generates read-write control signal and address in the distributor in 3 track loops of SRAM type FPGA
Data be read out, and put to the vote respectively to the corresponding distributor data of the same treatment link of 3 track loops,
It is illustrated by taking the voting logic of the corresponding 3 distributor data of one of same treatment link as an example, specifically:
S=AB+AC+BC
The logical expressions A, B, C two-by-two step-by-step ask with after again step-by-step ask or, wherein A indicate 1 data of track loop, B indicate
2 data of track loop, C indicate 3 data of track loop, S indicate three moduluses according to court verdict, i.e., two-way in A, B, C (or more)
Data.It adjudicates to obtain the serial number of several track loops errors and error track loop by state simultaneously.State judgement
Logic are as follows:
E1=T1T2
E2=T1T3
E3=T2T3
The logical expressions A, B, C obtain 1 bit intermediate result two two-phases and T again after step-by-step exclusive or two-by-two1Indicate tracking ring
Whether road 1 is completely the same (0 expression is consistent, and 1 indicates inconsistent) with the data of track loop 2, T2Indicate track loop 1 and tracking
Whether the data of loop 3 are completely the same, T3Indicate whether the data of track loop 2 and track loop 3 are completely the same, E1Indicate with
Whether track loop 1 malfunctions (1 indicates error, and 0 indicates not malfunction), E2Indicate whether track loop 2 malfunctions, E3Indicate track loop 3
Whether malfunction.
In this way, each processing links can obtain a voting result；
(4) each voting result obtained for track loop error checking unit, track loop error correction unit form difference
Processing strategie, specifically:
If a) the corrupt data of only one track loop, according to the data voting knot of track loop error checking unit generation
Fruit and track loop error flag, track loop error correction unit generates corresponding write enable signal and address, by correct data
Court verdict S is written back in SRAM type FPGA in the corresponding distributor of track loop that malfunctions.
B) it if there is the corrupt data of two or more track loops, then generates multi-track loop fault mark and gives
Full loaded circuit loads SRAM type FPGA by complete loaded circuit completely, realizes and resets.
If c) occurring without any mistake, i.e., the data of three track loops are completely the same, without any error-correction operation；
(5) step 3)~4 are repeated), complete the inspection of three track loop whole distributor data in SRAM type FPGA
Wrong correction process.
In conclusion the above is merely preferred embodiments of the present invention, being not intended to limit the scope of the present invention.
All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should be included in of the invention
Within protection scope.
Claims (3)
1. a kind of track loop single-particle inversion errors repair method, which comprises the steps of:
Step 1 replicates three parts of exampleization to track loop inside SRAM type FPGA, receives external input signal and step by step respectively
It is handled；One processing links of every completion, obtained intermediate processing results are stored to corresponding distributor；
Step 2, for 3 track loops the corresponding distributor storage of each processing links intermediate processing results into
Row judgement, obtains court verdict；
Step 3 is proceeded as follows according to court verdict:
If a), the intermediate processing results error of only one track loop, intermediate deposit corresponding to the track loop of error
Device carries out error correcting；
B), if there is the intermediate processing results of two or more track loops malfunction, then SRAM type FPGA is zeroed out
It resets；
If c) occurring without any mistake, without any error-correction operation；
Wherein, intermediate processing results are made decisions in the step 2, obtain court verdict method particularly includes:
The intermediate processing results of 3 track loops are indicated with A, B, C distribution；S indicates three moduluses according to court verdict；By A, B, C two
Two step-by-steps ask with after that step-by-step is asked or, obtain court verdict S again, that is, indicate are as follows:
S=AB+AC+BC；
To be obtained after A, B, C two-by-two step-by-step exclusive or again 1 bit interlocutory judgment result again two two-phases with, obtained several track loops
Error, the then logic that state is adjudicated are as follows:
Wherein, T1Indicate whether the data of track loop 1 and track loop 2 are completely the same, T2Indicate track loop 1 and tracking ring
Whether the data on road 3 are completely the same, T3Indicate whether the data of track loop 2 and track loop 3 are completely the same, 0 indicates consistent,
1 indicates inconsistent；
The serial number of finally judgement error track loop, logical expression are as follows:
E1=T1T2
E2=T1T3
E3=T2T3
Wherein, E1Indicate whether track loop 1 malfunctions, E2Indicate whether track loop 2 malfunctions, E3Indicate whether track loop 3 goes out
It is wrong；1 indicates error, and 0 indicates not malfunction.
2. track loop single-particle inversion errors repair method as described in claim 1, which is characterized in that the step 2 and
Step 3 is realized in anti-fuse type FPGA.
3. track loop single-particle inversion errors repair method as claimed in claim 2, which is characterized in that the anti-fuse type
FPGA carries out dynamic refresh to SRAM type FPGA configuration data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810557018.XA CN108766491B (en) | 2018-06-01 | 2018-06-01 | A kind of track loop single-particle inversion errors repair method in SRAM type FPGA piece |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810557018.XA CN108766491B (en) | 2018-06-01 | 2018-06-01 | A kind of track loop single-particle inversion errors repair method in SRAM type FPGA piece |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108766491A CN108766491A (en) | 2018-11-06 |
| CN108766491B true CN108766491B (en) | 2019-05-31 |
Family
ID=64001850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810557018.XA Active CN108766491B (en) | 2018-06-01 | 2018-06-01 | A kind of track loop single-particle inversion errors repair method in SRAM type FPGA piece |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108766491B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109669823B (en) * | 2018-12-03 | 2022-04-05 | 中国工程物理研究院电子工程研究所 | Multi-bit upset error resisting chip reinforcement method based on improved triple modular redundancy system |
| CN112447201A (en) * | 2020-10-29 | 2021-03-05 | 中国空间技术研究院 | System-level space single particle protection method suitable for SRAM type FPGA product |
| CN112433777A (en) * | 2020-10-30 | 2021-03-02 | 深圳市紫光同创电子有限公司 | Dynamic refreshing method and device for configuration data of SRAM (static random Access memory) type FPGA (field programmable Gate array) |
| CN113018698B (en) * | 2021-02-26 | 2023-03-28 | 上海联影医疗科技股份有限公司 | Single-particle overturn repair method and device, radiotherapy system, electronic equipment and medium |
| CN113721135B (en) * | 2021-07-22 | 2022-05-13 | 南京航空航天大学 | SRAM type FPGA fault online fault tolerance method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104867122A (en) * | 2015-05-29 | 2015-08-26 | 北京理工大学 | Infrared self-adaptive non-uniformity correction and detail enhanced cascade processing method |
| CN105388384A (en) * | 2015-12-15 | 2016-03-09 | 北京理工大学 | Whole-satellite single-particle soft error fault simulation system |
| CN107894898A (en) * | 2017-11-28 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | Refresh device, implementation method and the fpga chip with error correction on SRAM type FPGA pieces |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6838899B2 (en) * | 2002-12-30 | 2005-01-04 | Actel Corporation | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array |
| US7746682B2 (en) * | 2005-11-03 | 2010-06-29 | Agata Logic Inc. | SEU hardened latches and memory cells using programmable resistance devices |
| CN101551762B (en) * | 2009-05-15 | 2011-04-06 | 中国人民解放军国防科学技术大学 | Spaceborne processing platform resisting single event effect |
| CN103971732A (en) * | 2014-04-30 | 2014-08-06 | 浙江大学 | Method and system for monitoring single event upset effect of FPGA (field programmable gate array) and correcting reloading |
| CN104021051A (en) * | 2014-06-06 | 2014-09-03 | 上海航天电子通讯设备研究所 | Monitoring and correcting device for single event upset fault of satellite borne spread spectrum responder |
| CN104063292B (en) * | 2014-06-27 | 2017-04-19 | 中国航天科技集团公司第五研究院第五一三研究所 | On-track reconfigurable method |
| CN104317662B (en) * | 2014-09-11 | 2018-01-26 | 上海卫星工程研究所 | The in-orbit single-particle inversion protection quantitative estimation methods of SRAM type FPGA |
| CN105045672B (en) * | 2015-07-24 | 2018-07-06 | 哈尔滨工业大学 | A kind of multi-level fault tolerance based on SRAM FPGA reinforces satellite information processing system |
| CN106531224B (en) * | 2016-10-25 | 2019-07-16 | 哈尔滨工业大学 | A kind of RAM data reliability reinforcing device and method based on SRAM type FPGA |
| CN107741559B (en) * | 2017-10-12 | 2020-07-17 | 电子科技大学 | Single event upset test system and method under space radiation environment |
| CN108055031B (en) * | 2017-12-14 | 2021-04-13 | 北京时代民芯科技有限公司 | Self-recovery triple modular redundancy structure for resisting single-particle soft error accumulation |
-
2018
- 2018-06-01 CN CN201810557018.XA patent/CN108766491B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104867122A (en) * | 2015-05-29 | 2015-08-26 | 北京理工大学 | Infrared self-adaptive non-uniformity correction and detail enhanced cascade processing method |
| CN105388384A (en) * | 2015-12-15 | 2016-03-09 | 北京理工大学 | Whole-satellite single-particle soft error fault simulation system |
| CN107894898A (en) * | 2017-11-28 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | Refresh device, implementation method and the fpga chip with error correction on SRAM type FPGA pieces |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108766491A (en) | 2018-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108766491B (en) | A kind of track loop single-particle inversion errors repair method in SRAM type FPGA piece | |
| US6141770A (en) | Fault tolerant computer system | |
| KR20010005956A (en) | Fault tolerant computer system | |
| CN103971732A (en) | Method and system for monitoring single event upset effect of FPGA (field programmable gate array) and correcting reloading | |
| CN103325411B (en) | A kind of anti-single particle overturn hardened system and method thereof for FPGA | |
| CN103984630B (en) | Single event upset fault processing method based on AT697 processor | |
| US7739565B1 (en) | Detecting corruption of configuration data of a programmable logic device | |
| CN114783502A (en) | Method for screening weak bits in a memory array | |
| CN103500125B (en) | A kind of radiation-resistant data handling system based on FPGA and method | |
| CN110690917B (en) | Space-borne single-particle-upset-resisting system of transceiver | |
| CN104579313A (en) | On-orbit SRAM type FPGA fault detection and restoration method based on configuration frame | |
| CN106021169A (en) | Aerospace computer and refreshing and upgrading method for nonvolatile storage apparatus thereof | |
| CN102968363A (en) | Apparatus and method for the protection and for the non-destructive testing of safety-relevant registers | |
| CN104572326A (en) | Read-back self-reconfiguration-based fault-tolerant method for SoPC (Programming System on Chip) chip | |
| CN111708623B (en) | Star affair management and star map processing integrated platform | |
| CN109669823A (en) | Anti- Multiple-bit upsets error chip reinforcement means based on modified triple-modular redundancy system | |
| Rivers et al. | Reliability challenges and system performance at the architecture level | |
| Xie et al. | An automated FPGA-based fault injection platform for granularly-pipelined fault tolerant CORDIC | |
| CN115687230A (en) | Arrow-mounted triple-modular redundancy computer system | |
| Cherezova et al. | Understanding fault-tolerance vulnerabilities in advanced SoC FPGAs for critical applications | |
| Gomez-Cornejo et al. | Data content scrubbing approach for sram based fpga designs | |
| Burlyaev et al. | System fault-tolerance analysis of COTS-based satellite on-board computers | |
| JP3139738B2 (en) | Logic circuit | |
| US11120168B2 (en) | Method for protecting an FPGA against natural radiations | |
| CN108631772B (en) | Triple-modular redundancy circuit structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |