CN101551762B - Spaceborne processing platform resisting single event effect - Google Patents

Abstract

The invention discloses an on-board processing platform with anti-single event effect capability, which includes a high-reliability monitoring unit, a non-volatile memory, a field programmable logic gate array and more than one DSP, the high-reliability monitoring unit and other All parts are connected by local bus, and the field programmable logic gate array and DSP are connected by high-speed bus; the high-reliability monitoring unit is used to detect and repair the single event reversal in the field programmable logic gate array and DSP. The invention is a space-borne processing platform with simple structure and principle, convenient operation, high reliability, good stability and anti-single event effect capability.

Description

On-board processing platform with anti-single event effect capability

technical field

The invention mainly relates to the field of space instrument engineering, in particular to a space-borne processing platform capable of resisting single-event effects.

Background technique

Cosmic space is full of various particles from the vast universe: protons, electrons, alpha particles, heavy ions, gamma rays, etc. The radiation effects caused by these particles, especially the single event effect, affect the reliability of space electronic instruments.

In recent years, with the development and application of VLSI (Very Large Scale Integrated circuits) technology, Field Programmable Logic Gate Array (FPGA, Field Programmable Gate Array) and Digital Signal Processor (DSP, Digital Signal Processor) , relying on its powerful signal processing capability and superior interface performance to gradually replace the traditional single-chip microcomputer, become an important part of the spaceborne high-speed signal processing platform, and began to be applied in aerospace engineering.

With the improvement of the manufacturing process, the operating frequency of VLSI is getting higher and lower, and the working voltage is getting lower and lower, which makes the on-board signal processing platform more sensitive to the single event effect, and FPGA, DSP, etc. are prone to single-event effects. Particle flipping and other glitches. VLSI such as FPGA and DSP rely on their complex logical relationships to complete various functions. In addition to the physical connection relationship between each transistor, through the later logical function design, such as FPGA hardware function description or DSP programming, Logical function-based connections and timing relationships are also created with each other. From an application point of view, the impact of single event effects on FPGAs and DSPs has been transmitted or coupled to larger areas from the transient, small-area, and single-transistor areas through the logic functions of sequential circuits. It can be seen that with the decrease of the feature size and the increase of the density of the VLSI transistor process, the reduction of the core operating voltage and the substantial increase of the operating frequency, the spaceborne signal processing platform is more and more seriously affected by the single event effect. The proportion of single event effect failures will further increase.

At present, in the on-board signal processing platform, on the one hand, high-performance, large-scale, high-grade FPGA and DSP devices are extremely expensive; Due to the large number of on-chip SRAM (Static Random Access Memory) used in low-priced FPGA and DSP devices, the probability of single event effects caused by high-energy particles in space is greatly increased, which seriously affects the normal operation of FPGA and DSP devices in the space environment.

Contents of the invention

The technical problem to be solved by the present invention is: aiming at the technical problems existing in the prior art, the present invention provides an on-board processing platform with simple structure, simple operation, high reliability, good stability and anti-single event effect ability .

In order to solve the above technical problems, the present invention adopts the following technical solutions.

An on-board processing platform with anti-single event effect capability is characterized in that it includes a highly reliable monitoring unit, a non-volatile memory, a field programmable logic gate array and more than one DSP, and the highly reliable monitoring unit and other All parts are connected by local bus, and the field programmable logic gate array and DSP are connected by high-speed bus; the high-reliability monitoring unit is used to detect and repair the single event reversal in the field programmable logic gate array and DSP.

As a further improvement of the present invention:

The high-reliability monitoring unit includes a detection and repair controller, a DSP monitoring module, a DSP repair module, an FPGA detection module, an FPGA repair module, a DSP monitoring interface, an FPGA monitoring interface, and an NVRAM interface interconnected by a bus.

The detection and repair controller is used for monitoring and receiving device repair request instructions issued by the DSP monitoring module and the FPGA detection module, and sending device repair commands to the DSP repair module and the FPGA repair module.

Described FPGA detection module comprises FPGA configuration data reading controller, FPGA configuration data read-back controller and FPGA configuration data detection controller, and described FPGA configuration data reading controller reads from non-volatile memory by NVRAM interface FPGA original configuration data, FPGA configuration data readback controller reads back FPGA running configuration data through the FPGA monitoring interface, FPGA configuration data detection controller compares and analyzes the original configuration data and running configuration data, when a comparison mismatch occurs , sending an FPGA repair request instruction to the detection and repair controller through the internal data bus.

Described FPGA repairing module comprises FPGA configuration data reading controller and FPGA configuration data writing controller, and FPGA configuration data reading controller receives the FPGA repairing command of detecting and repairing controller by local bus, reads and stores in non-volatile memory by NVRAM interface. The FPGA original configuration data in the volatile memory, the FPGA configuration data writing controller writes the FPGA original configuration data into the FPGA through the FPGA monitoring interface, and completes the restoration of the FPGA.

Described DSP monitoring module comprises DSP state information read-back controller and DSP state discriminator, and read-back controller monitors and receives DSP running state information by DSP monitoring interface, and discriminator discriminates DSP state according to DSP running state information, when monitoring When the DSP "runs to death" or "runs away", a DSP core reset command is generated and sent to the DSP for reset, or a DSP repair request command is generated to the detection and repair controller to wait for the DSP to be repaired.

Described DSP repairing module comprises DSP program data reading controller and DSP program data writing controller, and DSP program data reading controller receives the DSP repairing order of detecting and repairing controller by internal data bus, reads and stores in by NVRAM interface The DSP program data in the non-volatile memory, the DSP program data writing controller writes the DSP program data into the DSP through the DSP monitoring interface, and completes the repair of the DSP.

Compared with the prior art, the present invention has the advantages of:

1. The present invention adopts the interconnection structure of "FPGA plus multiple DSPs", which greatly improves the expansibility, processing performance and computing power of the platform;

2. The present invention is equipped with a highly reliable monitoring unit, which is used to detect and repair FPGA and DSP single event flipping, and reduces the requirements of the on-board processing platform for FPGA and DSP device levels, so that low-level FPGA and DSP devices can be used Applied to space instrument engineering, greatly reducing costs;

3. The readback process of the FPGA configuration memory of the present invention adopts a specific timing and uses an independent configuration frame as a unit to read back the FPGA configuration memory, without interfering with the operation of the normal logic function of the FPGA;

4. The repair process of the FPGA configuration memory of the present invention adopts a specific timing and uses an independent configuration frame as a unit to repair the wrong configuration frame of the FPGA configuration memory, without interfering with the normal operation of other logic functions of the FPGA;

5. The highly reliable monitoring unit of the present invention is an integrated circuit, implemented on a single FPGA, with simple structure and high degree of modularization.

Description of drawings

Fig. 1 is a structural representation of the on-board processing platform of the present invention;

Fig. 2 is a schematic structural view of the highly reliable monitoring unit of the present invention;

Fig. 3 is the structural representation of FPGA detection module of the present invention;

Fig. 4 is the structural representation of FPGA repair module of the present invention;

Fig. 5 is the structural representation of DSP monitoring module of the present invention;

Fig. 6 is the structural representation of DSP repairing module of the present invention;

Fig. 7 is a flowchart of FPGA detection and repair of the present invention;

Fig. 8 is the read-back flowchart of FPGA configuration memory of the present invention;

Fig. 9 is a flowchart of repairing FPGA configuration memory of the present invention;

Fig. 10 is a flow chart of DSP detection and repair in the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with specific embodiments and accompanying drawings.

As shown in Figure 1, a kind of on-board processing platform with anti-single event effect ability of the present invention is made up of highly reliable monitoring unit, nonvolatile memory, DSP and FPGA; Non-volatile memory, DSP and FPGA are connected through standard interfaces, and FPGA and each DSP are interconnected by high-speed data bus;

As shown in Figure 2, the high-reliability monitoring unit in this embodiment is designed and implemented by ActelFPGA, which is programmed once for high-grade radiation-resistant device antifuse, including a detection and repair controller, an FPGA detection module, an FPGA repair module, a DSP monitoring module, and a DSP repair The module and FPGA monitoring interface, DSP monitoring interface and NVRAM interface, each module and interface are interconnected through the local bus; the detection and repair controller is a logic processor in the high reliability monitoring unit, which monitors and receives the signals sent by the FPGA monitoring module and DSP detection module. The repair request command is sent to the FPGA repair module and the DSP repair module; the FPGA detection module compares and analyzes the FPGA original configuration data and the running configuration data, detects the single event flip, and sends the FPGA repair command to the detection and repair controller through the local bus. Repair request command; the FPGA repair module receives the FPGA repair command from the detection and repair controller through the local bus, reads the FPGA original configuration data stored in the non-volatile memory through the NVRAM interface, and writes the FPGA original configuration data through the FPGA monitoring interface. into the FPGA to complete the repair of the FPGA; the DSP monitoring module receives the running status information regularly reported by the DSP through the DSP monitoring interface and judges it. When it detects that the DSP is "running dead" or "running away", it will generate a DSP core reset command Send to the DSP for reset, or generate a DSP repair request command to the detection and repair controller to wait for the DSP to be repaired; the DSP repair module receives the DSP repair command from the detection and repair controller through the local bus, and reads the DSP stored in the non-volatile memory through the NVRAM interface. DSP program data in DSP and write DSP program data into DSP through DSP monitoring interface to complete the repair of DSP; data transfer between volatile memories.

As shown in Figure 3, the FPGA detection module in this embodiment is a logic processor in the highly reliable monitoring unit, and is made up of FPGA configuration data reading controller, FPGA configuration data readback controller and FPGA configuration data detector, reads The fetch controller is connected to the non-volatile memory through the NVRAM interface, the read-back controller is connected to the FPGA device through the standard FPGA monitoring interface, the detector is connected to the detection and repair controller through the local bus, and the read-out controller, read-back controller and The detectors are interconnected through a local bus; the FPGA configuration data reading controller reads the original FPGA configuration data stored in the non-volatile memory, and the FPGA configuration data readback controller reads back the FPGA running configuration data through the FPGA monitoring interface. The FPGA configuration data detector compares and analyzes the original configuration data and the running configuration data byte by byte, and sends an FPGA repair request command to the detection and repair controller when a comparison mismatch occurs.

As shown in Figure 4, the FPGA repair module in this embodiment is a logic processor in the highly reliable monitoring unit, which is composed of an FPGA configuration data reading controller and an FPGA configuration data writing controller, and the reading controller passes internal data The bus is connected to the detection and repair controller, the write controller is connected to the FPGA device through the standard FPGA monitoring interface, and the read controller and the write controller are interconnected through the internal data bus; the read controller receives the data from the detection and repair controller. The FPGA repair command reads the FPGA original configuration data stored in the non-volatile memory; the FPGA configuration data writing controller writes the FPGA original configuration data into the FPGA to complete the FPGA repair.

As shown in Figure 5, the DSP monitoring module in this embodiment is a logic processor in the highly reliable monitoring unit, is made up of DSP state information read-back controller and DSP state discriminator, read-back controller communicates with through standard DSP monitoring interface The DSP device is connected, the discriminator is connected with the detection and repair controller through the local bus, and the readback controller and the discriminator are interconnected through the local bus; the readback controller monitors and receives DSP operation status information through the DSP monitoring interface; the discriminator according to The DSP running status information judges the DSP status. When the DSP is detected as "running dead" or "running away", a DSP core reset command is generated and sent to the DSP for reset, or a DSP repair request command is generated to the detection and repair controller to wait for the DSP to be repaired. .

As shown in Figure 6, the DSP repair module in this embodiment is a logical processor in the highly reliable monitoring unit, which is composed of a DSP program data read controller and a DSP program data write controller, and the read controller passes through the NVRAM interface It is connected with the non-volatile memory, the write controller is connected with the DSP device through the DSP monitoring interface, and the read controller and the write controller are interconnected through the local bus; the read controller receives the DSP repair of the detection and repair controller Command, read the DSP program data stored in the non-volatile memory, write the DSP program data into the DSP in the controller, and complete the repair of the DSP.

As shown in Figure 7, in the present embodiment, the steps of the specific embodiment of the FPGA detection and repair method adopted by the present invention are:

① Obtain FPGA configuration data information by executing the FPGA configuration memory readback process through the standard FPGA monitoring interface;

②Read FPGA original configuration data from non-volatile memory through NVRAM interface;

③ Compare and analyze the FPGA configuration data obtained in step ① and step ②. If the comparison is found to be mismatched, it is considered that a single event flip has occurred, and step ④ is performed; otherwise, step ① is performed;

④ Execute the FPGA configuration memory repair process through the standard FPGA monitoring interface to repair the configuration data in the FPGA configuration memory, and proceed to step ①.

As shown in Figure 8, in the present embodiment, the FPGA configuration memory read-back process that the present invention adopts, its steps and command word and function are:

①Send a synchronous command word (AA-99-55-66) to the FPGA through the standard FPGA monitoring interface to start FPGA configuration memory readback; ②Send the device ID command word (30-00-C0-01 ), write the device ID number to the IDCODE register of the FPGA; ③ send the cyclic verification reset command word (00-00-00-07) to the FPGA through the standard FPGA monitoring interface, and reset the cyclic verification CRC calculation logic of the FPGA; ④ pass the standard The FPGA monitoring interface sends the start frame address command word (30-00-20-01) to the FPGA to set the start address of the readback configuration frame; ⑤ send the readback configuration memory command word (00- 00-00-04), the flag is ready to read back the configuration memory data of the FPGA; ⑥ send the configuration frame length command word (28-00-60-00) to the FPGA through the standard FPGA monitoring interface, and set the length of the readback configuration frame; ⑦ Read back a configuration frame data from the FPGA through the standard FPGA monitoring interface, and return the FPGA configuration frame data from the FPGA; ⑧ Send the cancel synchronization status command word (00-00-00-0D) to the FPGA through the standard FPGA monitoring interface, and end the FPGA configuration memory read back.

As shown in Figure 9, in the present embodiment, the steps of the specific embodiment of the FPGA configuration memory repair process adopted by the present invention are:

①Send a synchronous command word (AA-99-55-66) to the FPGA through the standard FPGA monitoring interface to start writing the FPGA configuration memory; ②Send the cycle check logic reset command word (00-00- 00-07), reset the cyclical check CRC calculation logic of the FPGA; ③ send the device ID command word (30-01-C0-01) to the FPGA through the standard FPGA monitoring interface, and write the device ID number to the IDCODE register of the FPGA; ④ pass The standard FPGA monitoring interface sends the configuration frame length command word (30-01-60-01) to the FPGA to set the length of the configuration frame to be written; ⑤ Send the ready to write data command word (00-00-00 -01), the flag is ready to be written into the configuration memory data of the FPGA; ⑥ Send the configuration frame address command word (30-00-20-01) to the FPGA through the standard FPGA monitoring interface, and set the starting address for writing the configuration frame; ⑦ Pass The standard FPGA monitoring interface sends a configuration frame data to the FPGA, and writes a configuration frame data to the FPGA, with a total of 52 words; ⑧ sending the cancel synchronization status command word (00-00-00-0D) to the FPGA through the standard FPGA monitoring interface, End FPGA configuration memory write.

As shown in Figure 10, in the present embodiment, the steps of the specific embodiment of the DSP detection and repair method adopted by the present invention are:

① Obtain the DSP running status information by reading back through the standard DSP monitoring interface;

②Discrimination of DSP status information, if it is judged that the DSP program flow is abnormal, proceed to step ③, if it is judged that a single event flip occurs in the DSP memory, proceed to step 5, otherwise proceed to step ①;

③ Reset the DSP core, wait for the DSP program to boot, if the DSP program boots successfully, proceed to step ④, otherwise proceed to step ⑤;

④Activate DSP, go to step ①;

⑤ Read the DSP program data from the non-volatile memory through the NVRAM interface, write the DSP program data into the DSP device through the standard DSP monitoring interface, and proceed to step ①.

The above descriptions are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention should also be regarded as the protection scope of the present invention.

Claims (6)

1. spaceborne processing platform with anti-single particle effect capability, it is characterized in that: it comprises by highly reliable monitoring unit, nonvolatile memory, field programmable gate array and more than one DSP, highly reliable monitoring unit and other each several parts adopt local bus interconnected, adopt high-speed bus interconnected between field programmable gate array and the DSP; Described highly reliable monitoring unit is used for the single-particle inversion in field programmable gate array and the DSP is detected and repairs, described highly reliable monitoring unit comprises the detection repair controller by bus interconnection, the DSP monitoring module, DSP repairs module, the FPGA detection module, FPGA repairs module and DSP monitor-interface, FPGA monitor-interface and NVRAM interface, described detection repair controller is direct and DSP monitoring module by bus, DSP repairs module, the FPGA detection module, FPGA repairs module and is connected with the NVRAM interface, the DSP monitor-interface is repaired module with the DSP monitoring module with DSP by bus and is connected, and the FPGA monitor-interface is repaired module with the FPGA detection module with FPGA by bus and is connected; Described FPGA detection module is realized the FPGA single-particle inversion is detected by the FPGA monitor-interface; Described FPGA repairs module and by the FPGA monitor-interface FPGA single-particle inversion is repaired; Described DSP detection module is realized the DSP single-particle inversion is detected by the DSP monitor-interface; Described DSP repairs module and by the DSP monitor-interface DSP single-particle inversion is repaired.

2. the spaceborne processing platform with anti-single particle effect capability according to claim 1, it is characterized in that: described detection repair controller is used to monitor and receive the device that DSP monitoring module and FPGA detection module send and repairs request instruction, and repairs module and FPGA to DSP and repair module and send device reparation order.

3. the spaceborne processing platform with anti-single particle effect capability according to claim 1, it is characterized in that: described FPGA detection module comprises FPGA configuration data Read Controller, FPGA configuration data retaking of a year or grade controller and FPGA configuration data detect controller, described FPGA configuration data Read Controller reads field programmable gate array original configuration data by the NVRAM interface from nonvolatile memory, FPGA configuration data retaking of a year or grade controller is by the operation configuration data of FPGA monitor-interface retaking of a year or grade field programmable gate array, the FPGA configuration data detects controller original configuration data and operation configuration data is compared, when the generation comparison does not match, send field programmable gate array reparation request instruction to detecting repair controller by internal data bus.

4. the spaceborne processing platform with anti-single particle effect capability according to claim 1, it is characterized in that: described FPGA repairs module and comprises FPGA configuration data Read Controller and FPGA configuration data writing controller, FPGA configuration data Read Controller receives the field programmable gate array reparation order that detects repair controller by local bus, read the field programmable gate array original configuration data that are stored in the nonvolatile memory by the NVRAM interface, field programmable gate array configuration data writing controller writes field programmable gate array original configuration data in the field programmable gate array by the FPGA monitor-interface, finishes the reparation to field programmable gate array.

5. the spaceborne processing platform with anti-single particle effect capability according to claim 1, it is characterized in that: described DSP monitoring module comprises DSP status information retaking of a year or grade controller and DSP condition identifier, the retaking of a year or grade controller is by the monitoring of DSP monitor-interface and receive the dsp operation status information, arbiter is differentiated the DSP state according to the dsp operation status information, when monitoring DSP " race is dead " or " race flies ", the order of generation DSP core reset sends to DSP and resets, and perhaps produces DSP and repairs request instruction to DSP to be repaired such as detection repair controllers.

6. the spaceborne processing platform with anti-single particle effect capability according to claim 1, it is characterized in that: described DSP repairs module and comprises DSP routine data Read Controller and DSP routine data writing controller, DSP routine data Read Controller receives the DSP that detects repair controller by internal data bus and repairs order, reads the DSP routine data that is stored in the nonvolatile memory by the NVRAM interface, DSP routine data writing controller writes the DSP routine data among the DSP by the DSP monitor-interface, finishes the reparation to DSP.

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