CN101551762B - Spaceborne processing platform resisting single event effect - Google Patents
Spaceborne processing platform resisting single event effect Download PDFInfo
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- CN101551762B CN101551762B CN2009100434226A CN200910043422A CN101551762B CN 101551762 B CN101551762 B CN 101551762B CN 2009100434226 A CN2009100434226 A CN 2009100434226A CN 200910043422 A CN200910043422 A CN 200910043422A CN 101551762 B CN101551762 B CN 101551762B
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Abstract
The invention discloses a spaceborne processing platform resisting single event effect, which comprises a high-reliability monitoring unit, a non-volatile memory, a field programmable logic gate arrayand more than one DSPs, the high-reliability monitoring unit and other parts are interconnected by a local bus, and the field programmable logic gate array and the DSPs are interconnected by a high-s peed bus; the high-reliability monitoring unit is used for detecting and repairing single event upset in the field programmable logic gate array and the DSPs. The invention is a spaceborne processing platform having simple structural principal, convenient operation, high reliability, good stability and the ability of resisting the single event effect.
Description
Technical field
The present invention is mainly concerned with space apparatus engineering field, refers in particular to a kind of spaceborne processing platform with anti-single particle effect capability.
Background technology
Be full of the various particles from immense universe in the cosmic space: proton, electronics, α particle, heavy ion, gamma-rays etc., the radiation effect that these particles cause, especially single particle effect affect the reliability of space electronic instrument.
In recent years, along with VLSI (very large scale integrated circuit) (VLSI, Very Large Scale Integrated circuits) development and the application of technology, field programmable gate array (FPGA, Field Programmable Gate Array) and digital signal processor (DSP, Digital Signal Processor), rely on its powerful signal handling capacity and superior interface capability to replace the conventional one-piece machine gradually, become the important component part of spaceborne high speed signal processing platform, beginning is applied in aerospace engineering.
Along with the raising of manufacturing process, the frequency of operation of VLSI is more and more higher, and operating voltage is more and more lower, and this makes spaceborne signal processing platform show stronger susceptibility to single particle effect, and faults such as single-particle inversion appear in FPGA, DSP etc. easily.VLSI such as FPGA, DSP relies on its complicated logical relation to finish various functions, between each transistor except annexation physically, by later stage logic function design, as the hardware capability description of FPGA or the program design of DSP, also in the connection and the sequential relationship that have produced the logic-based function each other.From application point, single particle effect to the influence of FPGA and DSP from the zone of of short duration, small size, single transistor by the logic function of sequential circuit, transmit or be coupled to bigger zone.As seen, increase, the reduction of core operational voltage and the increasing substantially of frequency of operation with density of reducing along with VLSI transistor technology characteristic dimension, spaceborne signal processing platform is subjected to the influence of single particle effect more and more serious, and the single particle effect fault proportion of space electronic instrument will further increase.
At present, in spaceborne signal processing platform, on the one hand be that high-performance, extensive, high-grade FPGA, DSP device price are expensive unusually; On the other hand, the reason that is limited to aspects such as manufacturing process and technology, low price FPGA such as general industry level or even army's grade, DSP device are owing to adopt SRAM (Static Random Access Memory) on the sheet in a large number, be subjected to the space high energy particle to influence the probability that single particle effect takes place and improve greatly, have a strong impact on FPGA and the operate as normal of DSP device in space environment.
Summary of the invention
The technical problem to be solved in the present invention just is: at the technical matters that prior art exists, the invention provides that a kind of structural principle is simple, easy and simple to handle, reliability is high, the spaceborne processing platform with anti-single particle effect capability of good stability.
For solving the problems of the technologies described above, the present invention by the following technical solutions.
A kind of spaceborne processing platform with anti-single particle effect capability, it is characterized in that: it comprises by highly reliable monitoring unit, nonvolatile memory, field programmable gate array and more than one DSP, highly reliable monitoring unit and other each several parts adopt local bus interconnected, adopt high-speed bus interconnected between field programmable gate array and the DSP; Described highly reliable monitoring unit is used for the single-particle inversion in field programmable gate array and the DSP is detected and repairs.
As a further improvement on the present invention:
Described highly reliable monitoring unit comprises that detection repair controller, DSP monitoring module, the DSP by bus interconnection repairs module, FPGA detection module, FPGA reparation module and DSP monitor-interface, FPGA monitor-interface and NVRAM interface.
Described detection repair controller is used to monitor and receive the device that DSP monitoring module and FPGA detection module send and repairs request instruction, and repairs module and FPGA to DSP and repair module and send device reparation order.
Described FPGA detection module comprises FPGA configuration data Read Controller, FPGA configuration data retaking of a year or grade controller and FPGA configuration data detect controller, described FPGA configuration data Read Controller reads FPGA original configuration data by the NVRAM interface from nonvolatile memory, FPGA configuration data retaking of a year or grade controller is by the operation configuration data of FPGA monitor-interface retaking of a year or grade FPGA, the FPGA configuration data detects controller original configuration data and operation configuration data is compared, when the generation comparison does not match, send FPGA reparation request instruction to detecting repair controller by internal data bus.
Described FPGA repairs module and comprises FPGA configuration data Read Controller and FPGA configuration data writing controller, FPGA configuration data Read Controller receives the FPGA that detects repair controller by local bus and repairs order, reads the FPGA original configuration data that are stored in the nonvolatile memory by the NVRAM interface, FPGA configuration data writing controller writes FPGA original configuration data among the FPGA by the FPGA monitor-interface, finishes the reparation to FPGA.
Described DSP monitoring module comprises DSP status information retaking of a year or grade controller and DSP condition identifier, the retaking of a year or grade controller is by the monitoring of DSP monitor-interface and receive the dsp operation status information, arbiter is differentiated the DSP state according to the dsp operation status information, when monitoring DSP " race is dead " or " race flies ", the order of generation DSP core reset sends to DSP and resets, and perhaps produces DSP and repairs request instruction to DSP to be repaired such as detection repair controllers.
Described DSP repairs module and comprises DSP routine data Read Controller and DSP routine data writing controller, DSP routine data Read Controller receives the DSP that detects repair controller by internal data bus and repairs order, reads the DSP routine data that is stored in the nonvolatile memory by the NVRAM interface, DSP routine data writing controller writes the DSP routine data among the DSP by the DSP monitor-interface, finishes the reparation to DSP.
Compared with prior art, advantage of the present invention just is:
1. the present invention adopts the interconnect architecture of " FPGA adds DSP ", has improved extendability and the handling property and the computing power of platform greatly;
2. the present invention is provided with highly reliable monitoring unit, be used to finish FPGA and DSP single-particle inversion are detected and repair, reduced of the requirement of spaceborne processing platform, thereby can reduce cost greatly with inferior grade FPGA and DSP device application in the space apparatus engineering to FPGA and DSP device grade;
3. FPGA config memory retaking of a year or grade flow process of the present invention adopts specific time sequence and is that unit carries out the retaking of a year or grade of FPGA config memory with the separate configurations frame, does not disturb the operation of FPGA normal logic function;
4. FPGA config memory of the present invention is repaired flow process, adopts specific time sequence and is that unit is repaired FPGA config memory error configurations frame with the separate configurations frame, does not disturb the normal operation of other logic functions of FPGA;
5. the highly reliable monitoring unit of the present invention is an integrated circuit, realizes on monolithic FPGA, and is simple in structure, degree of modularity height.
Description of drawings
Fig. 1 is the structural representation of the spaceborne processing platform of the present invention;
Fig. 2 is the structural representation of the highly reliable monitoring unit of the present invention;
Fig. 3 is the structural representation of FPGA detection module of the present invention;
Fig. 4 is the structural representation that FPGA of the present invention repairs module;
Fig. 5 is the structural representation of DSP monitoring module of the present invention;
Fig. 6 is the structural representation that DSP of the present invention repairs module;
Fig. 7 is that FPGA of the present invention detects the reparation process flow diagram;
Fig. 8 is a FPGA config memory retaking of a year or grade process flow diagram of the present invention;
Fig. 9 is that FPGA config memory of the present invention is repaired process flow diagram;
Figure 10 is that DSP of the present invention detects the reparation process flow diagram.
Embodiment
Below with reference to specific embodiment and Figure of description the present invention is described in further details.
As shown in Figure 1, a kind of spaceborne processing platform of the present invention with anti-single particle effect capability, it is made up of highly reliable monitoring unit, nonvolatile memory, DSP and FPGA; Highly reliable monitoring unit is connected by standard interface with nonvolatile memory, DSP and FPGA respectively, adopts high speed data bus interconnected between FPGA and each DSP;
As shown in Figure 2, highly reliable monitoring unit is realized by the ActelFPGA design of the anti-fuse once programming of high-grade anti-irradiation device in the present embodiment, comprise and detect repair controller, FPGA detection module, FPGA reparation module, DSP monitoring module, DSP reparation module and FPGA monitor-interface, DSP monitor-interface and NVRAM interface, interconnected between each module and the interface by local bus; The detection repair controller is logic processor in the highly reliable monitoring unit, and the reparation request instruction that monitoring and reception FPGA monitoring module and DSP detection module send sends the reparation order to FPGA reparation module and DSP reparation module; The FPGA detection module compares to FPGA original configuration data and operation configuration data, detects single-particle inversion, and sends FPGA reparation request instruction by local bus to detecting repair controller; FPGA repairs module and receives from the FPGA that detects repair controller by local bus and repair order, read the FPGA original configuration data that are stored in the nonvolatile memory and by the FPGA monitor-interface FPGA original configuration data are write among the FPGA by the NVRAM interface, finishes the reparation to FPGA; The DSP monitoring module regularly reports running state information by DSP monitor-interface reception DSP and it is differentiated, when monitoring DSP " race is dead " or " race flies ", the order of generation DSP core reset sends to DSP and resets, and perhaps produces DSP and repairs request instruction to DSP to be repaired such as detection repair controllers; DSP repairs module and receives from the DSP that detects repair controller by local bus and repair order, read the DSP routine data that is stored in the nonvolatile memory and by the DSP monitor-interface DSP routine data is write among the DSP by the NVRAM interface, finishes the reparation to DSP; FPGA monitor-interface, DSP monitor-interface and NVRAM interface are realized the data transmission between inner each correlation module of highly reliable monitoring unit and FPGA, DSP and the nonvolatile memory.
As shown in Figure 3, the FPGA detection module is a logic processor in the highly reliable monitoring unit in the present embodiment, form by FPGA configuration data Read Controller, FPGA configuration data retaking of a year or grade controller and FPGA configuration data detecting device, Read Controller is connected with nonvolatile memory by the NVRAM interface, the retaking of a year or grade controller is connected with the FPGA device by standard FPGA monitor-interface, detecting device is connected with the detection repair controller by local bus, and is interconnected by local bus between Read Controller, retaking of a year or grade controller and the detecting device; FPGA configuration data Read Controller reads the FPGA original configuration data that are stored in the nonvolatile memory, FPGA configuration data retaking of a year or grade controller is by FPGA monitor-interface retaking of a year or grade FPGA operation configuration data, FPGA configuration data detecting device carries out byte-by-byte compare of analysis to original configuration data and operation configuration data, when the generation comparison does not match, send FPGA reparation request instruction to detecting repair controller.
As shown in Figure 4, FPGA reparation module is a logic processor in the highly reliable monitoring unit in the present embodiment, form by FPGA configuration data Read Controller and FPGA configuration data writing controller, Read Controller is connected with the detection repair controller by internal data bus, writing controller is connected with the FPGA device by standard FPGA monitor-interface, and is interconnected by internal data bus between Read Controller and the writing controller; Read Controller receives from the FPGA that detects repair controller and repairs order, reads the FPGA original configuration data that are stored in the nonvolatile memory; FPGA configuration data writing controller writes FPGA original configuration data among the FPGA, finishes FPGA and repairs.
As shown in Figure 5, the DSP monitoring module is a logic processor in the highly reliable monitoring unit in the present embodiment, form by DSP status information retaking of a year or grade controller and DSP condition identifier, the retaking of a year or grade controller is connected with the DSP device by standard DSP monitor-interface, arbiter is connected with the detection repair controller by local bus, is undertaken interconnected by local bus between retaking of a year or grade controller and the arbiter; The retaking of a year or grade controller is by the monitoring of DSP monitor-interface and receive the dsp operation status information; Arbiter is differentiated the DSP state according to the dsp operation status information, when monitoring DSP " race is dead " or " race flies ", the order of generation DSP core reset sends to DSP and resets, and perhaps produces DSP and repairs request instruction to DSP to be repaired such as detection repair controllers.
As shown in Figure 6, DSP reparation module is a logic processor in the highly reliable monitoring unit in the present embodiment, form by DSP routine data Read Controller and DSP routine data writing controller, Read Controller is connected with nonvolatile memory by the NVRAM interface, writing controller is connected with the DSP device by the DSP monitor-interface, is undertaken interconnected by local bus between Read Controller and the writing controller; Read Controller receives the DSP that detects repair controller and repairs order, reads the DSP routine data that is stored in the nonvolatile memory, and writing controller writes the DSP routine data among the DSP, finishes the reparation to DSP.
As shown in Figure 7, in the present embodiment, the step that the FPGA that the present invention adopts detects the restorative procedure specific embodiment is:
1. carry out FPGA config memory retaking of a year or grade flow process by standard FPGA monitor-interface and obtain FPGA configuration data information;
2. from nonvolatile memory, read FPGA original configuration data by the NVRAM interface;
3. 1. step is compared with the FPGA configuration data that 2. step obtains, do not match, then think and carry out step 4. by the generation single-particle inversion, otherwise carry out step 1. if find comparison;
4. by the configuration data in the standard FPGA monitor-interface execution FPGA config memory reparation flow process reparation FPGA config memory, carry out step 1..
As shown in Figure 8, in the present embodiment, the FPGA config memory retaking of a year or grade flow process that the present invention adopts, its step and command word and function are:
1. send synch command word (AA-99-55-66) by standard FPGA monitor-interface to FPGA, start the retaking of a year or grade of FPGA config memory; 2. pass through standard FPGA monitor-interface to FPGA sending device id command word (30-00-C0-01), write device ID number to the IDCODE of FPGA register; 3. send cyclic check reset command word (00-00-00-07), the reset cycle check (CRC) computational logic of FPGA by standard FPGA monitor-interface to FPGA; 4. send start frame address command word (30-00-20-01) by standard FPGA monitor-interface to FPGA, the start address of retaking of a year or grade configuration frame is set; 5. send retaking of a year or grade config memory command word (00-00-00-04) by standard FPGA monitor-interface to FPGA, sign is prepared the config memory data of retaking of a year or grade FPGA; 6. send configuration frame length command word (28-00-60-00) by standard FPGA monitor-interface to FPGA, the length of retaking of a year or grade configuration frame is set; 7. dispose frame data by standard FPGA monitor-interface from one of FPGA retaking of a year or grade, return FPGA configuration frame data from FPGA; 8. send cancellation synchronous regime command word (00-00-00-0D) by standard FPGA monitor-interface to FPGA, finish the retaking of a year or grade of FPGA config memory.
As shown in Figure 9, in the present embodiment, the step that the FPGA config memory that the present invention adopts is repaired the flow process specific embodiment is:
1. send synch command word (AA-99-55-66) by standard FPGA monitor-interface to FPGA, start the FPGA config memory and write; 2. send cyclic check logic reset command word (00-00-00-07), the cyclic check CRC computational logic of the FPGA that resets by standard FPGA monitor-interface to FPGA; 3. pass through standard FPGA monitor-interface to FPGA sending device id command word (30-01-C0-01), write device ID number to the IDCODE of FPGA register; 4. send configuration frame length command word (30-01-60-01) by standard FPGA monitor-interface to FPGA, the length that writes the configuration frame is set; 5. send to FPGA by standard FPGA monitor-interface and prepare write data command word (00-00-00-01), sign prepares to write the config memory data of FPGA; 6. send configuration frame address command word (30-00-20-01) by standard FPGA monitor-interface to FPGA, the start address that writes the configuration frame is set; 7. send configuration frame data by standard FPGA monitor-interface to FPGA, write configuration frame data, totally 52 words to FPGA; 8. send cancellation synchronous regime command word (00-00-00-0D) by standard FPGA monitor-interface to FPGA, finish the FPGA config memory and write.
As shown in figure 10, in the present embodiment, the step that the DSP that the present invention adopts detects the restorative procedure specific embodiment is:
1. obtain the dsp operation status information by the retaking of a year or grade of standard DSP monitor-interface;
2. differentiating the DSP status information, is that the DSP program circuit is unusual if differentiate, and carries out step 3., is DSP internal memory generation single-particle inversion if differentiate, and carries out step 5., otherwise proceeds step 1.;
3. the DSP kernel that resets is waited for the DSP program designation, if 4. the success of DSP program designation is carried out step, otherwise proceeded step 5.;
4. activate DSP, carry out step 1.;
5. from nonvolatile memory, read the DSP routine data by the NVRAM interface, the DSP routine data is write in the DSP device, carry out step 1. by standard DSP monitor-interface.
The above only is a preferred implementation of the present invention, and protection scope of the present invention also not only is confined to the foregoing description, and all technical schemes that belongs under the thinking of the present invention all belong to protection scope of the present invention.Should be pointed out that for those skilled in the art in the some improvements and modifications that do not break away under the principle of the invention prerequisite, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. spaceborne processing platform with anti-single particle effect capability, it is characterized in that: it comprises by highly reliable monitoring unit, nonvolatile memory, field programmable gate array and more than one DSP, highly reliable monitoring unit and other each several parts adopt local bus interconnected, adopt high-speed bus interconnected between field programmable gate array and the DSP; Described highly reliable monitoring unit is used for the single-particle inversion in field programmable gate array and the DSP is detected and repairs, described highly reliable monitoring unit comprises the detection repair controller by bus interconnection, the DSP monitoring module, DSP repairs module, the FPGA detection module, FPGA repairs module and DSP monitor-interface, FPGA monitor-interface and NVRAM interface, described detection repair controller is direct and DSP monitoring module by bus, DSP repairs module, the FPGA detection module, FPGA repairs module and is connected with the NVRAM interface, the DSP monitor-interface is repaired module with the DSP monitoring module with DSP by bus and is connected, and the FPGA monitor-interface is repaired module with the FPGA detection module with FPGA by bus and is connected; Described FPGA detection module is realized the FPGA single-particle inversion is detected by the FPGA monitor-interface; Described FPGA repairs module and by the FPGA monitor-interface FPGA single-particle inversion is repaired; Described DSP detection module is realized the DSP single-particle inversion is detected by the DSP monitor-interface; Described DSP repairs module and by the DSP monitor-interface DSP single-particle inversion is repaired.
2. the spaceborne processing platform with anti-single particle effect capability according to claim 1, it is characterized in that: described detection repair controller is used to monitor and receive the device that DSP monitoring module and FPGA detection module send and repairs request instruction, and repairs module and FPGA to DSP and repair module and send device reparation order.
3. the spaceborne processing platform with anti-single particle effect capability according to claim 1, it is characterized in that: described FPGA detection module comprises FPGA configuration data Read Controller, FPGA configuration data retaking of a year or grade controller and FPGA configuration data detect controller, described FPGA configuration data Read Controller reads field programmable gate array original configuration data by the NVRAM interface from nonvolatile memory, FPGA configuration data retaking of a year or grade controller is by the operation configuration data of FPGA monitor-interface retaking of a year or grade field programmable gate array, the FPGA configuration data detects controller original configuration data and operation configuration data is compared, when the generation comparison does not match, send field programmable gate array reparation request instruction to detecting repair controller by internal data bus.
4. the spaceborne processing platform with anti-single particle effect capability according to claim 1, it is characterized in that: described FPGA repairs module and comprises FPGA configuration data Read Controller and FPGA configuration data writing controller, FPGA configuration data Read Controller receives the field programmable gate array reparation order that detects repair controller by local bus, read the field programmable gate array original configuration data that are stored in the nonvolatile memory by the NVRAM interface, field programmable gate array configuration data writing controller writes field programmable gate array original configuration data in the field programmable gate array by the FPGA monitor-interface, finishes the reparation to field programmable gate array.
5. the spaceborne processing platform with anti-single particle effect capability according to claim 1, it is characterized in that: described DSP monitoring module comprises DSP status information retaking of a year or grade controller and DSP condition identifier, the retaking of a year or grade controller is by the monitoring of DSP monitor-interface and receive the dsp operation status information, arbiter is differentiated the DSP state according to the dsp operation status information, when monitoring DSP " race is dead " or " race flies ", the order of generation DSP core reset sends to DSP and resets, and perhaps produces DSP and repairs request instruction to DSP to be repaired such as detection repair controllers.
6. the spaceborne processing platform with anti-single particle effect capability according to claim 1, it is characterized in that: described DSP repairs module and comprises DSP routine data Read Controller and DSP routine data writing controller, DSP routine data Read Controller receives the DSP that detects repair controller by internal data bus and repairs order, reads the DSP routine data that is stored in the nonvolatile memory by the NVRAM interface, DSP routine data writing controller writes the DSP routine data among the DSP by the DSP monitor-interface, finishes the reparation to DSP.
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| CN2009100434226A CN101551762B (en) | 2009-05-15 | 2009-05-15 | Spaceborne processing platform resisting single event effect |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101976212B (en) * | 2010-10-27 | 2012-01-25 | 西安空间无线电技术研究所 | Small amount code reloading-based DSP anti-single particle error correction method |
| CN102043754A (en) * | 2010-12-30 | 2011-05-04 | 浙江大学 | Method for improving satellite borne DSP (Digital Signal Processing) loading guiding reliability |
| CN103064810B (en) * | 2011-10-18 | 2016-05-25 | 上海航天控制工程研究所 | A kind of method that realizes satellite serial communication |
| CN104092629A (en) * | 2014-07-08 | 2014-10-08 | 中国航空无线电电子研究所 | AFDX switch for resisting single event upset |
| CN104133738B (en) * | 2014-07-11 | 2017-04-12 | 中国人民解放军信息工程大学 | SEU-resistant method for satellite-borne MIMO detector based on SEC-DED |
| CN104281742A (en) * | 2014-09-11 | 2015-01-14 | 上海卫星工程研究所 | SRAM (static random access memory) type large-scale FPGA (field programmable gate array) anti-single-particle device and method |
| CN105045335A (en) * | 2015-06-23 | 2015-11-11 | 上海航天测控通信研究所 | FPGA information processing system with embedded 8051IP core |
| CN105068969B (en) * | 2015-07-17 | 2018-02-09 | 西安空间无线电技术研究所 | Single particle effect guard system and method for digital signal processing platform framework |
| CN108766491B (en) * | 2018-06-01 | 2019-05-31 | 北京理工大学 | A kind of track loop single-particle inversion errors repair method in SRAM type FPGA piece |
| CN109213632B (en) * | 2018-08-23 | 2022-06-17 | 湖南斯北图科技有限公司 | Spaceborne electronic system with anti-radiation reinforcement design and reinforcement method |
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