CN108735725A - A kind of semiconductor devices and its manufacturing method and electronic device - Google Patents
A kind of semiconductor devices and its manufacturing method and electronic device Download PDFInfo
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- CN108735725A CN108735725A CN201710253829.6A CN201710253829A CN108735725A CN 108735725 A CN108735725 A CN 108735725A CN 201710253829 A CN201710253829 A CN 201710253829A CN 108735725 A CN108735725 A CN 108735725A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 105
- 229910052751 metal Inorganic materials 0.000 claims abstract description 102
- 239000002184 metal Substances 0.000 claims abstract description 102
- 235000012431 wafers Nutrition 0.000 claims description 175
- 239000010410 layer Substances 0.000 claims description 130
- 238000000034 method Methods 0.000 claims description 59
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 26
- 239000010949 copper Substances 0.000 claims description 26
- 229910052802 copper Inorganic materials 0.000 claims description 25
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 9
- 238000002360 preparation method Methods 0.000 claims description 8
- 238000011049 filling Methods 0.000 claims description 7
- 238000003780 insertion Methods 0.000 claims description 6
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- 238000012856 packing Methods 0.000 claims description 6
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- 230000005494 condensation Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
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- 238000005516 engineering process Methods 0.000 abstract description 12
- 238000013467 fragmentation Methods 0.000 abstract description 9
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- 238000005240 physical vapour deposition Methods 0.000 description 13
- 239000012212 insulator Substances 0.000 description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000011469 building brick Substances 0.000 description 2
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- 238000000407 epitaxy Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
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- 238000000059 patterning Methods 0.000 description 2
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- 238000010992 reflux Methods 0.000 description 2
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- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
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- 239000002305 electric material Substances 0.000 description 1
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- 238000002513 implantation Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a kind of semiconductor devices and its manufacturing method and electronic devices.The semiconductor devices includes：First wafer is formed with engagement groove in first wafer, and layer of bonding material is formed on the surface of the engagement groove；Second wafer is formed with metal column on second wafer, wherein the metal column is embedded and fills the engagement groove.Metal column by the way that Embedded riveting column type is arranged can prevent the second wafer fragmentation, and circuit will not be made to disconnect after high-temperature technology and prolonged pressure, and the performance and yield to make device improve.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method and electronics
Device.
Background technology
In consumer electronics field, multifunctional equipment is increasingly liked by consumer, compared to the simple equipment of function,
Multifunctional equipment manufacturing process will be more complicated, for example need to integrate the chip of multiple and different functions in circuit version, thus go out
3D integrated circuits (integrated circuit, IC) technology, 3D integrated circuits (integrated circuit, IC) quilt are showed
It is defined as a kind of system-level integrated morphology, multiple chips are stacked in vertical plane direction, to save space, each chip
Marginal portion can draw multiple pins as needed, utilize these pins as needed, it would be desirable to which the chip of interconnection is logical
Metal wire interconnection is crossed, but aforesaid way still has many deficiencies, for example stacked chips quantity is more, and between chip
Connection relation is more complicated, then just may require that final wire laying mode is more chaotic, and can lead using a plurality of metal wire
Volume is caused to increase.
Copper post is used widely in flipchip mounting processes (flip chip assembly process) at present.
But include more pressure relative to solder-bump in the preparation process of copper post, this can lead to wafer fragmentation, and
And circuit can be made to disconnect after high-temperature technology and prolonged pressure, to make the reduced performance of device, or even failure.
Therefore, be the above-mentioned technical problem solved in current technique, it is necessary to propose a kind of new semiconductor devices and its
Manufacturing method and electronic device.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are the present invention provides a kind of semiconductor devices, the semiconductor devices includes：
First wafer is formed with engagement groove in first wafer, is formed with and connects on the surface of the engagement groove
Condensation material layer；
Second wafer is formed with metal column on second wafer, wherein being connect described in metal column insertion and filling
Close groove.
Optionally, the metal column of the package in the engagement groove is additionally provided in the layer of bonding material
The weld material layer on surface.
Optionally, the metal column is partially embedded into the engagement groove, is positioned partially at the level of second wafer
It is more than surface.
Optionally, filling first wafer and described the are formed between first wafer and second wafer
The packing material in gap between two wafers.
Optionally, the metal column includes copper post.
Optionally, first wafer is support wafer, and second wafer is device wafers.
The present invention also provides a kind of preparation method of semiconductor devices, the method includes：
First wafer is provided, engagement groove is formed in first wafer, is formed on the surface of the engagement groove
There is layer of bonding material；
Second wafer is provided, metal column is formed on second wafer, described in metal column insertion and filling
Groove is engaged, so that first wafer and second wafer engage.
Optionally, the method that first wafer and second wafer engage is made to include：
The metal column is embedded in the engagement groove；
Reflow step is executed, so that the metal column melts and is filled up completely the engagement groove.
Optionally, it is also formed on the surface of the metal column and covers the weld material layer of the layer of bonding material, in institute
State the surface of the metal column of the package of weld material layer described in reflow step in the engagement groove.
Optionally, after engaging first wafer and second wafer, the method still further comprises
The step of gap between first wafer and second wafer being filled using packing material.
Optionally, the step of formation engagement groove includes：
First wafer is provided, the first metal layer is formed on first wafer；
The first metal layer and first wafer are patterned, to form several engagement grooves；
On the first metal layer and the surface of the engagement groove forms the layer of bonding material；
The T-shaped sacrificial material layer of shape in the engagement groove；
The layer of bonding material and described first of first crystal column surface is removed using the sacrificial material layer as mask
Metal layer；
The sacrificial layer is removed, to form the engagement groove.
Optionally, it is formed after the engagement groove, the method further includes：
Protective layer is formed, to cover first wafer；
The protective layer is patterned, to form opening and expose the engagement groove.
Optionally, the method for forming the sacrificial material layer of the T shapes includes：
Form the coating for covering the layer of bonding material；
The coating is patterned, to form the patterns of openings that opening size is more than the engagement groove；
Sacrificial layer is selected to fill the engagement groove and the patterns of openings.
Optionally, the metal column includes copper post.
Optionally, first wafer is support wafer, and second wafer is device wafers.
The present invention also provides a kind of electronic devices, including above-mentioned semiconductor devices.
The second wafer fragmentation is caused in order to solve the problems, such as that pressure is excessive in the present invention, provides a kind of semiconductor devices
And preparation method thereof, it is formed with engagement groove in first wafer in the semiconductor devices, in the engagement groove
Surface be formed with layer of bonding material；It is formed with metal column on second wafer, wherein the metal column is embedded and fills
The engagement groove.Metal column by the way that Embedded riveting column type is arranged can prevent the second wafer fragmentation, and pass through
Circuit will not be made to disconnect after high-temperature technology and prolonged pressure, the performance and yield to make device improve.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is a kind of schematic flow chart of the manufacturing method of semiconductor devices of an alternative embodiment of the invention；
Fig. 2A-Fig. 2 D are that a kind of correlation step of the manufacturing method of semiconductor devices in one embodiment of the invention is formed
Structure sectional view；
Fig. 3 A- Fig. 3 J are the phase of the manufacturing method of the first wafer in a kind of semiconductor devices in one embodiment of the invention
Close the sectional view for the structure that step is formed；
Fig. 4 shows the schematic diagram of electronic device according to an embodiment of the present invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but include due to for example manufacturing caused shape
Shape deviation.For example, be shown as the injection region of rectangle its edge usually there is circle or bending features and/or implantation concentration ladder
Degree, rather than the binary from injection region to non-injection regions changes.Equally, the disposal area can be led to by injecting the disposal area formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiment.
The manufacturing method of semiconductor devices described in technique includes the following steps at present：The first wafer is provided, described
Layer of bonding material is formed on one wafer, the layer of bonding material is convex, then provides the second wafer, second wafer
On be formed with metal column, the metal column and the layer of bonding material are engaged, then filling first wafer and institute
State the gap between the second wafer.
The method since the height of copper post is larger, but simultaneously with the contact area very little of the second wafer, therefore molten
It needs to apply larger pressure during melting pushing, this can lead to the second wafer fragmentation, and pass through high-temperature technology and length
Circuit can be made to disconnect after the pressure of time, to make the reduced performance of device, or even failure.
For this purpose, to solve the above-mentioned problems, this application provides a kind of preparation method of semiconductor devices, the method packets
It includes：
First wafer is provided, engagement groove is formed in first wafer, is formed on the surface of the engagement groove
There is layer of bonding material；
Second wafer is provided, metal column is formed on second wafer, described in metal column insertion and filling
Groove, so that first wafer and second wafer engage.
Wherein, the method that first wafer and second wafer engage is made to include：
The metal column is embedded in the engagement groove；
Reflow step is executed, so that the metal column melts and is filled up completely the engagement groove.
In addition, the present invention also provides a kind of semiconductor devices, the semiconductor devices includes：
First wafer is formed with engagement groove in first wafer, is formed with and connects on the surface of the engagement groove
Condensation material layer；
Second wafer is formed with metal column on second wafer, wherein being connect described in metal column insertion and filling
Close groove.
The present invention is formed with engagement groove in first wafer, and engagement material is formed on the surface of the engagement groove
The bed of material；Second wafer is formed with metal column on second wafer, wherein the metal column is embedded and to fill the engagement recessed
Slot.Metal column by the way that Embedded riveting column type is arranged can prevent the second wafer fragmentation, and by high-temperature technology and
Circuit will not be made to disconnect after prolonged pressure, the performance and yield to make device improve.
In addition, compared to conventional solder-bump (solder bump), copper post may be implemented to be electrically connected, can also be the
Support is realized between one wafer and the second wafer, and there is better electric property and hot property.
Embodiment one
In order to solve this problem, the present invention provides a kind of semiconductor devices, and 2D is to the semiconductor below in conjunction with the accompanying drawings
Device is described further.
Wherein, the semiconductor devices includes：
First wafer 201 is formed with engagement groove in first wafer, is formed on the surface of the engagement groove
Layer of bonding material 202；
Second wafer 101 is formed with metal column 102 on second wafer, wherein the metal column is embedded and fills
The engagement groove.
Specifically, the first wafer 201 can be following at least one of the material being previously mentioned：Silicon, silicon-on-insulator
(SOI), silicon (SSOI), stacking SiGe (S-SiGeOI), germanium on insulator SiClx on insulator are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
Wherein, the technique is flipchip mounting processes (flip chip assembly in this application
Process), therefore first wafer is support wafer or substrate.
But various logic device is equally could be formed in first wafer, such as it is formed with various cmos devices
And passive device etc..
Wherein, unlike current technique, the metal column that is formed is riveting column in the present invention, i.e., riveting is embedded in described the
In one wafer, therefore it is formed in first wafer engagement groove for the embedding metal column of riveting.
Wherein, the surface of the engagement groove is also formed with layer of bonding material 202, and the layer of bonding material 202 is used for
It is engaged in subsequent technique.
The layer of bonding material 202 selects metal material, wherein the layer of bonding material 202 is copper, aluminium, cobalt (Co), molybdenum
(Mo), titanium nitride (TiN) and the conductive material or combinations thereof containing tungsten.
Layer of bonding material 202 is copper in this embodiment.
Wherein, second wafer 101 is logic wafer, and various logic device, example are formed in second wafer 101
Such as it is formed with various cmos devices and passive device.
As an example, the first functional component, such as transistor, interconnection structure can also be formed in the second wafer 101
And radio-frequency devices.
Wherein, transistor can be normal transistor, high-k/metal gate transistors, fin transistor or other are suitable
Transistor.Interconnection structure may include metal layer (such as layers of copper or aluminium layer), metal plug etc..Radio-frequency devices may include inductance
(inductor) devices such as.
In addition to including transistor, radio-frequency devices and interconnection structure, cmos device can also include other various feasible groups
Part, such as resistance, capacitance, MEMS device etc., are not defined herein.
Wherein, the concrete structure and forming method of the various components in cmos device, those skilled in the art can roots
It is selected with reference to the prior art according to actual needs, details are not described herein again.
Optionally, it is also formed with weld material layer 103 on the surface of the metal column, wherein the weld material layer 103
Tin can be selected, but is not limited to the material, details are not described herein.
Wherein, the metal column is embedded in the engagement groove, i.e., the metal column and weld material layer 103 is inserted into institute
It states in engagement groove, as shown in Figure 2 D, so that the weld material layer 103 is in direct contact with the layer of bonding material.
The metal column through reflux, melt and be filled up completely the engagement groove, also formed on the surface of the metal column
There is weld material layer 103, the weld material layer described in reflow step covers the layer of bonding material and wraps up and connect embedded in described
Close the surface of the metal column in groove.
This is provided with packing material between first wafer and second wafer, to fill first wafer and institute
State the gap between the second wafer.
It is formed with engagement groove in first wafer in the semiconductor devices in the present invention, it is recessed in the engagement
The surface of slot is formed with layer of bonding material；Second wafer is formed with metal column on second wafer, wherein the metal column
It is embedded in and fills the engagement groove.Metal column by the way that Embedded riveting column type is arranged can prevent the second wafer fragmentation,
And circuit will not be made to disconnect after high-temperature technology and prolonged pressure, the performance and yield to make device carry
It is high.
In addition, compared to conventional solder-bump (solder bump), copper post may be implemented to be electrically connected, can also be the
Support is realized between one wafer and the second wafer, and there is better electric property and hot property.
Embodiment two
In the following, the one exemplary side of manufacturing method for the semiconductor devices that embodiment proposes with reference to the accompanying drawings to describe the present invention
The detailed step of method.Fig. 1 is a kind of schematic flow of the manufacturing method of semiconductor devices of an alternative embodiment of the invention
Figure；Fig. 2A-Fig. 2 D are the knot that a kind of correlation step of the manufacturing method of semiconductor devices in one embodiment of the invention is formed
The sectional view of structure；Fig. 3 A- Fig. 3 J are the manufacturing method of the first wafer in a kind of semiconductor devices in one embodiment of the invention
Correlation step formed structure sectional view.
Wherein, Fig. 1 is a kind of schematic flow of the manufacturing method of semiconductor devices of an alternative embodiment of the invention
Scheme, includes specifically：
Step S1：First wafer is provided, engagement groove is formed in first wafer, in the table of the engagement groove
Face is formed with layer of bonding material；
Step S2：Second wafer is provided, metal column is formed on second wafer, by metal column insertion and is filled out
The engagement groove is filled, so that first wafer and second wafer engage.
The manufacturing method of the semiconductor devices of the present embodiment, specifically comprises the following steps：
It executes step 1 and provides the first wafer 201 as shown in Figure 2 a, engagement groove is formed in first wafer,
It is formed with layer of bonding material 202 on the surface of the engagement groove.
Specifically, the first wafer 201 can be following at least one of the material being previously mentioned：Silicon, silicon-on-insulator
(SOI), silicon (SSOI), stacking SiGe (S-SiGeOI), germanium on insulator SiClx on insulator are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
Wherein, the technique is flipchip mounting processes (flip chip assembly in this application
Process), therefore first wafer is support wafer or substrate.
But various logic device is equally could be formed in first wafer, such as it is formed with various cmos devices
And passive device etc..
Wherein, unlike current technique, the metal column that is formed is riveting column in the present invention, i.e., riveting is embedded in described the
In one wafer, therefore it is formed in first wafer engagement groove for the embedding metal column of riveting.
Wherein, the surface of the engagement groove is also formed with layer of bonding material 202, and the layer of bonding material 202 is used for
It is engaged in subsequent technique.
The layer of bonding material 202 selects metal material, wherein the layer of bonding material 202 is copper, aluminium, cobalt (Co), molybdenum
(Mo), titanium nitride (TiN) and the conductive material or combinations thereof containing tungsten.
Layer of bonding material 202 is copper in this embodiment.
Wherein, the preparation method of first wafer includes but not limited to following steps, below in conjunction with the accompanying drawings 3A- Fig. 3 J couple
The preparation method of first wafer is described further.
Step A1：First wafer is provided, the first metal layer is formed on first wafer；
Step A2：The first metal layer and first wafer are patterned, to form several engagement grooves；
Step A3：On the first metal layer and the surface of the engagement groove forms the layer of bonding material；
Step A4：Form the coating for covering the layer of bonding material；
Step A5：The coating is patterned, to form the patterns of openings that opening size is more than the engagement groove；
Step A6：Sacrificial layer is selected to fill the engagement groove and the patterns of openings, with the T-shaped expendable material of shape
Layer；
Step A7：The layer of bonding material and the institute of first crystal column surface are removed using the sacrificial material layer as mask
State the first metal layer；
Step A8：The sacrificial layer is removed, to form the engagement groove.
Step A9：Protective layer is formed, to cover first wafer；
Step A10：The protective layer is patterned, to form opening and expose the engagement groove.
In the step A1, as shown in Figure 3a, the first wafer 201 is provided, first is formed on first wafer
Metal layer 204.
Wherein, the deposition method of the first metal layer 204 can be heavy for chemical vapor deposition (CVD) method, physical vapor
The low-pressure chemical vapor deposition (LPCVD) of the product formation such as (PVD) method or atomic layer deposition (ALD) method, laser ablation deposition (LAD)
And one kind in selective epitaxy growth (SEG), preferably physical vapour deposition (PVD) (PVD) method in the present invention.
Wherein, the first metal layer 204 is copper, aluminium, cobalt (Co), molybdenum (Mo), titanium nitride (TiN) and leading containing tungsten
Electric material or combinations thereof.
The first metal layer 204 is copper in this embodiment.
In the step A2, as shown in Figure 3B, the mode of digital control hole drilling or laser drill can be selected to be formed described
Engage groove.
The method that etching can certainly be selected forms the engagement groove, no longer limits herein, can as needed into
Row selection.
Wherein, the number of the engagement groove is also not limited to a certain numberical range.Equally, the engagement slot opening
Size does not also limit.
In the step A3, as shown in Figure 3c, formed with the surface of the engagement groove on the first metal layer
The layer of bonding material 202, wherein the deposition method of the layer of bonding material 202 can be chemical vapor deposition (CVD) method,
Low-pressure chemical vapor deposition (LPCVD), the laser of the formation such as physical vapour deposition (PVD) (PVD) method or atomic layer deposition (ALD) method are burnt
One kind in erosion deposition (LAD) and selective epitaxy growth (SEG), in the present invention preferably physical vapour deposition (PVD) (PVD) method.
In addition, layer of bonding material 202 can also select electric plating method to be formed, such as when the selection copper of layer of bonding material 202,
Copper coating is selected to form the layer of bonding material 202.
Specifically, in this step first it is described engagement groove in deposited metal copper seed layer, the seed layer
Deposition method can select chemical vapor deposition (CVD) method, physical vapour deposition (PVD) (PVD) method or atomic layer deposition (ALD) method etc..
Then the method for Cu electroplating (ECP) is selected to form the metallic copper, preferably, can also make in plating
With additive, the additive is flat dose (LEVELER), accelerator (ACCELERATORE) and inhibitor
(SUPPRESSOR)。
Preferably, the step of can also further include annealing after forming the metallic copper and being formed, annealing can be
It is carried out 2-4 hours at 80-160 DEG C, to promote copper to recrystallize, long big crystal grain reduces resistance and improves stability.
In the step A4, as shown in Figure 3d, coating 205 is formed by the method for press mold in this step, wherein
The layer of bonding material 202 and the engagement groove is completely covered in the coating 205, but and is not filled with the engagement groove.
Wherein, the coating can select the materials such as conventional copper foil, not limit further herein.
In the step A5, as shown in Figure 3 e, the coating is exposed, to form patterns of openings, wherein institute
The opening size for stating patterns of openings is more than the opening size of the engagement groove.
In one embodiment of this invention, the size of the patterns of openings is equal to the opening size for engaging groove and connects
2 times of sum of 202 sidewall thickness of condensation material layer.As shown in Figure 3 e, wherein the side wall of the patterns of openings and the grafting material
The lateral wall of layer 202 is concordant on vertical direction (i.e. on the direction of first wafer).
But the size of the patterns of openings is not limited to above-mentioned example, such as the size of the patterns of openings can be with
It is more than 2 times of opening size and 202 sidewall thickness of layer of bonding material of the engagement groove and.Therefore patterning step it
It afterwards can also in the vertical direction can be with the first metal described in member-retaining portion (i.e. on the direction of first wafer)
Layer 204, specific embodiment can be selected as needed, not further herein to be limited.
In the step A6, as illustrated in figure 3f, sacrificial layer is selected to fill the engagement groove and the patterns of openings, by
It is more than the opening size of the engagement groove, therefore the sacrificial material layer that shape is T-shaped in the opening size of the patterns of openings
206。
Wherein, the sacrificial material layer 206 can select tin, can be formed by electric plating method.
It can also include planarisation step after forming the sacrificial material layer 206, such as planarize the sacrifice material
The bed of material 206 is to the coating 205.
In the step A7, such as Fig. 3 g, the institute of first crystal column surface is removed using the sacrificial material layer as mask
Layer of bonding material and the first metal layer are stated, the first metal layer covered by the sacrificial material layer and institute are only retained
Layer of bonding material is stated, to be used to engage in subsequent steps.
In the step A8, such as Fig. 3 h, the sacrificial layer is removed, and then expose the layer of bonding material, wherein described
Minimizing technology can select wet method anti-etching.
Such as when the sacrificial material layer selects tin, selects stripping tin liquor to shell tin, remove the sacrificial layer.
In the step A9, such as Fig. 3 i, wherein the protective layer 203 can select green oil, green oil, that is, liquid photopolymerizable resistance
Solder flux is a kind of acrylic acid oligomer.As a kind of protective layer, the circuit and base material of welding are not required to coated in printed circuit board
On, or it is used as solder resist.
In the step A10, such as Fig. 3 j, the protective layer is patterned, to form opening and expose the engagement groove,
Wherein, the patterning method can select conventional method, it is not limited to a certain.
Step 2 is executed, the second wafer 101 is provided, metal column 102 is formed on second wafer, by the metal
Column is embedded and fills the engagement groove, so that first wafer and second wafer engage.
Wherein, second wafer 101 is logic wafer, and various logic device, example are formed in second wafer 101
Such as it is formed with various cmos devices and passive device.
As an example, the first functional component, such as transistor, interconnection structure can also be formed in the second wafer 101
And radio-frequency devices.
Wherein, transistor can be normal transistor, high-k/metal gate transistors, fin transistor or other are suitable
Transistor.Interconnection structure may include metal layer (such as layers of copper or aluminium layer), metal plug etc..Radio-frequency devices may include inductance
(inductor) devices such as.
In addition to including transistor, radio-frequency devices and interconnection structure, cmos device can also include other various feasible groups
Part, such as resistance, capacitance, MEMS device etc., are not defined herein.
Wherein, the concrete structure and forming method of the various components in cmos device, those skilled in the art can roots
It is selected with reference to the prior art according to actual needs, details are not described herein again.
Optionally, it is also formed with weld material layer 103 on the surface of the metal column, wherein the weld material layer 103
Tin can be selected, but is not limited to the material, details are not described herein.
Then, the metal column is embedded in the engagement groove, i.e., be inserted into the metal column and weld material layer 103
In the engagement groove, as shown in Figure 2 b, so that the weld material layer 103 is in direct contact with the layer of bonding material.
Then reflow step is executed, so that the metal column melts and is filled up completely the engagement groove, in the reflux
Weld material layer described in step covers the layer of bonding material and wraps up the metal column in the engagement groove
Surface, as shown in Figure 2 c.
Finally the method still further comprises use after engaging first wafer and second wafer
Packing material fills the step of gap between first wafer and second wafer.
So far, the introduction for preparing the semiconductor devices of the embodiment of the present invention is completed.After the above step, may be used also
To include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the manufacturing method of the present embodiment may be used also
To include other steps among above-mentioned each step or between different steps, these steps can be by current technique
Various techniques realize that details are not described herein again.
It is formed with engagement groove in first wafer in the preparation process of the semiconductor devices in the present invention,
The surface of the engagement groove is formed with layer of bonding material；Second wafer is formed with metal column on second wafer, wherein
The metal column is embedded and fills the engagement groove.Metal column by the way that Embedded riveting column type is arranged can prevent second
Wafer fragmentation, and circuit will not be made to disconnect after high-temperature technology and prolonged pressure, to make the property of device
It can be improved with yield.
In addition, compared to conventional solder-bump (solder bump), copper post may be implemented to be electrically connected, can also be the
Support is realized between one wafer and the second wafer, and there is better electric property and hot property.
Embodiment three
The embodiment of the present invention provides a kind of electronic device comprising electronic building brick and be electrically connected with the electronic building brick partly
Conductor device.
Wherein, the electronic device includes partly leading for the manufacturing method manufacture of the semiconductor devices according to embodiment two
Body device, or including the semiconductor devices described in embodiment one.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, can also be to have
The intermediate products of above-mentioned semiconductor device, such as：Cell phone mainboard etc. with the integrated circuit.
Wherein, Fig. 4 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loud speaker 305, microphone 306 etc..
The wherein described mobile phone handsets include semiconductor devices above-mentioned, or the semiconductor device according to embodiment two
Semiconductor devices obtained by the manufacturing method of part, the semiconductor devices include that the semiconductor devices includes：First wafer
201, it is formed with engagement groove in first wafer, layer of bonding material 202 is formed on the surface of the engagement groove；The
Two wafers 101 are formed with metal column 102 on second wafer, wherein the metal column is embedded and to fill the engagement recessed
Slot.
It is formed with engagement groove in first wafer in the semiconductor devices in the present invention, it is recessed in the engagement
The surface of slot is formed with layer of bonding material；Second wafer is formed with metal column on second wafer, wherein the metal column
It is embedded in and fills the engagement groove.Metal column by the way that Embedded riveting column type is arranged can prevent the second wafer fragmentation,
And circuit will not be made to disconnect after high-temperature technology and prolonged pressure, the performance and yield to make device carry
It is high.
In addition, compared to conventional solder-bump (solder bump), copper post may be implemented to be electrically connected, can also be the
Support is realized between one wafer and the second wafer, and there is better electric property and hot property.
The electronic device of the present invention, as a result of above-mentioned semiconductor device, thus equally has the advantages that above-mentioned.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (16)
1. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes：
First wafer is formed with engagement groove in first wafer, and engagement material is formed on the surface of the engagement groove
The bed of material；
Second wafer is formed with metal column on second wafer, wherein the metal column is embedded and to fill the engagement recessed
Slot.
2. semiconductor devices according to claim 1, which is characterized in that be additionally provided with package in the layer of bonding material
The weld material layer on the surface of the metal column in the engagement groove.
3. semiconductor devices according to claim 1, which is characterized in that it is recessed that the metal column is partially embedded into the engagement
Slot is positioned partially at the horizontal surface of second wafer or more.
4. semiconductor devices according to claim 3, which is characterized in that first wafer and second wafer it
Between be formed with the packing material for filling gap between first wafer and second wafer.
5. semiconductor devices according to claim 1, which is characterized in that the metal column includes copper post.
6. semiconductor devices according to claim 1, which is characterized in that first wafer is support wafer, described the
Two wafers are device wafers.
7. a kind of preparation method of semiconductor devices, which is characterized in that the method includes：
First wafer is provided, engagement groove is formed in first wafer, is formed with and connects on the surface of the engagement groove
Condensation material layer；
Second wafer is provided, metal column is formed on second wafer, by metal column insertion and fills the engagement
Groove, so that first wafer and second wafer engage.
8. the method according to the description of claim 7 is characterized in that first wafer and second wafer is made to engage
Method includes：
The metal column is embedded in the engagement groove；
Reflow step is executed, so that the metal column melts and is filled up completely the engagement groove.
9. according to the method described in claim 8, being connect it is characterized in that, being also formed with described in covering on the surface of the metal column
The weld material layer of condensation material layer, institute of the weld material layer package described in the reflow step in the engagement groove
State the surface of metal column.
10. the method according to the description of claim 7 is characterized in that connecting by first wafer and second wafer
After conjunction, the method is still further comprised fills gap between first wafer and second wafer using packing material
The step of.
11. the method according to the description of claim 7 is characterized in that the step of forming the engagement groove includes：
First wafer is provided, the first metal layer is formed on first wafer；
The first metal layer and first wafer are patterned, to form several engagement grooves；
On the first metal layer and the surface of the engagement groove forms the layer of bonding material；
The T-shaped sacrificial material layer of shape in the engagement groove；
The layer of bonding material of first crystal column surface and first metal are removed by mask of the sacrificial material layer
Layer；
The sacrificial layer is removed, to form the engagement groove.
12. according to the method for claim 11, which is characterized in that formed after the engagement groove, the method is also wrapped
It includes：
Protective layer is formed, to cover first wafer；
The protective layer is patterned, to form opening and expose the engagement groove.
13. according to the method for claim 11, which is characterized in that the method for forming the sacrificial material layer of the T shapes includes：
Form the coating for covering the layer of bonding material；
The coating is patterned, to form the patterns of openings that opening size is more than the engagement groove；
Sacrificial layer is selected to fill the engagement groove and the patterns of openings.
14. the method according to the description of claim 7 is characterized in that the metal column includes copper post.
15. the method according to the description of claim 7 is characterized in that first wafer is to support wafer, second wafer
For device wafers.
16. a kind of electronic device, which is characterized in that including the semiconductor devices described in one of claim 1 to 6.
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| JPH06342796A (en) * | 1993-05-31 | 1994-12-13 | Olympus Optical Co Ltd | Forming method of bump electrode |
| CN105097777A (en) * | 2014-04-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN104332419A (en) * | 2014-08-28 | 2015-02-04 | 南通富士通微电子股份有限公司 | Inversion-type chip packaging method |
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