CN108735725B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents
Semiconductor device, manufacturing method thereof and electronic device Download PDFInfo
- Publication number
- CN108735725B CN108735725B CN201710253829.6A CN201710253829A CN108735725B CN 108735725 B CN108735725 B CN 108735725B CN 201710253829 A CN201710253829 A CN 201710253829A CN 108735725 B CN108735725 B CN 108735725B
- Authority
- CN
- China
- Prior art keywords
- wafer
- bonding
- material layer
- metal
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
The invention relates to a semiconductor device, a method of manufacturing the same, and an electronic apparatus. The semiconductor device includes: the wafer structure comprises a first wafer, a second wafer and a third wafer, wherein a bonding groove is formed in the first wafer, and a bonding material layer is formed on the surface of the bonding groove; and a second wafer on which metal pillars are formed, wherein the metal pillars are embedded and fill the bonding grooves. The second wafer can be prevented from being cracked by arranging the embedded rivet-column type metal column, and the circuit can not be disconnected after high-temperature process and long-time pressure, so that the performance and yield of the device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
In the field of electronic consumption, multi-function devices are more and more popular with consumers, and compared with devices with simple functions, the manufacturing process of multi-function devices is more complicated, for example, a plurality of chips with different functions need to be integrated on a circuit board, so that a 3D Integrated Circuit (IC) technology is developed, where the 3D Integrated Circuit (IC) is defined as a system-level integrated structure, a plurality of chips are stacked in a vertical plane direction, so as to save space, a plurality of pins can be led out from an edge portion of each chip as needed, and the chips required to be connected with each other are interconnected through metal wires by using the pins as needed, but the above-mentioned method still has many disadvantages, for example, the number of stacked chips is large, and the connection relationship between the chips is complicated, so that a plurality of metal wires need to be used, and the final wiring manner is disordered, but also leads to an increase in volume.
At present, copper columns are widely applied in flip chip assembly processes (flip chip assembly processes).
However, the copper pillar manufacturing process involves more stress relative to the solder bump, which may result in wafer cracking and circuit breaking after high temperature processing and long stress, thereby degrading or even failing the device.
Therefore, in order to solve the above technical problems in the prior art, it is necessary to provide a new semiconductor device, a method for manufacturing the same, and an electronic apparatus.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the problems existing at present, the present invention provides a semiconductor device comprising:
the wafer structure comprises a first wafer, a second wafer and a third wafer, wherein a bonding groove is formed in the first wafer, and a bonding material layer is formed on the surface of the bonding groove;
and a second wafer on which metal pillars are formed, wherein the metal pillars are embedded and fill the bonding grooves.
Optionally, a welding material layer is further disposed on the bonding material layer to wrap the surface of the metal pillar embedded in the bonding groove.
Optionally, the metal pillar is partially embedded in the bonding groove, partially above a horizontal surface of the second wafer.
Optionally, a filling material filling a gap between the first wafer and the second wafer is formed between the first wafer and the second wafer.
Optionally, the metal pillar comprises a copper pillar.
Optionally, the first wafer is a support wafer, and the second wafer is a device wafer.
The invention also provides a preparation method of the semiconductor device, which comprises the following steps:
providing a first wafer, wherein a bonding groove is formed in the first wafer, and a bonding material layer is formed on the surface of the bonding groove;
providing a second wafer, forming a metal column on the second wafer, and embedding and filling the metal column into the bonding groove so as to bond the first wafer and the second wafer.
Optionally, the method of bonding the first wafer and the second wafer comprises:
embedding the metal posts in the engagement grooves;
a reflow step is performed to melt the metal pillar and completely fill the bonding groove.
Optionally, a solder material layer covering the bonding material layer is further formed on the surface of the metal pillar, and the solder material layer covers the surface of the metal pillar embedded in the bonding groove in the reflow step.
Optionally, after the first wafer and the second wafer are bonded, the method further includes a step of filling a gap between the first wafer and the second wafer with a filling material.
Optionally, the step of forming the engagement groove includes:
providing a first wafer, and forming a first metal layer on the first wafer;
patterning the first metal layer and the first wafer to form a plurality of joint grooves;
forming the bonding material layer on the first metal layer and the surface of the bonding groove;
forming a T-shaped sacrificial material layer in the bonding groove;
removing the bonding material layer and the first metal layer on the surface of the first wafer by taking the sacrificial material layer as a mask;
and removing the sacrificial layer to form the bonding groove.
Optionally, after forming the engagement groove, the method further comprises:
forming a protective layer to cover the first wafer;
and patterning the protective layer to form an opening and expose the bonding groove.
Optionally, the method for forming the T-shaped sacrificial material layer includes:
forming a covering layer covering the bonding material layer;
patterning the covering layer to form an opening pattern with an opening size larger than that of the bonding groove;
and filling the bonding groove and the opening pattern with a sacrificial layer.
Optionally, the metal pillar comprises a copper pillar.
Optionally, the first wafer is a support wafer, and the second wafer is a device wafer.
The invention also provides an electronic device comprising the semiconductor device.
In order to solve the problem of second wafer fragmentation caused by overlarge pressure, the invention provides a semiconductor device and a preparation method thereof, wherein a bonding groove is formed in a first wafer in the semiconductor device, and a bonding material layer is formed on the surface of the bonding groove; a metal pillar is formed on the second wafer, wherein the metal pillar is embedded in and fills the bonding groove. The second wafer can be prevented from being cracked by arranging the embedded rivet-column type metal column, and the circuit can not be disconnected after high-temperature process and long-time pressure, so that the performance and yield of the device are improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 is a schematic flow chart of a method of manufacturing a semiconductor device according to another embodiment of the present invention;
FIGS. 2A-2D are cross-sectional views of structures formed at steps associated with a method of fabricating a semiconductor device in accordance with an embodiment of the present invention;
FIGS. 3A-3J are cross-sectional views of structures formed at steps associated with a method of fabricating a first wafer in a semiconductor device, in accordance with an embodiment of the present invention;
fig. 4 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
The manufacturing method of the semiconductor device in the prior art comprises the following steps: providing a first wafer, forming a bonding material layer on the first wafer, wherein the bonding material layer is in a convex shape, then providing a second wafer, wherein a metal column is formed on the second wafer, bonding the metal column and the bonding material layer, and then filling a gap between the first wafer and the second wafer.
The method has the advantages that the height of the copper pillar is large, but the contact area with the second wafer is small, so that large pressure needs to be applied in the melting and pressing process, the second wafer is cracked, and a circuit is broken after the high-temperature process and long-time pressure, so that the performance of the device is reduced, and even the device fails.
To this end, in order to solve the above-mentioned problems, the present application provides a method of manufacturing a semiconductor device, the method including:
providing a first wafer, wherein a bonding groove is formed in the first wafer, and a bonding material layer is formed on the surface of the bonding groove;
providing a second wafer, forming metal columns on the second wafer, and embedding and filling the metal columns into the grooves so as to enable the first wafer and the second wafer to be jointed.
Wherein the method of bonding the first wafer and the second wafer comprises:
embedding the metal posts in the engagement grooves;
a reflow step is performed to melt the metal pillar and completely fill the bonding groove.
In addition, the present invention also provides a semiconductor device including:
the wafer structure comprises a first wafer, a second wafer and a third wafer, wherein a bonding groove is formed in the first wafer, and a bonding material layer is formed on the surface of the bonding groove;
and a second wafer on which metal pillars are formed, wherein the metal pillars are embedded and fill the bonding grooves.
According to the invention, a bonding groove is formed in the first wafer, and a bonding material layer is formed on the surface of the bonding groove; and a second wafer on which metal pillars are formed, wherein the metal pillars are embedded and fill the bonding grooves. The second wafer can be prevented from being cracked by arranging the embedded rivet-column type metal column, and the circuit can not be disconnected after high-temperature process and long-time pressure, so that the performance and yield of the device are improved.
In addition, compared with a conventional solder bump (solder bump), the copper pillar can realize electrical connection, can also realize support between the first wafer and the second wafer, and has better electrical performance and thermal performance.
Example one
In order to solve this problem, the present invention provides a semiconductor device, which is further described with reference to fig. 2D.
Wherein the semiconductor device includes:
a first wafer 201 in which a bonding groove is formed, and a bonding material layer 202 is formed on a surface of the bonding groove;
a second wafer 101 on which metal pillars 102 are formed, wherein the metal pillars are embedded and fill the bonding grooves.
Specifically, the first wafer 201 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
In the present application, the process is a flip chip assembly process (flip chip assembly process), and thus the first wafer is a support wafer or a substrate.
Various logic devices, such as various CMOS devices and passive devices, may be formed in the first wafer.
Different from the prior art, the metal posts formed in the invention are rivet posts, namely, the metal posts are riveted in the first wafer, so that the first wafer is provided with a joint groove for riveting and embedding the metal posts.
Wherein, the surface of the bonding groove is also formed with a bonding material layer 202, and the bonding material layer 202 is used for bonding in the subsequent process.
The bonding material layer 202 is made of a metal material, wherein the bonding material layer 202 is made of copper, aluminum, cobalt (Co), molybdenum (Mo), titanium nitride (TiN), a conductive material containing tungsten, or a combination thereof.
The bonding material layer 202 is copper in this embodiment.
The second wafer 101 is a logic wafer, and various logic devices, such as various CMOS devices and passive devices, are formed in the second wafer 101.
As an example, first functional components, such as transistors, interconnect structures, and radio frequency devices, may also be formed in the second wafer 101.
The transistors may be normal transistors, high-k metal gate transistors, fin-type transistors, or other suitable transistors. The interconnect structure may include a metal layer (e.g., a copper or aluminum layer), a metal plug, and the like. The radio frequency device may include an inductor (inductor) or the like.
In addition to transistors, rf devices, and interconnect structures, CMOS devices may include various other possible components, such as resistors, capacitors, MEMS devices, and the like, without limitation.
The specific structure and the forming method of each component in the CMOS device may be selected by those skilled in the art according to actual needs by referring to the prior art, and are not described herein again.
Optionally, a soldering material layer 103 is further formed on the surface of the metal pillar, wherein the soldering material layer 103 may be tin, but is not limited to the material, and is not described herein again.
Wherein the metal pillar is embedded in the bonding groove, that is, the metal pillar and the welding material layer 103 are inserted into the bonding groove, as shown in fig. 2D, so that the welding material layer 103 is in direct contact with the bonding material layer.
The metal post is reflowed, melted and completely filled in the bonding groove, a solder material layer 103 is further formed on the surface of the metal post, and the solder material layer covers the bonding material layer and wraps the surface of the metal post embedded in the bonding groove in the reflowing step.
And a filling material is arranged between the first wafer and the second wafer so as to fill a gap between the first wafer and the second wafer.
In the semiconductor device, a bonding groove is formed in the first wafer, and a bonding material layer is formed on the surface of the bonding groove; and a second wafer on which metal pillars are formed, wherein the metal pillars are embedded and fill the bonding grooves. The second wafer can be prevented from being cracked by arranging the embedded rivet-column type metal column, and the circuit can not be disconnected after high-temperature process and long-time pressure, so that the performance and yield of the device are improved.
In addition, compared with a conventional solder bump (solder bump), the copper pillar can realize electrical connection, can also realize support between the first wafer and the second wafer, and has better electrical performance and thermal performance.
Example two
Hereinafter, detailed steps of an exemplary method of a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a schematic flow chart of a method of manufacturing a semiconductor device according to another embodiment of the present invention; FIGS. 2A-2D are cross-sectional views of structures formed at steps associated with a method of fabricating a semiconductor device in accordance with an embodiment of the present invention; fig. 3A-3J are cross-sectional views of structures formed at steps associated with a method of fabricating a first wafer in a semiconductor device in accordance with an embodiment of the present invention.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to another embodiment of the present invention, and specifically includes:
step S1: providing a first wafer, wherein a bonding groove is formed in the first wafer, and a bonding material layer is formed on the surface of the bonding groove;
step S2: providing a second wafer, forming a metal column on the second wafer, and embedding and filling the metal column into the bonding groove so as to bond the first wafer and the second wafer.
The method for manufacturing the semiconductor device of the embodiment specifically includes the following steps:
step one, as shown in fig. 2a, a first wafer 201 is provided, a bonding groove is formed in the first wafer, and a bonding material layer 202 is formed on a surface of the bonding groove.
Specifically, the first wafer 201 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
In the present application, the process is a flip chip assembly process (flip chip assembly process), and thus the first wafer is a support wafer or a substrate.
Various logic devices, such as various CMOS devices and passive devices, may be formed in the first wafer.
Different from the prior art, the metal posts formed in the invention are rivet posts, namely, the metal posts are riveted in the first wafer, so that the first wafer is provided with a joint groove for riveting and embedding the metal posts.
Wherein, the surface of the bonding groove is also formed with a bonding material layer 202, and the bonding material layer 202 is used for bonding in the subsequent process.
The bonding material layer 202 is made of a metal material, wherein the bonding material layer 202 is made of copper, aluminum, cobalt (Co), molybdenum (Mo), titanium nitride (TiN), a conductive material containing tungsten, or a combination thereof.
The bonding material layer 202 is copper in this embodiment.
The method for manufacturing the first wafer includes, but is not limited to, the following steps, which are further described with reference to fig. 3A to 3J.
Step A1: providing a first wafer, and forming a first metal layer on the first wafer;
step A2: patterning the first metal layer and the first wafer to form a plurality of joint grooves;
step A3: forming the bonding material layer on the first metal layer and the surface of the bonding groove;
step A4: forming a covering layer covering the bonding material layer;
step A5: patterning the covering layer to form an opening pattern with an opening size larger than that of the bonding groove;
step A6: filling the joint groove and the opening pattern with a sacrificial layer to form a T-shaped sacrificial material layer;
step A7: removing the bonding material layer and the first metal layer on the surface of the first wafer by taking the sacrificial material layer as a mask;
step A8: and removing the sacrificial layer to form the bonding groove.
Step A9: forming a protective layer to cover the first wafer;
step A10: and patterning the protective layer to form an opening and expose the bonding groove.
In step a1, as shown in fig. 3a, a first wafer 201 is provided, on which a first metal layer 204 is formed.
The deposition method of the first metal layer 204 may be one of low-pressure chemical vapor deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and the like, and is preferably Physical Vapor Deposition (PVD) in the present invention.
Wherein the first metal layer 204 is copper, aluminum, cobalt (Co), molybdenum (Mo), titanium nitride (TiN), and a conductive material containing tungsten, or a combination thereof.
The first metal layer 204 is copper in this embodiment.
In step a2, as shown in fig. 3B, the engaging groove may be formed by numerical control drilling or laser drilling.
The bonding groove may be formed by etching, which is not limited herein and may be selected as desired.
Wherein the number of the engagement grooves is not limited to a certain range of values. Also, the size of the opening of the engagement groove is not limited.
In the step a3, as shown in fig. 3c, the bonding material layer 202 is formed on the first metal layer and on the surface of the bonding groove, wherein the deposition method of the bonding material layer 202 may be one of Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD), and is preferably Physical Vapor Deposition (PVD) in the present invention.
In addition, the bonding material layer 202 may also be formed by electroplating, for example, when the bonding material layer 202 is formed by copper, the bonding material layer 202 is formed by copper plating.
Specifically, a seed layer of copper metal is first deposited in the bonding groove in this step, and the deposition method of the seed layer may be a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD) method, or the like.
The copper metal is then formed by Electrochemical Copper Plating (ECP), and preferably, additives such as a LEVELER (leveller), an accelerator (accelerater) and an inhibitor (suppresor) may also be used in the plating.
Preferably, the method further comprises the step of annealing after the metallic copper is formed, wherein the annealing can be carried out at 80-160 ℃ for 2-4 hours, so as to promote the recrystallization of the copper, grow grains, reduce the resistance and improve the stability.
In the step a4, as shown in fig. 3d, a cover layer 205 is formed in this step by a lamination method, in which the cover layer 205 completely covers the bonding material layer 202 and the bonding grooves, but does not fill the bonding grooves.
The covering layer can be made of conventional copper foil and the like, and is not further limited herein.
In the step a5, as shown in fig. 3e, the cover layer is exposed to form an opening pattern, wherein an opening size of the opening pattern is larger than an opening size of the engaging groove.
In an embodiment of the invention, the size of the opening pattern is equal to the sum of the opening size of the bonding groove and 2 times the thickness of the sidewall of the bonding material layer 202. As shown in fig. 3e, the sidewalls of the opening pattern are flush with the outer sidewall of the bonding material layer 202 in the vertical direction (i.e., the direction perpendicular to the first wafer).
However, the size of the opening pattern is not limited to the above example, and for example, the size of the opening pattern may be larger than the sum of the opening size of the bonding groove and the thickness of the sidewall of the bonding material layer 202 by 2 times. Therefore, after the patterning step, a portion of the first metal layer 204 may also remain in a vertical direction (i.e., a direction perpendicular to the first wafer), and a specific embodiment may be selected as needed, which is not further limited herein.
In step a6, as shown in fig. 3f, a sacrificial layer is selected to fill the bonding groove and the opening pattern, and a T-shaped sacrificial material layer 206 is formed because the opening size of the opening pattern is larger than that of the bonding groove.
The sacrificial material layer 206 may be tin, which may be formed by electroplating.
A planarization step may also be included after forming the layer of sacrificial material 206, such as planarizing the layer of sacrificial material 206 to the capping layer 205.
In step a7, as shown in fig. 3g, the sacrificial material layer is used as a mask to remove the bonding material layer and the first metal layer on the first wafer surface, and only the first metal layer and the bonding material layer covered by the sacrificial material layer remain for bonding in the subsequent step.
In step A8, as shown in fig. 3h, the sacrificial layer is removed to expose the bonding material layer, wherein the removal method may be wet etching.
For example, when the sacrificial material layer is tin, a tin stripping solution is used for stripping tin, and the sacrificial layer is removed.
In step a9, as shown in fig. 3i, the protective layer 203 may be green oil, which is a liquid photo solder resist and is an acrylic oligomer. As a protective layer, it is coated on the circuit and substrate of printed circuit board without soldering, or used as solder resist.
In the step a10, as shown in fig. 3j, the protection layer is patterned to form an opening and expose the bonding groove, wherein the patterning method may be a conventional method, and is not limited to one.
And performing a second step, providing a second wafer 101, forming a metal pillar 102 on the second wafer, and embedding and filling the metal pillar into the bonding groove to bond the first wafer and the second wafer.
The second wafer 101 is a logic wafer, and various logic devices, such as various CMOS devices and passive devices, are formed in the second wafer 101.
As an example, first functional components, such as transistors, interconnect structures, and radio frequency devices, may also be formed in the second wafer 101.
The transistors may be normal transistors, high-k metal gate transistors, fin-type transistors, or other suitable transistors. The interconnect structure may include a metal layer (e.g., a copper or aluminum layer), a metal plug, and the like. The radio frequency device may include an inductor (inductor) or the like.
In addition to transistors, rf devices, and interconnect structures, CMOS devices may include various other possible components, such as resistors, capacitors, MEMS devices, and the like, without limitation.
The specific structure and the forming method of each component in the CMOS device may be selected by those skilled in the art according to actual needs by referring to the prior art, and are not described herein again.
Optionally, a soldering material layer 103 is further formed on the surface of the metal pillar, wherein the soldering material layer 103 may be tin, but is not limited to the material, and is not described herein again.
Then, the metal stud is inserted into the bonding groove, i.e., the metal stud and the solder material layer 103 are inserted into the bonding groove, as shown in fig. 2b, so that the solder material layer 103 is in direct contact with the bonding material layer.
A reflow step is then performed to melt the metal pillar and completely fill the bonding groove, in which the solder material layer covers the bonding material layer and wraps around the surface of the metal pillar embedded in the bonding groove, as shown in fig. 2 c.
Finally, the method further comprises the step of filling the gap between the first wafer and the second wafer with a filling material after the first wafer and the second wafer are bonded.
Thus, the introduction of the embodiment of the present invention to manufacture the semiconductor device is completed. After the above steps, other related steps may also be included, which are not described herein again. Besides the above steps, the manufacturing method of this embodiment may further include other steps in the above steps or between different steps, and these steps may be implemented by various processes in the current process, and are not described herein again.
In the preparation process of the semiconductor device, a bonding groove is formed in the first wafer, and a bonding material layer is formed on the surface of the bonding groove; and a second wafer on which metal pillars are formed, wherein the metal pillars are embedded and fill the bonding grooves. The second wafer can be prevented from being cracked by arranging the embedded rivet-column type metal column, and the circuit can not be disconnected after high-temperature process and long-time pressure, so that the performance and yield of the device are improved.
In addition, compared with a conventional solder bump (solder bump), the copper pillar can realize electrical connection, can also realize support between the first wafer and the second wafer, and has better electrical performance and thermal performance.
EXAMPLE III
An embodiment of the invention provides an electronic device, which comprises an electronic component and a semiconductor device electrically connected with the electronic component.
The electronic device includes the semiconductor device manufactured by the method for manufacturing a semiconductor device according to the second embodiment, or includes the semiconductor device according to the first embodiment.
The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, and a PSP, or may be an intermediate product having the semiconductor device, for example: a mobile phone mainboard with the integrated circuit, and the like.
Wherein figure 4 shows an example of a mobile telephone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.
Wherein the mobile phone handset comprises the semiconductor device described above, or the semiconductor device manufactured by the method for manufacturing a semiconductor device according to embodiment two, the semiconductor device comprising the semiconductor device comprises: a first wafer 201 in which a bonding groove is formed, and a bonding material layer 202 is formed on a surface of the bonding groove; a second wafer 101 on which metal pillars 102 are formed, wherein the metal pillars are embedded and fill the bonding grooves.
In the semiconductor device, a bonding groove is formed in the first wafer, and a bonding material layer is formed on the surface of the bonding groove; and a second wafer on which metal pillars are formed, wherein the metal pillars are embedded and fill the bonding grooves. The second wafer can be prevented from being cracked by arranging the embedded rivet-column type metal column, and the circuit can not be disconnected after high-temperature process and long-time pressure, so that the performance and yield of the device are improved.
In addition, compared with a conventional solder bump (solder bump), the copper pillar can realize electrical connection, can also realize support between the first wafer and the second wafer, and has better electrical performance and thermal performance.
The electronic device of the present invention also has the above advantages because of the use of the above semiconductor device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. A method of fabricating a semiconductor device, the method comprising:
providing a first wafer, wherein a bonding groove is formed in the first wafer, and a bonding material layer is formed on the surface of the bonding groove;
providing a second wafer, forming a metal column on the second wafer, and embedding and filling the metal column into the bonding groove so as to bond the first wafer and the second wafer;
wherein the step of forming the engagement groove includes:
providing a first wafer, and forming a first metal layer on the first wafer;
patterning the first metal layer and the first wafer to form a plurality of joint grooves;
forming the bonding material layer on the first metal layer and the surface of the bonding groove;
forming a T-shaped sacrificial material layer in the bonding groove;
removing the bonding material layer and the first metal layer on the surface of the first wafer by taking the sacrificial material layer as a mask;
and removing the sacrificial material layer to form the joint groove.
2. The method of claim 1, wherein the bonding the first wafer and the second wafer comprises:
embedding the metal posts in the engagement grooves;
a reflow step is performed to melt the metal pillar and completely fill the bonding groove.
3. The method of claim 2, wherein a solder material layer is further formed on the surface of the metal pillar to cover the bonding material layer.
4. The method of claim 1, wherein a filler material is disposed between the first wafer and the second wafer to fill a gap between the first wafer and the second wafer.
5. The method of claim 1, wherein after forming the engagement groove, the method further comprises:
forming a protective layer to cover the first wafer;
and patterning the protective layer to form an opening and expose the bonding groove.
6. The method of claim 1, wherein forming the T-shaped sacrificial material layer comprises:
forming a covering layer covering the bonding material layer;
patterning the covering layer to form an opening pattern with an opening size larger than that of the bonding groove;
and filling the bonding groove and the opening pattern with a sacrificial layer.
7. The method of claim 1, wherein the metal pillar comprises a copper pillar.
8. The method of claim 1, wherein the first wafer is a support wafer and the second wafer is a device wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710253829.6A CN108735725B (en) | 2017-04-18 | 2017-04-18 | Semiconductor device, manufacturing method thereof and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710253829.6A CN108735725B (en) | 2017-04-18 | 2017-04-18 | Semiconductor device, manufacturing method thereof and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108735725A CN108735725A (en) | 2018-11-02 |
| CN108735725B true CN108735725B (en) | 2020-06-05 |
Family
ID=63925111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710253829.6A Active CN108735725B (en) | 2017-04-18 | 2017-04-18 | Semiconductor device, manufacturing method thereof and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108735725B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06342796A (en) * | 1993-05-31 | 1994-12-13 | Olympus Optical Co Ltd | Forming method of bump electrode |
| CN104332419A (en) * | 2014-08-28 | 2015-02-04 | 南通富士通微电子股份有限公司 | Inversion-type chip packaging method |
| CN204391096U (en) * | 2014-12-18 | 2015-06-10 | 南通富士通微电子股份有限公司 | Flip-chip packaged structure |
| CN105097777A (en) * | 2014-04-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
-
2017
- 2017-04-18 CN CN201710253829.6A patent/CN108735725B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06342796A (en) * | 1993-05-31 | 1994-12-13 | Olympus Optical Co Ltd | Forming method of bump electrode |
| CN105097777A (en) * | 2014-04-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
| CN104332419A (en) * | 2014-08-28 | 2015-02-04 | 南通富士通微电子股份有限公司 | Inversion-type chip packaging method |
| CN204391096U (en) * | 2014-12-18 | 2015-06-10 | 南通富士通微电子股份有限公司 | Flip-chip packaged structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108735725A (en) | 2018-11-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102064863B1 (en) | Method of fabricating Semiconductor Devices Having TSV | |
| CN102187452B (en) | Semiconductor substrates with unitary vias and via terminals, and associated systems and methods | |
| US9147640B2 (en) | Semiconductor devices having back side bonding structures | |
| US9099460B2 (en) | Stack semiconductor package and manufacturing the same | |
| US20130313722A1 (en) | Through-silicon via (tsv) semiconductor devices having via pad inlays | |
| CN105845589B (en) | A kind of semiconductor devices and its manufacturing method and electronic device | |
| US20140048952A1 (en) | Semiconductor device including through via structures and redistribution structures | |
| JP2010510663A (en) | Method for packaging semiconductor devices and assembled connectors | |
| EP2831913B1 (en) | Method of providing a via hole and routing structure | |
| CN102376695A (en) | Stacked semiconductor device and method of fabricating the same | |
| US20160020193A1 (en) | PACKAGE ON PACKAGE (PoP) INTEGRATED DEVICE COMPRISING A CAPACITOR IN A SUBSTRATE | |
| US9831103B2 (en) | Manufacturing method of interposed substrate | |
| JP2008258478A (en) | Electronic component device and its manufacturing method | |
| CN103137566A (en) | Method for forming an integrated circuit | |
| CN105826334A (en) | Image sensor packages and methods of fabricating the same | |
| CN107305840B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| US9852965B2 (en) | Semiconductor devices with through electrodes and methods of fabricating the same | |
| US20060281223A1 (en) | Packaging method and package using the same | |
| CN108735725B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| US8816477B2 (en) | Semiconductor package having a contamination preventing layer formed in the semiconductor chip | |
| CN107316847B (en) | Semiconductor device packaging structure and electronic device | |
| EP3128546A1 (en) | Power amplifier module package and packaging method thereof | |
| CN101506965B (en) | Semiconductor chip, semiconductor mounting module, mobile communication device, and process for producing semiconductor chip | |
| CN107293513B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| CN107346746B (en) | Semiconductor device, manufacturing method thereof and electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |