CN108735709A - 3-D stacks semiconductor device and its manufacturing method - Google Patents
3-D stacks semiconductor device and its manufacturing method Download PDFInfo
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- CN108735709A CN108735709A CN201710257945.5A CN201710257945A CN108735709A CN 108735709 A CN108735709 A CN 108735709A CN 201710257945 A CN201710257945 A CN 201710257945A CN 108735709 A CN108735709 A CN 108735709A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
Abstract
The invention discloses a kind of 3-D stacks semiconductor device and its manufacturing methods.The method includes：Using the combination of N number of etching mask with the removal number of plies that produce O kinds in these conductive layers and these insulating layers in contact area different, to form multiple touchdown areas (landing area) on these conductive layers in contact area, it is not superimposed these conductive layers above these touchdown areas, each mask includes multiple masks areas and multiple opening etch areas, N is the integer more than or equal to 2, O is integer more than 2,2N‑1<O≦2N；And these conductive layers of part and these insulating layers in replacement contact area, to generate the multiple etching depths for extending to these conductive layers from a superficial layer, each etching depth extends to corresponding touchdown area, wherein, the corresponding etching depth of each etching mask step is equal to 1P layer stacked structures, 2P layer stacked structures and nP layer stacked structures, n is the integer more than or equal to 3, and P is the integer more than or equal to 1.
Description
Technical field
The invention relates to a kind of semiconductor device and its manufacturing methods, and in particular to a kind of 3-D stacks half
Conductor device and its manufacturing method.
Background technology
With the development of semiconductor technology, various semiconductor element continues to introduce new.Semiconductor element can pass through suitable
Various electrical functionalities may be implemented after local arrangement.Various electronic products have all widely applied various semiconductor elements now.
Under the trend for wherein pursuing " light, thin, short, small " with electronic product, how by the volume-diminished of semiconductor element,
Or increase circuit closeness under fixed volume, it has also become one important research developing direction of semiconductor industry.
Invention content
The invention relates to a kind of 3-D stacks semiconductor device and its manufacturing methods.
According to an aspect of the invention, it is proposed that a kind of manufacturing method of 3-D stacks semiconductor device.3-D stacks are partly led
Body device includes multi-layer laminate structure and there is a burst of column region and a contact area, each laminated construction to include a conductive layer and one
Insulating layer, these conductive layers and these insulating layer cross laminates, the method connect to form multiple centres in a contact area
Fitting (interlayer connector), each intermediate connector are connected to corresponding each conductive layer.The method includes：Use N
The combination of a etching mask is with the removal layer that produce O kinds in these conductive layers and these insulating layers in contact area different
Number, to form multiple touchdown areas (landing area) on these conductive layers in contact area, on these touchdown areas
Side is not superimposed these conductive layers, and each mask includes multiple masks areas and multiple opening etch areas, and N is more than or equal to 2
Integer, O is integer more than 2,2N-1<O≦2N, m is the serial number for these masks, so that a mask therein
M be equal to 1, the m of another mask is equal to 2, until m is equal to N；And replace contact area in these conductive layers of part and these
Insulating layer, including：With selected sequence using in these mask etching contact areas these conductive layers of part and these absolutely
Edge layer n times, to generate the multiple etching depths for extending to these conductive layers from a superficial layer, each etching depth extends to corresponding
Touchdown area, wherein when m=1, corresponding etching depth is equal to 1P layer stacked structures；And when m=2, corresponding etching depth
2P layer stacked structures are equal to, P is the integer more than or equal to 1.
According to another aspect of the invention, it is proposed that a kind of 3-D stacks semiconductor device.3-D stacks semiconductor device packet
Multi-layer laminate structure and multiple intermediate connectors (interlayer connector) are included, each laminated construction includes a conductive layer
And an insulating layer, these conductive layers and these insulating layer cross laminates, wherein these laminated construction are to form 3-D stacks partly to lead
A burst of column region, a contact area and a virtual region for body device, virtual region abut array region and contact area and position
In the same side of array region and contact area, intermediate connector is formed in contact area, and each intermediate connector is connected to pair
Each conductive layer answered.
In order to which the above-mentioned and other aspect to the present invention has a better understanding, special embodiment below, and coordinate appended attached
Detailed description are as follows for figure：
Description of the drawings
Figure 1A is painted the top view of the 3-D stacks semiconductor device of an embodiment.
Figure 1B is painted the top view of the 3-D stacks semiconductor device of another embodiment.
Fig. 2A~2E is painted the flow chart of the manufacturing method of the 3-D stacks semiconductor device of an embodiment.
Fig. 3 A~3F are painted the flow chart of the manufacturing method of the 3-D stacks semiconductor device of another embodiment.
Fig. 4 A~4D are painted change schematic diagram of the photoresist layer of embodiment during etching and reduction.
Fig. 5 A~5B and Fig. 6 A~6U are painted the flow of the manufacturing method of the 3-D stacks semiconductor device of another embodiment
Figure.
Fig. 7 A~7T are painted the flow chart of the manufacturing method of the 3-D stacks semiconductor device of another embodiment.
【Symbol description】
100,200：3-D stacks semiconductor device
100A：Array region
100B：Contact area
100C：Virtual region
110：Laminated construction
111：Conductive layer
112：Insulating layer
120：Word-line decoder
140：Intermediate connector
180：Media filler object
180a：Contact openings
610,710,810,910：Photoresist layer
D1,D2：Depth
DR1：First direction
DR2：Second direction
DR3：Third direction
h1,t1：Thickness
PR,PR1,PR2,PR3：Mask
PR1a,PR2a,PR3a：Masks area
PR1b,PR2b,PR3b：Be open etch areas
R：Touchdown area
tx：Width
Specific implementation mode
It is to propose that various embodiments are described in detail below, embodiment can't limit only to illustrate as example
The range to be protected of the present invention.In addition, the attached drawing in embodiment is that portion of element is omitted, to clearly show that the technology of the present invention
Feature.
Figure 1A is painted the top view of the 3-D stacks semiconductor device of an embodiment.As shown in Figure 1A, 3-D stacks are partly led
Body device 100 includes multi-layer laminate structure 110 and multiple intermediate connectors (interlayer connector) 140, stack
Layer structure 110 includes a conductive layer 111 and an insulating layer 112, these conductive layers 111 and these 112 cross laminates of insulating layer (are asked
With reference to Fig. 5 A~5B).These laminated construction 110 are a burst of column region 100A to form 3-D stacks semiconductor device 100, one connect
A region 100B and virtual region 100C is touched, virtual region 100C abuts array region 100A and contact area 100B and is located at
The same side of array region 100A and contact area 100B, intermediate connector 140 are formed in contact area 100B, and each centre connects
Fitting 140 is connected to corresponding each conductive layer.
In Figure 1A, Y0~Y21 indicates that the coordinate of Y-direction, C indicate that the central point of X-direction, L1~L18 and R1~R18 indicate
The coordinate that X-direction extends from central point C to both sides, coordinate Y0~Y21 collocation C, L1~L18 and R1~R18 can define out three-dimensional
Multiple subregions of stacked semiconductor device 100.In Figure 1A, the digital representation subregion marked in each sub-regions it is folded
The number of plies of layer structure 110, and be the upper surface of the subregion with the conductive layer 111 of laminated construction 110.For example, array region
All subregions in 100A all have 56 layer stacked structures 110, and contact area 100B then has 56 kinds of numbers of plies (1~56 layer),
And virtual region 100C then has 5 kinds of numbers of plies (2~6 layers).Subsequent attached drawing indicates in the same manner herein, no longer superfluous later
It states.
As shown in Figure 1A, the laminated construction 110 in virtual region 100C and in contact area 100B all has hierarchic structure,
And the ladder number in virtual region 100C is less than the ladder number in contact area 100B.For example, as shown in Figure 1A, empty
Ladder number in quasi- region 100C is 5 stratum, and the ladder number in contact area 100B is 56 stratum.
In embodiment, the ladder height in virtual region 100C is less than or equal to the ladder height in contact area 100B.
For example, as shown in Figure 1A, the ladder height in virtual region 100C is 6 layer stacked structures 110, and in contact area 100B
Ladder height be 56 layer stacked structures 110.
As shown in Figure 1A, there is a difference in height, this is highly worse than array between array region 100A and contact area 100B
The interface of region 100A and contact area 100B successively decrease along the direction for being directed away from virtual region 100C.For example, most
Difference in height at virtual region 100C is 49 layers (56-7), and is gradually successively decreased, until farthest away from the height at virtual region 100C
Degree difference is 0 layer (56-56).
In some embodiments, this difference of height is successively decreased as unit of P layer stacked structures, and P is the integer more than or equal to 1.
For example, as shown in Figure 1A, in embodiment, P is equal to 7, then difference in height is successively decreased as unit of 7 layer stacked structures, from 49,42,
35,28,21,14,7 it is decremented to 0 layer.
As shown in Figure 1A, 3-D stacks semiconductor device 100 further includes an at least word-line decoder 120, word-line decoder
120 are connected to array region 100A, and word-line decoder 120 and virtual region 100C are located at the adjacent of array region 100A
Both sides.
Figure 1B is painted the top view of the 3-D stacks semiconductor device of another embodiment.In the present embodiment with previous embodiment
Same or analogous element is to continue to use same or like element numbers, and before the related description of same or similar element please refers to
It states, details are not described herein.
As shown in Figure 1B, in 3-D stacks semiconductor device 200, laminated construction 110 more may include multiple laminations at interval
Block, there are one array region 100A and at least one contact area 100B for each lamination block tool, and 3-D stacks semiconductor fills
It sets 200 tools and is located at the opposite sides of lamination block there are two virtual region 100C, two virtual region 100C.
According to some embodiments, the present invention provides the manufacturing method of 3-D stacks semiconductor device.The method is to three
It ties up in the contact area of stacked semiconductor device and forms multiple intermediate connectors (interlayer connector), each centre connects
Fitting is connected to corresponding each conductive layer.According to some embodiments, the method includes：Using the combination of N number of etching mask in
The removal number of plies that produce O kinds in these conductive layers and these insulating layers in contact area different, to form multiple touch-down zones
Domain (landing area) is not superimposed these conductions on these conductive layers in contact area above these touchdown areas
Layer, each mask include multiple masks areas and multiple opening etch areas, and N is the integer more than or equal to 2, and O is whole more than 2
Number, 2N-1<O≦2N, m is the serial number for these masks, so that the m of a mask therein is equal to 1, the m of another mask
Equal to 2, until m is equal to N；And these conductive layers of part and these insulating layers in replacement contact area, including：With selected
Sequence using these conductive layers of part and these insulating layer n times in these mask etching contact areas, to generate from a table
Face layer extends to multiple etching depths of these conductive layers, and each etching depth extends to corresponding touchdown area, wherein m=1
When, corresponding etching depth is equal to 1P layer stacked structures；And when m=2, corresponding etching depth is equal to 2P layer laminate knots
Structure, P are the integer more than or equal to 1.
In some embodiments, when m is greater than or equal to 3, corresponding etching depth is equal to nP layer stacked structures, n be more than
Or the integer equal to 3.In embodiment, n includes being not equal to 2m-1Integer, and n be less than or equal to 2N-1。
It is the manufacturing method for illustrating 3-D stacks semiconductor device above-mentioned with multiple embodiments below.
Fig. 2A~2E is painted the flow chart of the manufacturing method of the 3-D stacks semiconductor device of an embodiment.In the present embodiment
It is to continue to use same or like element numbers with the same or analogous element of previous embodiment, and the correlation of same or similar element
Illustrate to please refer to aforementioned, details are not described herein.
As shown in Figure 2 A, laminated construction 110 (Fig. 2A is only painted the laminated construction 110 in contact area) is provided, it is each folded
Layer structure 110 includes a conductive layer 111 and an insulating layer 112,112 cross laminates of conductive layer 111 and insulating layer.At this point, providing
First mask PR1 (m=1), mask PR1 include multiple masks area PR1a and multiple opening etch areas PR1b.
As shown in Figure 2 B, the partial electroconductive layer 111 and insulating layer 112 in contact area are replaced.This first time etch step
In (N=1) extended to from a superficial layer with generating using first mask PR1 etched portions conductive layer 111 and insulating layer 112
One etching depth D1 of conductive layer 111, this etching depth D1 are equal to 7 layers of (P=7) laminated construction 110.
Then, as shown in Fig. 2 C~2D, mask PR1 is replaced, then carries out in the 2nd etch step (N=2), using the 2nd
A mask PR2 etched portions conductive layer 111 and insulating layer 112, with generate from a superficial layer extend to conductive layer 111 another
Etching depth D2, this etching depth D2 are equal to 14 layers of (2P=14) laminated construction 110.
Then, as shown in Figure 2 E, 111 He of conductive layer via the combination for using multiple etching masks and in the contact areas
After producing a variety of different removal numbers of plies in insulating layer 112, multiple touchdown area (landing area) R are formed in contact zone
On these conductive layers 111 in domain, and extended to without superposition conductive layer 111, each etching depth above these touchdown areas R
Corresponding touchdown area R.
As shown in Figure 2 E, then, a media filler object 180 is formed on touchdown area R, forming multiple contact openings 180a
Through media filler object 180, each contact openings 180a is connected to corresponding each touchdown area R, is then filled with a conductive material
These contact openings 180a, to form multiple intermediate connectors 140.
Illustrate the manufacturing method of 3-D stacks semiconductor device with embodiment further below.In following embodiment, with 4
The combination (N=4, m=1~4) of etching mask is to producing 12 kinds (O=12) no in the conductive layer and insulating layer in contact area
The same removal number of plies, and 12 subregions with the different laminated construction numbers of plies can be generated.In table 1, " PR " indicates the secondary quarter
Mask is lost using masks area in the subregion, and " X " then indicates the secondary etching mask using opening etch areas in the subregion.
Wherein, the corresponding etching depths of m=1 are 1 layer stacked structure (P=1), and the corresponding etching depths of m=2 are 2 layer stacked structure (P
=1), the corresponding etching depths of m=3 are 3 layer stacked structures (n=3, P=1), and the corresponding etching depths of m=4 are 6 layer laminate knots
Structure (n=6, P=1).
Table 1
As can be seen from Table 1, in some embodiments, when m is greater than or equal to 3, n may include being not equal to 2m-1Integer (such as 3
With 6), and n be less than 2N-1(3 and 6 are respectively less than 23)。
According to some embodiments, using the combination of N number of etching mask with the conductive layer 111 and insulating layer in contact area
Before producing the different removal number of plies of O kinds in 112, (trim) technology can be cut down by photoresist layer collocation to manufacture three-dimensional
Stacked semiconductor device.For example, it is possible to provide a photoresist layer, photoresist layer cover folded in array region and contact area
The part surface of layer structure, then using this photoresist layer as mask etching laminated construction, and cuts down the width of (trim) photoresist layer
Degree, except the photoresist layer that the laminated construction in contact area is exposed to after cutting down, wherein photoresist layer is in contact area
In be towards a first direction cut down width.
For example, in some embodiments, M-1 laminated construction can be etched, in this step using photoresist layer as mask
Each etching in, laminated construction is etched 1Q layers of thickness, and after the 1st time~the M-2 times etching stack structure, all cuts down
(trim) width of photoresist layer is primary, and M is the integer more than or equal to 3, and Q is the integer more than or equal to 1.
It is the manufacturing method for illustrating 3-D stacks semiconductor device above-mentioned with embodiment below.
Fig. 3 A~3F are painted the flow chart of the manufacturing method of the 3-D stacks semiconductor device of another embodiment.The present embodiment
In be to continue to use same or like element numbers with the same or analogous element of previous embodiment, and the phase of same or similar element
Speak on somebody's behalf it is bright please refer to aforementioned, details are not described herein.
As shown in Figure 3A, laminated construction 110 is provided.At this point, 4 layer stacked structures 110 are not all etched, 4 layers of conductive layer 111
With 4 layer insulatings 112 densely cross laminates.
In figure 3 a, photoresist layer 810 is more provided.Photoresist layer 810 covers the part surface of 4 layer stacked structures 110.
In figure 3b, it is mask with photoresist layer 810, etches (etch) laminated construction 110.In this etching, these
The part of the exposure of laminated construction 110 is etched one layer of thickness (Q=1).
In fig. 3 c, the width that (trim) photoresist layer 810 is cut down towards a first direction DR1, with these lamination knots of exposure
Wherein 2 layers of structure 110.
In fig. 3d, these laminated construction 110 are etched for mask with the photoresist layer 810 cut down.In this etching
In, the part of the exposure of these laminated construction 110 is etched 1 layer of thickness.That is, the lamination knot of first layer and the second layer
The a part of thickness by 1 layer of etching simultaneously of structure 110.
In Fig. 3 E~3F, repeats the reduction photoresist layer 810 of earlier figures 3C~3D and etch these laminated construction 110
Step can form 4 stratum after finally replacing photoresist layer 810.
In Fig. 3 A~3F the step of, the secondary laminated construction of 3 (i.e. M-1) 110 is etched altogether.In each etching, laminated construction
110 are etched 1 layer of thickness, and after the 1st time~the 2nd (i.e. M-2) secondary etching stack structure 110, all cut down (trim) photoetching
The width of glue-line 810 is primary, and the M of the present embodiment is 4, Q 1.
Fig. 4 A~4D are painted change schematic diagram of the photoresist layer of embodiment during etching and reduction.The present embodiment
In be to continue to use same or like element numbers with the same or analogous element of previous embodiment, and the phase of same or similar element
Speak on somebody's behalf it is bright please refer to aforementioned, details are not described herein.
As shown in Fig. 4 A~4B, during etching stack structure 110, photoresist layer 910 will be consumed thickness h 1 (about
500 angstroms).As shown in Fig. 4 B~4C, during cutting down the width tx of photoresist layer 910, photoresist layer 910 will be consumed thickness
Spend t1 (about 4000 angstroms).So above-mentioned manufacturing process must take into account photoresist layer 910 in the consumption for etching and cutting down process.
Also, since the reduction of photoresist layer 910 etching is equal tropism (isotropic), the width of consumption is at least
It is two-way (bi-directional).As shown in Figure 4 D, even if the predetermined terrace structure made is to be located at X1Direction, but in X2、
Y1And Y2Direction can all form terrace structure.
Fig. 5 A~5B and Fig. 6 A~6U are painted the flow of the manufacturing method of the 3-D stacks semiconductor device of another embodiment
Figure.With the same or analogous element of previous embodiment be in the present embodiment continue to use same or like element numbers, and it is identical or
The related description of similar components please refers to aforementioned, and details are not described herein.
Fig. 5 A~5B are the section height features illustrated represented by the top view of subsequent figure 6A~6U.Fig. 5 A be one
The top view of laminated construction, Fig. 5 B are painted the diagrammatic cross-section of the hatching 5B-5B ' along Fig. 5 A.In Fig. 5 A, in each sub-regions
The number of plies of the laminated construction 110 of the digital representation subregion indicated, with the conductive layer 111 of laminated construction 110 for the son
The upper surface in region, and as shown in Fig. 5 A~5B, the part surface of mask PR covering laminated construction 110 (has 30 layers and 29 layers
On the subregion of laminated construction 110), and as shown in Figure 5 B, the number of plies of laminated construction 110 is decremented to by 30 layers to the right by left side
1 layer and have hierarchic structure.
As shown in Figure 6A, laminated construction 110 is provided.At this point, 56 layer stacked structures 110 are not all etched.
As shown in Figure 6B, photoresist layer 710 is provided.Photoresist layer 710 covers the part surface of 56 layer stacked structures 110.
In some embodiments, as shown in Figure 6B, another photoresist layer 610 can be also set in the portion of laminated construction 110
Divide on surface, and photoresist layer 610 and photoresist layer 710 are for mirror symmetry relative to central point (C).
As shown in Figure 6 C, it is mask, etching stack structure 110 with photoresist layer 710.In this etching, these laminations
The part of the exposure of structure 110 is etched one layer of thickness (Q=1), that is, remaining 55 layer stacked structures 110.Some are implemented
In example, it is mask with photoresist layer 610 as shown in Figure 6 C, also etches 1 layer of thickness of these laminated construction 110.
As shown in Figure 6 D, the width for cutting down (trim) photoresist layer 710, to expose wherein the 2 of these laminated construction 110
Layer.In embodiment, in scheduled contact area 100B, the width of photoresist layer 710 is cut down towards first direction DR1, in pre-
In fixed virtual region 100C, the width of photoresist layer 710 is cut down towards third direction DR3, and third direction DR3 is different from first
Direction DR1.In some embodiments, in the step of cutting down the width of photoresist layer 710, also photoresist layer 610 is cut down simultaneously
The opposite direction of width, width towards the first direction DR1 of photoresist layer 610 is cut down.
As illustrated in fig. 6e, these laminated construction 110 are etched for mask with the photoresist layer 710 cut down.In this etching
In, the part of the exposure of these laminated construction 110 is etched 1 layer of thickness.That is, first layer and the second layer (script 55
Layer and 56 layers of part) laminated construction 110 a part of thickness by 1 layer of etching simultaneously.
In some embodiments, top view shown in Fig. 6 E is please referred to, the photoresist layer 610 to have cut down also is carved for mask
Lose 1 layer of thickness of these laminated construction 110.
In Fig. 6 F~6M, repeats the reduction photoresist layer 710 of earlier figures 6D~6E and etch these laminated construction 110
Step can form 7 stratum.As shown in Fig. 6 M, it is weight to cut down photoresist layer 710 and the step of etching these laminated construction 110
Again after the laminated construction 110 in a little laminated construction 110 and virtual region 100C in contact area 100B is exposed to reduction
Photoresist layer 710 except.
In Fig. 6 A~6M the step of, the secondary laminated construction of 6 (i.e. M-1) 110 is etched altogether.In each etching, laminated construction
110 are etched 1 layer of thickness, and after the 1st time~the 5th (i.e. M-2) secondary etching stack structure 110, all cut down photoresist layer 710
Width it is primary, the M of the present embodiment is 7, Q 1.
Then, as shown in fig. 6n, first mask PR1 (m=1) be provided, mask PR1 include multiple masks area PR1a and
Multiple opening etch areas PR1b.
As shown in Fig. 6 O, the partial electroconductive layer and insulating layer in scheduled contact area 100B are replaced.In embodiment, this step
Suddenly the partial electroconductive layer and insulation for not being photo-etched that glue-line and mask are covered other than scheduled contact area 100B are also replaced
Layer.It carries out in this first time etch step (N=1), using first mask PR1 etched portions conductive layer and insulating layer, with production
The raw etching depth that conductive layer is extended to from a superficial layer, this etching depth are equal to 7 layers of (P=7) laminated construction 110.
Then, as shown in Fig. 6 P~6Q, mask PR1 is replaced, then carries out in the 2nd etch step (N=2), using the 2nd
A mask PR2 etched portions conductive layer and insulating layer, to generate another etching depth for extending to conductive layer from a superficial layer,
This etching depth is equal to 14 layers of (2P=14) laminated construction 110.Mask PR2 includes that multiple masks area PR2a and multiple openings are carved
Lose region PR2b.
Then, as shown in Fig. 6 R~6S, mask PR2 is replaced, then carries out in the 3rd etch step (N=3), using the 3rd
A mask PR3 etched portions conductive layer and insulating layer, to generate another etching depth for extending to conductive layer from a superficial layer,
This etching depth is equal to 28 layers of (4P=28) laminated construction 110.Mask PR3 includes masks area PR3a and opening etch areas
PR3b.As shown in Fig. 6 N~6S, in embodiment, 3 mask PR1, PR2 and PR3 (N=3) are adjacent to photoresist layer 710.
Then, as shown in Fig. 6 T, photoresist layer and mask are replaced.So far, via the group for using 3 (N=3) a etching masks
Close and produced in conductive layer and insulating layer in the contact areas 8 (O=8) plant the different removal number of plies (0 layer, 7 layers, 14 layers,
21 layers, 28 layers, 35 layers, 42 layers and 49 layers) after, collocation is formed by 7 stratum using photoresist layer, shares 56 touchdown areas
It is respectively formed on these different conductive layers in contact area, and without superposition conductive layer above these touchdown areas R, it is each
Etching depth extends to corresponding touchdown area.
As shown in Fig. 6 T, removal is planted using 8 (O=8) produced in contact area 100B that are combined in of N number of etching mask
The number of plies is incremented by towards second direction DR2, and first direction DR1 is different from second direction DR2.
Then, Fig. 2 E are please also refer to, media filler object can be formed on 56 touchdown areas, form 56 contact openings
Through media filler object, each contact openings are connected to corresponding each touchdown area, then fill these contacts with a conductive material
Opening, to form 56 intermediate connectors (not being illustrated in figure) (P × O=7 × 8=56).In embodiment, intermediate connector edge
First direction DR1 and the arrangement of second direction DR2 arrays, first direction DR1 is substantially perpendicular to second direction DR2.
As shown in Fig. 6 U, an at least word-line decoder 120 is set, word-line decoder 120 is connected to array region 100A, and
Word-line decoder 120 and virtual region 100C are located at the adjacent both sides of array region 100A.
In embodiment, as shown in Fig. 6 A~6U, photoresist layer is used to be cut down the etching direction of (trim) technology as
One direction DR1, and it is second direction DR2 to produce a variety of etching directions for removing the number of plies using the combination of N number of etching mask, this
Two directions are perpendicular to one another, therefore can be minimized the area of virtual region 100C, and can reduce process costs.
Fig. 7 A~7T are painted the flow chart of the manufacturing method of the 3-D stacks semiconductor device of another embodiment.The present embodiment
In be to continue to use same or like element numbers with the same or analogous element of previous embodiment, and the phase of same or similar element
Speak on somebody's behalf it is bright please refer to aforementioned, details are not described herein.It is noted that the present embodiment is only painted the laminated construction in contact area
110。
As shown in Figure 7 A, laminated construction 110 is provided.At this point, 56 layer stacked structures 110 are not all etched.
As shown in Figure 7 B, photoresist layer 710 is provided.Photoresist layer 710 covers the part surface of 56 layer stacked structures 110.
As seen in figure 7 c, it is mask, etching stack structure 110 with photoresist layer 710.In this etching, these laminations
The part of the exposure of structure 110 is etched 8 layers of thickness (Q=8), that is, remaining 48 layer stacked structures 110.
As illustrated in fig. 7d, the width for cutting down (trim) photoresist layer 710, to expose wherein 2 layers of these laminated construction 110
(the 48th layer and the 56th layer).In embodiment, in scheduled contact area, the width of photoresist layer 710 is towards first direction DR1
It cuts down.In fact, the reduction etching of photoresist layer 910 is equal tropism (isotropic), therefore in scheduled virtual region
The width of (not being painted), photoresist layer 710 is cut down towards third direction DR3.
As seen in figure 7e, these laminated construction 110 are etched for mask with the photoresist layer 710 cut down.In this etching
In, the part of the exposure of these laminated construction 110 is etched 8 layers of thickness.That is, first layer and the second layer (script 48
Layer and 56 layers of part) laminated construction 110 a part of thickness by 8 layers of etching simultaneously.
In Fig. 7 F~7M, repeats the reduction photoresist layer 710 of earlier figures 7D~7E and etch these laminated construction 110
Step can form 7 stratum.As shown in Fig. 7 M, it is weight to cut down photoresist layer 710 and the step of etching these laminated construction 110
Except the multiple photoresist layer 710 being exposed to after cutting down until a little laminated construction 110 in contact area.
In Fig. 7 A~7M the step of, the secondary laminated construction of 6 (i.e. M-1) 110 is etched altogether.In each etching, laminated construction
110 are etched 8 layers of thickness, and after the 1st time~the 5th (i.e. M-2) secondary etching stack structure 110, all cut down photoresist layer 710
Width it is primary, the M of the present embodiment is 7, Q 8.
Then, as shown in figure 7n, first mask PR1 (m=1) be provided, mask PR1 include multiple masks area PR1a and
Multiple opening etch areas PR1b.
As shown in figure 7o, the partial electroconductive layer 111 and insulating layer 112 in scheduled contact area are replaced.Carry out this first
In secondary etch step (N=1), using first mask PR1 etched portions conductive layer and insulating layer, prolonged from a superficial layer with generating
An etching depth of conductive layer is extended to, this etching depth is equal to 1 layer of (P=1) laminated construction 110.
Then, as shown in Fig. 7 P~7Q, mask PR1 is replaced, then carries out in the 2nd etch step (N=2), using the 2nd
A mask PR2 etched portions conductive layer and insulating layer, to generate another etching depth for extending to conductive layer from a superficial layer,
This etching depth is equal to 2 layers of (2P=2) laminated construction 110.Mask PR2 includes multiple masks area PR2a and multiple openings etching
Region PR2b.
Then, as shown in Fig. 7 R~7S, mask PR2 is replaced, then carries out in the 3rd etch step (N=3), using the 3rd
A mask PR3 etched portions conductive layer and insulating layer, to generate another etching depth for extending to conductive layer from a superficial layer,
This etching depth is equal to 4 layers of (4P=4) laminated construction 110.Mask PR3 includes multiple masks area PR3a and multiple openings etching
Region PR3b.
Then, as shown in figure 7t, photoresist layer and mask are replaced.So far, via the group for using 3 (N=3) a etching masks
Close and produced in conductive layer and insulating layer in the contact areas 8 (O=8) plant the different removal number of plies (0 layer, 1 layer, 2 layers, 3
Layer, 4 layers, 5 layers, 6 layers and 7 layers) after, collocation using photoresist layer is formed by 7 stratum, shares 56 touchdown areas and distinguishes shapes
At not having superposition conductive layer on these different conductive layers in contact area, and above these touchdown areas, each etching is deeply
Degree extends to corresponding touchdown area.
As shown in figure 7t, removal is planted using 8 (O=8) produced in contact area 100B that are combined in of N number of etching mask
The number of plies is incremented by towards second direction DR2, and in the present embodiment, first direction DR1 is equal to second direction DR2.
Then, it is similar to embodiment above-mentioned, intermediate connector can be formed on the touchdown area of each conductive layer, and is borrowed
This forms the 3-D stacks semiconductor device of the present invention.
In conclusion although the present invention is disclosed as above with embodiment, however, it is not to limit the invention.This field skill
Art personnel without departing from the spirit and scope of the present invention, when various modification and variation can be made.Therefore, protection model of the invention
It encloses subject to ought being defined depending on appended claims.
Claims (10)
1. a kind of manufacturing method of 3-D stacks semiconductor device, which is characterized in that the 3-D stacks semiconductor device includes more
Layer stacked structure simultaneously has a burst of column region and a contact area, and respectively the laminated construction includes a conductive layer and an insulating layer, this
A little conductive layers and these insulating layer cross laminates, this method in a contact area forming multiple intermediate connectors
(interlayer connector), respectively the intermediate connector be connected to the corresponding respectively conductive layer, this method and include：
Using the combination of N number of etching mask to produce O kinds in these conductive layers and these insulating layers in the contact area
The different removal numbers of plies, to form multiple touchdown areas (landing area) on these conductive layers in the contact area,
These conductive layers are not superimposed above these touchdown areas, respectively the mask includes multiple masks areas and multiple opening etched areas
Domain, N are integer more than or equal to 2, and O is the integer more than 2,2N-1<O≦2N, m is the serial number for these masks,
So that the m of a mask therein is equal to 1, the m of another mask is equal to 2, until m is equal to N；And
These conductive layers of part and these insulating layers in the contact area are replaced, including：These are used with selected sequence
These conductive layers of part in the mask etching contact area and these insulating layer n times extend to this to generate from a superficial layer
Multiple etching depths of a little conductive layers, respectively the etching depth extend to the corresponding touchdown area, wherein
When m=1, the corresponding etching depth is equal to the 1P layers of laminated construction；And
When m=2, the corresponding etching depth is equal to the 2P layers of laminated construction, and wherein P is the integer more than or equal to 1.
2. the manufacturing method of 3-D stacks semiconductor device according to claim 1, which is characterized in that m is greater than or equal to 3
When, the corresponding etching depth is equal to the nP layers of laminated construction, and n is the integer more than or equal to 3, and n includes being not equal to 2m-1
Integer, and n be less than or equal to 2N-1。
3. the manufacturing method of 3-D stacks semiconductor device according to claim 1, which is characterized in that use N number of etching
The combination of mask with produced in these conductive layers and these insulating layers in the contact area the different removal number of plies of O kinds it
Before, it further includes：
A photoresist layer is provided, which covers the part of these laminated construction in the array region and the contact area
Surface；And
Using the photoresist layer as these laminated construction of mask etching, and the width of (trim) photoresist layer is cut down, until this connects
It touches except the photoresist layer that these laminated construction in region are exposed to after cutting down, wherein the photoresist layer is in the contact area
In be towards a first direction cut down width.
4. the manufacturing method of 3-D stacks semiconductor device according to claim 3, which is characterized in that these intermediate connections
The number of part be P × O.
5. the manufacturing method of 3-D stacks semiconductor device according to claim 3, which is characterized in that use N number of etching
The O kinds removal number of plies produced in the contact area that is combined in of mask is incremented by towards a second direction, and the first direction is different
In the second direction.
6. the manufacturing method of 3-D stacks semiconductor device according to claim 3, which is characterized in that with the photoresist layer
For mask etching, these laminated construction include：
Using the photoresist layer as mask, M-1 these laminated construction is etched, in each etching of this step, these lamination knots
Structure is etched 1Q layers of thickness, and after etching these laminated construction at the 1st time~the M-2 times, all cuts down (trim) photoresist
The width of layer is primary, and M is the integer more than or equal to 3, and Q is the integer more than or equal to 1.
7. the manufacturing method of 3-D stacks semiconductor device according to claim 3, which is characterized in that N number of mask is equal
It is adjacent to the photoresist layer.
8. a kind of 3-D stacks semiconductor device, which is characterized in that including：
Multi-layer laminate structure, respectively the laminated construction includes a conductive layer and an insulating layer, these conductive layers and these insulating layers are handed over
Wrong lamination, wherein these laminated construction are a burst of column region to form the 3-D stacks semiconductor device, a contact area and one
Virtual region, the virtual region abut the array region and the contact area and positioned at the same of the array region and the contact area
Side；And
Multiple intermediate connectors (interlayer connector), are formed in the contact area, and respectively the intermediate connector connects
It is connected to corresponding respectively conductive layer.
9. 3-D stacks semiconductor device according to claim 8, which is characterized in that the array region and the contact area
Between there is a difference in height, this is highly worse than the interface of the array region and the contact area along far from the virtual region
Successively decrease in direction.
10. 3-D stacks semiconductor device according to claim 9, which is characterized in that the difference of height is with the P layers of lamination
Structure is successively decreased for unit, and P is the integer more than or equal to 1.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120306089A1 (en) * | 2011-06-02 | 2012-12-06 | Micron Technology, Inc. | Apparatuses including stair-step structures and methods of forming the same |
| CN103972151A (en) * | 2013-01-31 | 2014-08-06 | 旺宏电子股份有限公司 | Formation method for interlayer connectors connecting conducting layers of laminated structure |
| CN106024786A (en) * | 2015-03-31 | 2016-10-12 | 三星电子株式会社 | Three-dimensional semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120306089A1 (en) * | 2011-06-02 | 2012-12-06 | Micron Technology, Inc. | Apparatuses including stair-step structures and methods of forming the same |
| CN103972151A (en) * | 2013-01-31 | 2014-08-06 | 旺宏电子股份有限公司 | Formation method for interlayer connectors connecting conducting layers of laminated structure |
| CN106024786A (en) * | 2015-03-31 | 2016-10-12 | 三星电子株式会社 | Three-dimensional semiconductor device |
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