CN103928395B - Three-dimensional laminated semiconductor device and manufacturing method thereof - Google Patents
Three-dimensional laminated semiconductor device and manufacturing method thereof Download PDFInfo
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- CN103928395B CN103928395B CN201310015893.2A CN201310015893A CN103928395B CN 103928395 B CN103928395 B CN 103928395B CN 201310015893 A CN201310015893 A CN 201310015893A CN 103928395 B CN103928395 B CN 103928395B
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Abstract
The invention discloses a three-dimensional laminated semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps of providing N layers of laminated structures, wherein each laminated structure comprises a conducting layer and an insulation layer; providing a first photoresist layer; etching the laminated structures for P-1 times with the first photoresist layer serving as a mask; providing a second photoresist layer; etching the laminated structures for Q-1 times with the second photoresist layer serving as a mask; decreasing the width of the first photoresist layer in a first direction; decreasing the width of the second photoresist layer in a second direction, wherein the first direction is different from the second direction, a plurality of connection points are arranged in the first direction and the second direction in an array mode, and an acute angle is formed by the first direction and the second direction.
Description
Technical field
The invention relates to a kind of semiconductor device and its manufacture method, and in particular to a kind of 3-D stacks half
Conductor device and its manufacture method.
Background technology
With the development of semiconductor technology, various semiconductor element is constantly weeded out the old and bring forth the new.Semiconductor element can be through suitable
Various electrical functionalities can be realized after local arrangement.Now various electronic products have all widely applied various semiconductor elements.
Wherein as electronic product is pursued under the trend of " light, thin, short, little ", how by the volume-diminished of semiconductor element,
Or under fixed volume increase circuit closeness, it has also become one important research developing direction of semiconductor industry.
The content of the invention
The invention relates to a kind of 3-D stacks semiconductor device and its manufacture method.
According to an aspect of the invention, it is proposed that a kind of manufacture method of 3-D stacks semiconductor device, 3-D stacks are partly led
The manufacture method of body device is comprised the following steps：N shell laminated construction is provided；Each laminated construction includes a conductive layer and an insulation
Layer；This little conductive layer and these insulating barrier cross laminates；N≤P × Q, N, P, Q are positive integer；One first photoresist layer is provided；The
One photoresist layer covers the part surface of this little laminated construction；With the first photoresist layer as mask, this is a little for etching (etch) P-1 time
Laminated construction；In each etching of this step, this little laminated construction is etched one layer of thickness, and at the 1st time～the P-2 time
After etching this little laminated construction, the width of (trim) first photoresist layer is all cut down once；Remove the first photoresist layer；There is provided one
Second photoresist layer；Second photoresist layer covers the part surface of this little laminated construction；With the second photoresist layer as mask, etching
Q-1 this little laminated construction；In each etching of this step, this little laminated construction is etched the thickness of P layers, and at the 1st time
Etch after this little laminated construction for～the Q-2 time, all cut down the width of the second photoresist layer once；Remove the second photoresist layer；If
N bar wires are put, respectively the wire is electrically connected at a contact of the respectively conductive layer；First photoresist layer is cut down towards a first direction
Width, the second photoresist layer is to cut down width towards a second direction；First direction is different from second direction；Multiple contacts are along
One direction and second direction array are arranged；The angle of first direction and second direction is acute angle.
According to another aspect of the invention, it is proposed that a kind of 3-D stacks semiconductor device, 3-D stacks semiconductor device bag
Include N shell laminated construction and N bar wires；Each laminated construction includes a conductive layer and an insulating barrier；N is positive integer；This little conduction
Layer and this little insulating barrier cross laminates；Each wire is electrically connected with a contact of each conductive layer；Wherein this little contact are along one
First direction is arranged in a P stratum step structure with the gap of monolayer, and this little contact is along a second direction with the gap of P layers
It is arranged in a Q stratum step structure；N≦P×Q；This little contact is along a first direction and second direction array is arranged；First
The angle of direction and second direction is acute angle.
It is that the above of the present invention can be become apparent, various good embodiments cited below particularly, and coordinate institute's accompanying drawings,
It is described in detail below：
Description of the drawings
Fig. 1 illustrates the schematic diagram of 3-D stacks semiconductor device.
Fig. 2A to Fig. 2 R illustrates the flow chart of the manufacture method of 3-D stacks semiconductor device.
Fig. 3 A to Fig. 3 B illustrate the flow chart of the manufacture method of 3-D stacks semiconductor device.
Fig. 4 A to Fig. 4 C illustrate change schematic diagram of the photoresist layer during etching and reduction.
Fig. 5 illustrates the configuration figure that wire is connected to the contact of conductive layer with wire.
Fig. 6 illustrates the configuration figure that wire is connected to the contact of conductive layer with wire.
Fig. 7 to Fig. 8 illustrates contact with the distance on border with the variation relation figure cut down.
【Main element symbol description】
100、200：3-D stacks semiconductor device
110、210、310：Laminated construction
111、211、411、511：Conductive layer
111a、411a、511a、611a：Contact
112、212：Insulating barrier
120：Stop-layer
140、440、540：Wire
810：First photoresist layer
820：Second photoresist layer
610、910：Photoresist layer
830：3rd photoresist layer
C11、C41、C51：First direction
C12、C42、C52：Second direction
D1、D2、D3：Distance
dx：The margin of error
h1、t1：Thickness
p：Spacing
tx、tx’：Width
θ1、θ2：Angle
Specific embodiment
The following is the various embodiments of proposition to be described in detail, embodiment can't be limited only to illustrate as example
The scope to be protected of the present invention.Additionally, the schema in embodiment is to omit portion of element, it is special with the technology for clearly showing that the present invention
Point.
Fig. 1 is refer to, it illustrates the schematic diagram of 3-D stacks semiconductor device 100.3-D stacks semiconductor device 100 is wrapped
Include N shell laminated construction 110 and N bars wire 140.Each laminated construction 110 includes a conductive layer 111 and an insulating barrier 112.N is
Positive integer, e.g. 18.Each conductive layer 111 has a stop-layer 120.This little wire 140 passes through these stop-layers 120, with
Each transmit the signal of N shell conductive layer 111.Through the design of 3-D stacks semiconductor device 100, N shell conductive layer 111 can be made
Densely lamination, and it is densely aligned wire 140.
Fig. 2A to Fig. 2 R is refer to, it illustrates the flow chart of the manufacture method of 3-D stacks semiconductor device 100.It is real one
In applying example, can arrange in pairs or groups multidirectional reduction (trim) technology to form 3-D stacks semiconductor device through multilevel resist layer
100.Fig. 2A to Fig. 2 R is the reduction technology through two-layer photoresist layer and both direction completing the three of N shell laminated construction 110
Dimension stacked semiconductor device 100.
As shown in Fig. 2A～Fig. 2 E, it carries out technique through the first photoresist layer 810, to form the stepped knot of P stratum
Structure.P is positive integer, e.g. 3.As shown in Fig. 2 F～Fig. 2 P, it carries out technique through the second photoresist layer 820, to form Q
Stratum's step structure.Q is positive integer, e.g. 6.N≦P×Q.E.g. 18≤3 × 6.Following N, P, Q be directly with
18th, explain as a example by 3,6.
In fig. 2, there is provided laminated construction 110.Now, 18 layer stacked structures 110 are not all etched.18 layers of conductive layer 111
With 18 layer insulatings 112 densely cross laminates.
In fig. 2, the first photoresist layer 810 is more provided.First photoresist layer 810 covers the portion of 18 layer stacked structures 110
Divide surface.
In fig. 2b, with the first photoresist layer 810 as mask, (etch) laminated construction 110 is etched.In this etching,
The exposed part of this little laminated construction 110 is etched one layer of thickness.
In fig. 2 c, the width of (trim) first photoresist layer 810 is cut down towards a first direction C11, it is a little folded to expose this
Wherein 2 layers of Rotating fields 110.
In figure 2d, with the first photoresist layer 810 for having cut down as mask, this little laminated construction 110 is etched.At this quarter
In erosion, the exposed part of this little laminated construction 110 is etched 1 layer of thickness.That is, the lamination of ground floor and the second layer
The some of structure 110 is by the thickness of 1 layer of etching simultaneously.
In Fig. 2 E, the first photoresist layer 810 is removed, to form 3 stratum.
In the step of Fig. 2A～Fig. 2 E, 2 (i.e. P-1) secondary laminated construction 110 are etched altogether.In etching every time, this is a little folded
The exposed part of Rotating fields 110 is etched one layer of thickness, and after the 1st (i.e. P-2) secondary etching this little laminated construction 110,
Towards first direction C11 cut down the first photoresist layer 810 width once.It is to be with 3 stratum in the embodiment of Fig. 2A～Fig. 2 E
Example is explained.It is, with the first photoresist layer 810 as mask, to etch P-1 this little laminated construction 110 if extending to P stratum.
In every time etching, this little laminated construction 110 is etched one layer of thickness, and ties in the 1st time～the P-2 time etching this little lamination
After structure 110, all towards first direction C11 cut down the first photoresist layer 810 width once.
Then, in fig. 2f, there is provided the second photoresist layer 820.Second photoresist layer 820 covers this little laminated construction 110
Portion.
In fig 2g, with the second photoresist layer 820 as mask, this little laminated construction 110 is etched.In this etching, this
The exposed part of a little laminated construction 110 is etched 3 layers of thickness.That is, one of the 1st～3 layer of laminated construction 110
Part is by the thickness of 3 layers of etching simultaneously.
In Fig. 2 H, the width of the second photoresist layer 820 is cut down towards second direction C12, to expose this little laminated construction 110
Wherein 6 layers.
In Fig. 2 I, with the second photoresist layer 820 for having cut down as mask, this little laminated construction 110 is etched.At this quarter
In erosion, the exposed part of this little laminated construction 110 is etched 3 layers of thickness.That is, the 1st～6 layer of laminated construction
110 some is by the thickness of 3 layers of etching simultaneously.
In Fig. 2 J, the width of the second photoresist layer 820 is cut down towards second direction C12, to expose this little laminated construction 110
Wherein 9 layers.
In Fig. 2 K, with the second photoresist layer 820 for having cut down as mask, this little laminated construction 110 is etched.At this quarter
In erosion, the exposed part of this little laminated construction 110 is etched 3 layers of thickness.That is, the 1st～9 layer of laminated construction
110 some is by the thickness of 3 layers of etching simultaneously.
In Fig. 2 L, the width of the second photoresist layer 820 is cut down towards second direction C12, to expose this little laminated construction 110
Wherein 12 layers.
In Fig. 2 M, with the second photoresist layer 820 for having cut down as mask, this little laminated construction 110 is etched.At this quarter
In erosion, the exposed part of this little laminated construction 110 is etched 3 layers of thickness.That is, the 1st～12 layer of laminated construction
110 some is by the thickness of 3 layers of etching simultaneously.
In Fig. 2 N, the width of the second photoresist layer 820 is cut down towards second direction C12, to expose this little laminated construction 110
Wherein 15 layers.
In Fig. 2 O, with the second photoresist layer 820 for having cut down as mask, this little laminated construction 110 is etched.At this quarter
In erosion, the exposed part of this little laminated construction 110 is etched 3 layers of thickness.That is, the 1st～15 layer of laminated construction
110 some is by the thickness of 3 layers of etching simultaneously.
In Fig. 2 P, the second photoresist layer 820 is removed, to form 18 stratum.
In the step of Fig. 2 F～Fig. 2 P, 5 (i.e. Q-1) secondary laminated construction 110 are etched altogether.In etching every time, this is a little folded
The exposed part of Rotating fields 110 is etched the thickness of 3 (i.e. P) layers, and in the 1st～4 (i.e. 1～Q-2) secondary etching this little lamination
After structure 110, towards second direction C12 cut down the second photoresist layer 820 width once.In the embodiment of Fig. 2 E～Fig. 2 P,
It is to explain by taking 6 stratum as an example.If extending to Q stratum, be with the second photoresist layer 820 as mask, etching Q-1 time this fold a bit
Rotating fields 110.In each etching of this step, this little laminated construction 110 is etched the thickness of P layers, and in the 1st time～Q-
After etching this little laminated construction 110 for 2 times, all towards second direction C12 cut down the second photoresist layer 820 width once.
In Fig. 2 Q, stop-layer is formed in the exposed part of this little laminated construction 110.
In Fig. 2 R, stop-layer 120 is formed on the conductive layer 111 that each laminated construction 110 is exposed, and with wire
140 pass through this little stop-layer 120, to be connected to conductive layer 111.
Thus, you can intensive 18 stratum 3-D stacks semiconductor device 100 is formed in quite narrow and small volume.
Wherein, in Fig. 2A～Fig. 2 E, the first photoresist layer 810 is to cut down width towards first direction C11；In Fig. 2 F～Fig. 2 P, the
Two photoresist layers 820 are to cut down width towards second direction C12.First direction C11 is different from second direction C12, and makes etched
C11 and second direction C12 several layers of ladder can be all formed in a first direction in journey, and be woven into matrix form hierarchic structure.
In the embodiment of Fig. 2A to Fig. 2 R, first direction C11 is to be essentially right angle with the angle of second direction C12
As a example by explain.In one embodiment, first direction C11 and the angle of second direction C12 can also be acute angles.
In the present embodiment, 3-D stacks semiconductor device 100 have N shell laminated construction 110, in a first direction C11 with
The gap of monolayer is arranged in P stratum step structure, and the stepped knot of Q stratum is arranged in the gap of P layers in second direction C12
Structure.N, P, Q of the present embodiment is to explain as a example by 18,3,6 respectively.In one embodiment, N, P, Q can also be 18,6,3 or
18th, 9,2, as long as P, Q all may be used for the factor of N.
Above-described embodiment is to form 3-D stacks semiconductor device 100 with two modules (P stratum and Q stratum),
In another embodiment, it is also possible to which three modules (e.g. P stratum, Q stratum and R stratum) are forming 3-D stacks half
Conductor device 200.Fig. 3 A to Fig. 3 B are refer to, it illustrates the flow chart of the manufacture method of 3-D stacks semiconductor device 200.
In Fig. 3 A, P stratum step structure can be formed in the way of through similar Fig. 2A～Fig. 2 R and Q stratum step structure is constituted
One P × Q stratum step structure (e.g. 3 × 6 stratum's step structures).
In figure 3b, there is provided one the 3rd photoresist layer 830.3rd photoresist layer 830 covers the laminated construction 210 of part.
Each laminated construction 210 includes conductive layer 211 and insulating barrier 212.Then.With the 3rd photoresist layer 830 as mask, etch 1 time
Laminated construction 210.The thickness of each 210 18 layers of etching stack structure.It is to be with 2 stratum in the embodiment of Fig. 3 A to Fig. 3 B
Example is explained.If extending to R stratum, with the 3rd photoresist layer 830 as mask, R-1 laminated construction 210 is etched, carved every time
The thickness of erosion laminated construction 210P × Q layers, and after the 1st time～the R-2 time etching stack structure 210, all cut down the 3rd photoetching
The width of glue-line 830 is once.
If that is, the 3-D stacks semiconductor device of N stratum to be formed, can pass through P stratum, Q stratum, R stratum
Complete, P × Q stratum step structure is arranged in one P × Q × R ranks with the gap of P × Q layers along a first direction in three stages
Layer step structure.Wherein N, P, Q, R are the factor that positive integer, N≤P × Q × R, and P, Q, R are N.
Similarly, if sequentially promoting, the 3-D stacks semiconductor device of N stratum can through P stratum, Q stratum, R stratum,
The stage of S stratum etc. four completes.P × Q × R stratum step structure is arranged in along second direction with the gap of P × Q × R layers
One P × Q × R × S stratum step structure.Wherein N, P, Q, R, S are that positive integer, N≤P × Q × R × S, and P, Q, R, S are N's
The factor.3-D stacks semiconductor device is completed after P stratum, Q stratum, R stratum, can provide one the 4th photoresist layer, and the 4th
Photoresist layer covers the laminated construction of part.Again with the 4th photoresist layer as mask, S-1 laminated construction is etched, every time etching
Laminated construction P × Q × R layers, and after etching the laminated construction at the 1st time～the S-2 time, all cut down the width of the 4th photoresist layer
Degree is once.
According to similar mode, you can continue popularization and more than the stage complete 3-D stacks semiconductor device with five.
Fig. 4 A to Fig. 4 C are refer to, it illustrates change schematic diagram of the photoresist layer 910 during etching and reduction.As schemed
Shown in 4A～Fig. 4 B, during etching stack structure 310, photoresist layer 910 will be consumed thickness h 1 (about).Such as
Shown in Fig. 4 B～Fig. 4 C, during the width tx for cutting down photoresist layer 910, photoresist layer 910 will be consumed thickness t1 (about).So above-mentioned manufacture process must account for photoresist layer 910 in the consumption for etching and cutting down process.
By taking table 1 as an example, when N is 36, when the 3-D stacks semiconductor device with 36 stratum is formed using a stage, cut
Subtract number of times for 34 times, the etching number of plies is 35 layers, therefore photoresist layer total flow is
Table 1
By taking table 2A as an example, when N is 36, when the 3-D stacks semiconductor device with 36 stratum is formed using the two-stage,
First stage can be combined using various with the P of second stage and Q, e.g. three kinds of combinations such as numbering 2-1,2-2,2-3.Such as
Shown in table 2B, when the first stage adopts 6 stratum using 6 stratum and second stage, it is possible to obtain relatively low photoresist layer is total
Consumption.
Because the second stage etching number of plies is more, the photoresist layer consumption caused by second stage single etch can be more than the
The photoresist layer consumption of one stage single etch.Consider to be cut down per the stage photoresist consume total amount caused with etching, Q≤P
It is preferably to select.For example；Numbering 2-1 of table 2B, first stage photoresist demandAnd second stage photoresist demandIt is very high.Additionally, the too thick shortcoming of photoresist：1st, optics esolving degree is reduced；2nd, photoresist thickness has in technique
Certain limit.Therefore numbering 2-1 is not preferred plan.Numbering 2-2, numbering 2-3 are preferable selection schemes.
Table 2A
Table 2B
By taking table 3A as an example, when N is 36, when the 3-D stacks semiconductor device with 36 stratum is formed using three stages,
First stage, second stage and P, Q of phase III and R can be combined using various, e.g. numbering 3-1,3-2,3-3,
Four kinds of combinations such as 3-4.As shown in table 3B, the first stage is using 3 stratum, second stage are using 3 stratum and the phase III adopts
Relatively low photoresist layer total flow can be obtained with 4 stratum.
The reason for being normally introduced into the new stage be photoresist thickness encounter the limit, cut down number of times excessively cause alignment doubt or
There is the doubt that design rule (Design Rule) amplifies.By taking photoresist thickness as an example, if being per stage thickness limitThat table 2B does not have selectable scheme；And table 3B also only has numbering 3-2 to use with numbering 3-4.
Furthermore, it is understood that the photoresist layer consumption caused by phase III single etch can be carved more than second stage single
The photoresist layer consumption of erosion.Consider to be cut down per the stage photoresist consume total amount caused with etching, R≤Q≤P is preferably choosing
Select.
The rest may be inferred, and when further using the S stratum of fourth stage, S≤R≤Q≤P is preferably to select.
Table 3A
Table 3B
Fig. 5 is refer to, it illustrates the configuration figure that wire 440 is connected to the contact 411a of conductive layer 411 with wire 440.On
State 3-D stacks semiconductor device can densely lamination plurality of conductive layers 411, wire 440 is connected to the contact of conductive layer 411
411a is also densely aligned.In the fabrication process, when photoresist layer is cut down towards first direction C41 and second direction C42, contact
411a also C41 and second direction C42 array will be arranged along a first direction.If the folder of first direction C41 and second direction C42
Angle θ 1 is essentially right angle, and when wire 440 is configured, wire 440 can be with l-shaped, with this little wire 440 that stagger.
Fig. 6 is refer to, it illustrates the configuration figure that wire 540 is connected to the contact 511a of conductive layer 511 with wire 540.On
State 3-D stacks semiconductor device can densely lamination plurality of conductive layers 511, wire 540 is connected to the contact of conductive layer 511
511a is also densely.In the fabrication process, when photoresist layer is cut down towards first direction C51 and second direction C52, contact 511a
Also C51 and second direction C52 array will arrange along a first direction.If the angle theta 2 of first direction C51 and second direction C52
For acute angle, when wire 540 is configured, wire 540 without l-shaped, can since then a little contact 511a in the same direction run-in index is straight
Line extends, you can stagger this little wire 540.
Additionally, when the angle theta 2 of first direction C51 and second direction C52 is acute angle, photoresist layer needs to cut down originally
Width tx also can be changed into width tx '.Wherein width tx ' is sin (θ 2) times of width tx.
Additionally, refer to Fig. 7 to Fig. 8, it illustrates closing with the change cut down apart from D1, D2, D3 for contact 611a and border
System's figure.Spacing p of two neighboring contact 611a is fixation.As shown in fig. 7, in an ideal case, the width that each photoresist is cut down
Degree tx all keeps fixed.Therefore, the contact 611a of Fig. 7 and border can be fixed on p/2 apart from D1, D2, D3.
As shown in figure 8, cut down there may be margin of error dx every time.Therefore, the contact 611a of Fig. 8 and border apart from D2
P/2-dx will be changed into, contact 611a will be changed into p/2-2dx with border apart from D3.The rest may be inferred, and N shell laminated construction 110 does
After the step of cutting down photoresist layer N-1 time, contact 611a will be reduced into p/2- (N-1) * dx with the distance on border.Connect to allow
Point 611a will not be contracted to zero with the distance on border, and spacing p have to be larger than 2 (N-1) * dx.
In sum, although the present invention is disclosed above with various embodiments, so it is not limited to the present invention.This
Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made
With retouching.Therefore, protection scope of the present invention is when depending on being defined that appended claims scope is defined.
Claims (8)
1. a kind of manufacture method of 3-D stacks semiconductor device, including：
N shell laminated construction is provided, respectively the laminated construction includes a conductive layer and an insulating barrier, these conductive layers and these insulating barriers
Cross laminates, N≤P × Q, N, P, Q are positive integer；
One first photoresist layer is provided, first photoresist layer covers the part surface of these laminated construction；
With first photoresist layer as mask, (etch) P-1 these laminated construction is etched, in each etching of this step,
These laminated construction are etched one layer of thickness, and after etching these laminated construction at the 1st time～the P-2 time, all cut down
(trim) width of first photoresist layer is once；
Remove first photoresist layer；
One second photoresist layer is provided, second photoresist layer covers the part surface of these laminated construction；
With second photoresist layer as mask, Q-1 these laminated construction is etched, in each etching of this step, these are folded
Rotating fields are etched the thickness of P layers, and after etching these laminated construction at the 1st time～the Q-2 time, all cut down second photoresist
The width of layer is once；
Remove second photoresist layer；And
N bar wires are set, and respectively the wire is electrically connected at a contact of the respectively conductive layer；
Wherein first photoresist layer is to cut down width towards a first direction, and second photoresist layer is cut down towards a second direction
Width, the first direction is different from the second direction, and multiple contacts are arranged along the first direction and the second direction array,
The angle of the first direction and the second direction is acute angle；
The 3-D stacks semiconductor device has multiple contacts, the step of cut down first photoresist layer and second photoresist layer
In, a spacing of adjacent two point meets following formula：P≤2 (N-1) * dx, wherein p are the spacing, and dx is to cut down photoresist layer
One margin of error.
2. the manufacture method of 3-D stacks semiconductor device according to claim 1, wherein Q≤P.
3. the manufacture method of 3-D stacks semiconductor device according to claim 1, wherein N≤P × Q × R, R are just whole
Number, the manufacture method of the 3-D stacks semiconductor device is further included：
One the 3rd photoresist layer is provided, the 3rd photoresist layer covers the part surface of these laminated construction；
With the 3rd photoresist layer as mask, R-1 these laminated construction is etched, in each etching of this step, these are folded
Rotating fields are etched the thickness of P × Q layers, and after etching these laminated construction at the 1st time～the R-2 time, all cut down the 3rd light
The width of photoresist layer is once；And
Remove the 3rd photoresist layer.
4. the manufacture method of 3-D stacks semiconductor device according to claim 3, wherein R≤Q≤P.
5. a kind of 3-D stacks semiconductor device, including：
N shell laminated construction, respectively the laminated construction include：
One conductive layer, N is positive integer；And
One insulating barrier, these conductive layers and these insulating barrier cross laminates；And
N bar wires, respectively the wire be electrically connected at a contact of the respectively conductive layer；
Wherein these contacts are arranged in a P stratum step structure, these contact edges along a first direction with the gap of monolayer
A second direction and one Q stratum step structure is arranged in the gap of P layers, N≤P × Q, these contacts are along the first direction
And the angle of the second direction array arrangement, the first direction and the second direction is acute angle, P, Q are positive integer；
One spacing of adjacent two point meets following formula：P≤2 (N-1) * dx, wherein p are the spacing, and dx is reduction photoresist layer
A margin of error, manufacture 3-D stacks semiconductor device during photoresist series of strata be covered in laminated construction as mask
Part surface all cuts down the light to etch the P-1 laminated construction after etching these laminated construction at the 1st time～the P-2 time
The width of photoresist layer is once.
6. 3-D stacks semiconductor device according to claim 5, wherein the N bars wire from these contacts in the same direction
Run-in index straight-line extension.
7. 3-D stacks semiconductor device according to claim 5, wherein the P stratum step structure and the Q stratum rank
Ladder-shaper structure constitutes one P × Q stratum step structure, and P × Q stratum step structure is along the first direction with P × Q layers
Gap is arranged in one P × Q × R stratum step structure, and wherein R is positive integer, and R≤Q≤P.
8. 3-D stacks semiconductor device according to claim 7, the wherein P × Q × R stratum step structure is along this
Second direction is arranged in one P × Q × R × S stratum step structure with the gap of P × Q × R layers, and wherein S is positive integer, N≤P
× Q × R × S, and P, Q, R, S are the factor of N.
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| US8530350B2 (en) * | 2011-06-02 | 2013-09-10 | Micron Technology, Inc. | Apparatuses including stair-step structures and methods of forming the same |
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