CN108733116B - 恒压电源电路 - Google Patents
恒压电源电路 Download PDFInfo
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- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
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Abstract
本发明提供一种谋求改善负载调节的恒压电源电路。恒压电源电路具备:误差放大器(6),具备反相输入端子(61)和非反相输入端子(62);基准电压源(5),与该误差增幅器(6)的反相输入端子(61)连接;输出用的晶体管(MP1),源极与电源端子(1)连接,漏极与电路输出端子(3)连接,栅极与误差放大器(6)的输出端子(63)连接;以及输出电压检测电路(7),连接在电路输出端子(3)与电源端子(2)之间,检测电路输出端子(3)的电压并输入至误差放大器(6)的非反相输入端子(62),其中,在误差放大器(6)的输出端子(63)与晶体管(MP1)的栅极之间连接有正反馈电路(8)。
Description
技术领域
本发明涉及一种在输出电流的整个区域负载调节特性优异的恒压电源电路。
背景技术
图5示出了以往的恒压电源电路10E(例如,专利文献1)。1是电压为VDD的高电位电源端子,2是电压为VSS(<VDD)的低电位电源端子,3是输出电压为VREG的电路输出端子,4是电流为IS的电流源,5是电压为VR的基准电压源。MN4、MN5、MN6是构成差分电路的NMOS晶体管,MP3、MP4是构成此差分电路的有源负载的电流反射镜连接的PMOS晶体管。由这些晶体管MN4~MN6、MP3、MP4构成误差放大器6,且此误差放大器6的反相输入端子61与基准电压源5连接。MN7是与晶体管MN6电流反射镜连接的NMOS晶体管,将电流源4的电流IS作为偏置电流供给至晶体管MN6。MP1是栅极与误差放大器6的输出端子63连接的输出用的PMOS晶体管,其漏极与电路输出端子3连接。电阻R3、R4构成检测输出电压VREG的输出电压检测电路7,连接在电路输出端子3与电源端子2之间,此电阻R3、R4的共同连接点与误差放大器6的非反相输入端子62连接。
然后,通过该恒压电源电路10E得到的输出电压VREG是:
在此,想到了从电路输出端子3引出输出电流的情况。
在完全没有输出电流的无负载的情况下,晶体管MP1仅供给流过电阻R3、R4的电流。通常,为了极力谋求低消耗电流化,在电阻R3、R4使用几MΩ的高电阻值的电阻。此时,驱动负载的晶体管MP1由误差放大器进行控制,以便在亚阈值区(sub-threshold region)动作。当输出电流逐渐增大时,晶体管MP1向在饱和区的动作转移,而且当输出电流增大时,向在非饱和区的动作转移,输出电压VREG随着输出电流的增大而呈线性降低。
现有技术文献
专利文献
专利文献1:日本特开2010-079653号公报
发明内容
发明所要解决的问题
在图6示出了该输出电流的特性。用实线表示的特性B是表示图5的恒压电源电路10E的相对于输出电流的输出电压的变化的特性。该输出电压特性被用作恒压电源电路的性能指标之一,该特性的好坏是电路选择的重要要素。
在图6的特性中,如前所述,在输出电流小的区域,由于晶体管MP1在亚阈值区动作,因此电压大幅变动。当输出电流进一步增大时,变为在饱和区的动作,并向相对于输出电流呈平方的特性转移,最终变为在非饱和区的动作,并遵循电压线性降低的轨跡。
该输出电压特性能够呈现作负载调节特性,该负载调节特性由在输出电流的任意2点I1、I2之间的输出电压VREG的降低倾斜的程度来表示,一般由以下算式(2)来定义:
VR1是输出电流为I1时的输出电压,VR2是输出电流为I2时的输出电压。图6中以LRb来表示图5的恒压电源电路10E的负载调节特性。
根据图6也可知,为了在输出电流的整个区域改善负载调节特性,要求改善在输出电流小的区域的特性。算式(2)的LR的值越小,负载调节越“好”。
本发明的目的在于提供一种谋求改善这样的负载调节的恒压电源电路。
用于解决问题的方案
为了达到上述目的,方案1的发明是一种恒压电源电路,其具备:误差放大器,具备反相输入端子和非反相输入端子;基准电压源,与该误差放大器的所述反相输入端子连接;输出用的第一导电型的第一晶体管,源极与第一电源端子连接,漏极与电路输出端子连接,栅极与所述误差放大器的输出端子连接;以及输出电压检测电路,连接在所述电路输出端子与第二电源端子之间,检测所述电路输出端子的电压并输入至所述误差放大器的非反相输入端子,其特征在于,在所述误差增幅器的输出端子与所述第一导电型的第一晶体管的栅极之间连接有正反馈电路。
方案2的发明的特征在于,在方案1所述的恒压电源电路中,所述正反馈电路包含:第一导电型的第二晶体管,栅极与所述误差放大器的输出端子连接,源极与所述第一电源端子连接;第二导电型的第一晶体管,漏极和栅极与该第一导电型的第二晶体管的漏极连接,源极与所述第二电源端子连接;以及第二导电型的第二晶体管,漏极与所述误差放大器的输出端子连接,源极与所述第二电源端子连接,栅极与所述第二导电型的第一晶体管的栅极连接。
方案3的发明的特征在于,在方案2所述的恒压电源电路中,在所述第一导电型的第二晶体管的漏极与所述第二导电型的第一晶体管的漏极之间插入连接有第一电阻。
方案4的发明的特征在于,在方案2所述的恒压电源电路中,在所述第一导电型的第二晶体管的漏极与所述第二导电型的第一晶体管的漏极之间,插入连接有漏极与所述第一导电型的第二晶体管的漏极连接、源极和栅极与所述第二导电型的第一晶体管的漏极连接的第二导电型的耗尽型晶体管。
方案5的发明的特征在于,在方案2、3或4所述的恒压电源电路中,在所述第二导电型的第二晶体管的源极与所述第二电源端子之间插入连接有第二电阻。
发明效果
根据本发明,在误差放大器的输出端子与作为输出晶体管的第一导电型的第一晶体管的栅极之间插入连接有正反馈电路,由此,能改善负载调节特性。
附图说明
图1是本发明的第一实施例的恒压电源电路的电路图。
图2是本发明的第二实施例的恒压电源电路的电路图。
图3是本发明的第三实施例的恒压电源电路的电路图。
图4是本发明的第四实施例的恒压电源电路的电路图。
图5是以往的恒压电源电路的电路图。
图6是负载调节特性图。
附图标记说明:
10A~10E 恒压电源电路
1 高压电源端子
2 低压电源端子
3 电路输出端子
4 电流源
5 基准电压源(reference voltage source)
6 误差放大器
61 反相输入端子(inverting input terminal)
62 非反相输入端子(noninverting input terminal)
63 输出端子
7 输出电压检测电路
8 正反馈电路
具体实施方式
<第一实施例>
图1示出了本发明的第一实施例的恒压电源电路10A。在图1中,对与通过图5进行了说明的构成相同的构成标注相同的附图标记并省略重复说明。8是正反馈电路,由PMOS晶体管MP2和NMOS晶体管MN1、MN2构成。晶体管MP2的源极与电源端子1连接,栅极与误差放大器6的输出端子63连接。晶体管MN1的栅极和漏极与晶体管MP2的漏极连接,源极与电源端子2连接。晶体管MN2的漏极与误差放大器6的输出端子63连接,栅极与晶体管MN1的栅极连接,源极与电源端子2连接。这些晶体管MN1、MN2构成电流反射镜,并且将晶体管MP2的漏极电流反射至晶体管MN2的漏极。
晶体管MP2与晶体管MP1栅极长度相等,栅极宽度的比设定为MP2:MP1=1:n(n>1)。由此,晶体管MP2的漏极电流是晶体管MP1的漏极电流的1/n。
晶体管MN1和MN2的栅极宽度比设定为MN1:MN2=m:1(m>1)。因此,在将晶体管MN2的漏极与误差放大器6的输出端子63连接时,晶体管MN2从误差放大器6的输出端子63引入晶体管MP1的输出电流量的1/(m×n)的电流,能使误差放大器6的输出特性大幅转变(迁移)。
这样,在本实施例的恒压电源电路10A中,由于除了误差放大器6固有的增益之外还加上正反馈电路8的增益,因此能使晶体管MP1的栅极电压变化,能改善在输出电流的整个区域的负载调节(load regulation)特性。
以上的结果是,如图6所示的特性A那样,具有与图5的恒压电源电路的特性B相比,能将电压降改善为大幅平缓的特性的特征。在图6中,输出电流为I2的点的输出电压的值从VR2向VR2’变化,可知其负载调节特性LRa的值会大幅改善。
<第二实施例>
图2示出了第二实施例的恒压电源电路10B。在通过图1进行了说明的第一实施例的恒压电源电路10A中,采用通过由误差放大器6的输出端子63的电压产生的电流来对误差放大器6的输出端子63施加正反馈的构成,因此还可想到因反馈量而附带振荡的风险。
因此,在图2所示的第二实施例的恒压电源电路10B中,在正反馈电路8的晶体管MP2的漏极与晶体管MN1的漏极之间插入了电阻R1。由此,在晶体管MP2的漏极电流大幅增大的情况下(晶体管MP1的输出电流也同样增大),能减小向误差放大器6的输出端子63的反馈量,降低振荡的风险。
<第三实施例>
图3示出了第三实施例的恒压电源电路10C。在即使通过如图2说明的那样将电阻R1插入连接到正反馈电路8的第二实施例的恒压电源电路10B也无法降低振荡的风险的情况下,如图3所示,以连接栅极、源极的构成插入连接耗尽型NMOS晶体管MN3来代替电阻R1。
这样,由于流过晶体管MP2的漏极电流增大,由此晶体管MN3的漏极电压上升,因此晶体管MN3的源极、背栅极(back gate)间的电位差增大。其结果是,由于晶体管MN3的背栅效应,其阈值电压升高,漏极、源极间的电阻进一步高电阻化。由此,在晶体管MP1流过大的输出电流时,能进一步减小向误差放大器6的反馈量。
根据以上,与通过图2进行了说明的恒压电源电路10B相比,能进一步降低振荡的风险。需要说明的是,作为背栅效应的算式,NMOS晶体管MN3的阈值电压Vth如以下的算式(3)那样来表示。
在此,Vth0是零偏置时的阈值电压,γ是基板效应系数,VSB是源极、背栅极间电压,φF是P型基板的费米能级。
<第四实施例>
图4示出了第四实施例的恒压电源电路10D。在本实施例中,在通过图1进行了说明的恒压电源电路10A中的正反馈电路8的输出侧的晶体管MN2的源极、背栅极端子与电源端子2之间插入电阻R2,以便进行电流限制。在该情况下,与通过图2以及图3进行了说明的恒压电源电路10B、10C同样,在晶体管MP1流过大的输出电流时,能减小向误差放大器6的反馈量。
<其他实施例>
需要说明的是,在以上的实施例中,在电源电压为VDD>VSS的条件的情况下进行了说明,但在电源电压的高低关系相反的情况下,将PMOS晶体管替换为NMOS晶体管,并将NMOS晶体管替换为PMOS晶体管即可。此外,在权利要求中将PMOS晶体管和NMOS晶体管的一方记载为第一导电型,将另一方记载为第二导电型。
Claims (5)
1.一种恒压电源电路,具备:误差放大器,具备反相输入端子和非反相输入端子以及差分电路;基准电压源,与该误差放大器的所述反相输入端子连接;输出用的第一导电型的第一晶体管,源极与第一电源端子连接,漏极与电路输出端子连接,栅极与所述误差放大器的输出端子连接;以及输出电压检测电路,连接在所述电路输出端子与第二电源端子之间,检测所述电路输出端子的电压并输入至所述误差放大器的非反相输入端子,其中,
在所述误差放大器的输出端子与所述第一导电型的第一晶体管的栅极之间连接有正反馈电路,所述正反馈电路的输入端子和输出端子是同一端子,所述正反馈电路的输入端子和输出端子连接于第一导电型的第一晶体管的栅极,所述正反馈电路的输入端子和输出端子直接连接于误差放大器的输出端子。
2.根据权利要求1所述的恒压电源电路,其特征在于,
所述正反馈电路包含:第一导电型的第二晶体管,栅极与所述误差放大器的输出端子连接,源极与所述第一电源端子连接;第二导电型的第一晶体管,漏极和栅极与该第一导电型的第二晶体管的漏极连接,源极与所述第二电源端子连接;以及第二导电型的第二晶体管,漏极与所述误差放大器的输出端子连接,源极与所述第二电源端子连接,栅极与所述第二导电型的第一晶体管的栅极连接。
3.根据权利要求2所述的恒压电源电路,其特征在于,
在所述第一导电型的第二晶体管的漏极与所述第二导电型的第一晶体管的漏极之间插入连接有第一电阻。
4.根据权利要求2所述的恒压电源电路,其特征在于,
在所述第一导电型的第二晶体管的漏极与所述第二导电型的第一晶体管的漏极之间,插入连接有漏极与所述第一导电型的第二晶体管的漏极连接、源极和栅极与所述第二导电型的第一晶体管的漏极连接的第二导电型的耗尽型晶体管。
5.根据权利要求2~4中任一项所述的恒压电源电路,其特征在于,
在所述第二导电型的第二晶体管的源极与所述第二电源端子之间插入连接有第二电阻。
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