CN108717843B

CN108717843B - Display device and gate driver thereof

Info

Publication number: CN108717843B
Application number: CN201810562337.XA
Authority: CN
Inventors: 林凱俊; 任珂锐; 陈致成
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2018-02-26
Filing date: 2018-06-04
Publication date: 2020-04-14
Anticipated expiration: 2038-06-04
Also published as: TW201937468A; TWI649733B; CN108717843A

Abstract

The invention provides a display device and a gate driver thereof. The display device and the gate driver thereof can integrate the clock pulse signal and the enabling signal into the same signal, and obtain the starting signal required by the gate driver by utilizing a plurality of logic circuit elements to carry out operation processing on the enabling signal, thereby reducing the number of input signal pins on the gate driver.

Description

Display device and gate driver thereof

Technical Field

The present invention relates to a display device and a gate driver thereof, and more particularly, to a display device and a gate driver thereof capable of reducing the number of pins (pins).

Background

In general, a display device includes a data driver, a gate driver, and pixels arranged in a matrix form. The gate driver includes a plurality of shift register circuits for outputting a plurality of scan signals to turn on a plurality of rows of pixels in the display device, and the turned-on pixels receive and display data provided by the data driver. In recent years, in order to meet consumer demands, display devices are generally designed to be light, thin and narrow (without) frames. Therefore, the number of pins for inputting signals is also severely limited in such designs. Accordingly, there is a need in the art for a display device and a gate driver thereof that can reduce the number of pins.

Disclosure of Invention

The invention provides a display device and a gate driver thereof capable of reducing the number of pins. To achieve the above objective, an embodiment of the present invention provides a gate driver, which includes a start signal generating circuit, a first shift register circuit, a second shift register circuit, and a third shift register circuit. The starting signal generating circuit is used for receiving a first enabling signal, a second enabling signal and a third enabling signal and generating a starting signal. The first shift register circuit is electrically coupled to the start signal generating circuit, receives the first enable signal and the start signal, and generates at least one first gate driving signal. The second shift register circuit is electrically coupled to the start signal generating circuit, receives the second enable signal and the start signal, and generates at least one second gate driving signal. The third shift register circuit is electrically coupled to the start signal generating circuit, receives the third enable signal and the start signal, and generates at least one third gate driving signal.

The embodiment of the invention further provides a display device, which comprises a time schedule controller, an initial signal generating circuit, a grid driver, a data driver and a plurality of pixel units. The time schedule controller is used for generating a first enabling signal, a second enabling signal and a third enabling signal. The starting signal generating circuit is electrically coupled with the time schedule controller and is used for receiving the first enabling signal, the second enabling signal and the third enabling signal and generating a starting signal. The gate driver is electrically coupled with the timing controller and the initial signal generating circuit, receives a first enabling signal, a second enabling signal, a third enabling signal and the initial signal, and outputs a plurality of gate driving signals according to the first enabling signal, the second enabling signal, the third enabling signal and the initial signal. The data driver is used for outputting a plurality of display data, each pixel unit is electrically coupled with the grid driver and the data driver, and each pixel unit is used for determining whether to receive the display data according to the received grid driving signal.

For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for illustration purposes only and are not intended to limit the scope of the invention.

Drawings

Fig. 1 is a functional block diagram of a gate driver according to an embodiment of the present invention.

Fig. 2 is a circuit schematic diagram of a start signal generating circuit in the gate driver of fig. 1.

Fig. 3A is a timing diagram illustrating first to third enable signals in the gate driver of fig. 1 during a first period.

Fig. 3B is a timing diagram illustrating the first to third enable signals in the gate driver of fig. 1 during a second period.

Fig. 4 is a functional block diagram of a display device according to an embodiment of the present invention.

Fig. 5 is a functional block diagram of a display device according to another embodiment of the present invention.

Wherein, the reference numbers:

4. 5: display device

40: time sequence controller

44: data driver

46: pixel unit

10. 42, 52: gate driver

101: initial signal generating circuit

520: shift register circuit

103: first shift register circuit

105: second shift register circuit

107: third shift register circuit

emOE 1: first enable signal

emOE 2: second enable signal

emOE 3: the third enable signal

i-STP: initial signal

GS 1: a first gate drive signal

GS 2: second gate drive signal

GS 3: third gate drive signal

G₁～G_M: polar drive signal

S₁～S_P: displaying data

1031: shift temporary storage device

1033: and gate

2011-2014: first to fourth logic gates

2021 to 2024: first to fourth D-type flip-flops

Detailed Description

Hereinafter, the present invention will be described in detail by illustrating various embodiments thereof with the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Moreover, in the drawings, like reference numerals may be used to denote similar elements.

Specifically, the gate driver provided in the embodiments of the invention may be applied to any display device, such as an Active Matrix Organic Light Emitting Diode (AMOLED) display device adopting a progressive scanning method, but the invention is not limited thereto. In summary, the present invention is not limited to the specific implementation of the display device, and one skilled in the art should be able to design the display device according to actual needs or applications.

In addition, as known in the art, the gate driver may include a plurality of shift register circuits, and each shift register circuit is configured to receive an enable signal, a start signal and at least one clock signal and generate at least one gate driving signal to drive at least one row of pixels in the display device. Therefore, in the case of only three shift register circuits, at least seven input signal pins are required in the conventional gate driver. Three of which are used to receive an enable signal, three of which are used to receive a clock signal, and the last of which is used to receive a common start signal.

However, compared to the prior art, the present invention proposes to hide or combine a part of the control mechanism on some existing signals, so as to achieve the purpose of reducing the number of pins. Referring to fig. 1, fig. 1 is a functional block diagram of a gate driver according to an embodiment of the present invention. The gate driver 10 includes a start signal generating circuit 101, a first shift register circuit 103, a second shift register circuit 105, and a third shift register circuit 107. The start signal generating circuit 101 is configured to receive a first enable signal emOE1, a second enable signal emOE2, and a third enable signal emOE3, and generate a start signal i-STP.

In addition, the first to third

shift register circuits

103, 105 and 107 are electrically coupled to the start signal generating circuit 101, respectively, and the first shift register circuit 103 receives the first enable signal emOE1 and the start signal i-STP for generating at least one first gate driving signal GS 1. The second shift register circuit 105 receives the second enable signal emOE2 and the start signal i-STP to generate at least one second gate driving signal GS2, and the third shift register circuit 107 receives the third enable signal emOE3 and the start signal i-STP to generate at least one third gate driving signal GS 3. It should be noted that, for the convenience of the following description, the shift register circuits of the present embodiment are also described by using only three sets (i.e., the first to third

shift register circuits

103, 105, 107), but the invention is not limited thereto.

In other words, the gate driver 10 may further include a fourth shift register circuit to an nth shift register circuit (i.e., N is a positive integer greater than or equal to five), and it should be understood that the operation principle of the fourth shift register circuit to the nth shift register circuit is similar to that of the first shift register circuit 103, the first shift register circuit 105, and the second shift register circuit 107, and therefore, the description thereof is omitted. In addition, since the details of the shift register circuit are well known to those skilled in the art, only the details of the first shift register circuit 103 will be taken as an illustration in fig. 1, and the details of the second and third

shift register circuits

105 and 107 will not be further described herein. As shown in fig. 1, the first shift register circuit 103 may include a shift register 1031 AND a plurality of AND gates 1033.

Similarly, for the convenience of the following description, the and gate 1033 in fig. 1 is also described by using only four examples, but it is not intended to limit the present invention. As is known in the art, since the waveform of the first clock signal (not shown) originally received by the shift register 1031 is very similar to the waveform of the first enable signal emOE1 received by the and gate 1033, the first clock signal and the first enable signal emOE1 are integrated into the same signal, and so on, the second clock signal (not shown) and the third clock signal (not shown) originally received by the second and third

shift register circuits

105 and 107 are integrated into the same signal as the second enable signal emOE2 and the third enable signal emOE3, respectively. Thus, the number of input signal pins on the gate driver 10 can be first omitted by three, while still meeting the operation requirements of the display device.

In addition, since the start signal i-STP commonly received by the first to third

shift register circuits

103, 105, 107 can be generated by the start signal generating circuit 101 in the gate driver 10, the number of input signal pins of the gate driver 10 is omitted. That is, compared to the conventional gate driver having seven input signal pins, the gate driver 10 of the embodiment of the invention only needs to have four input signal pins. However, in order to further explain the implementation details of the start signal generating circuit 101, the present invention further provides an implementation of the start signal generating circuit 101. Referring to fig. 2, fig. 2 is a circuit diagram of a start signal generating circuit in the gate driver of fig. 1. In fig. 2, the same elements as those in fig. 1 are denoted by the same reference numerals, and therefore, the details thereof will not be described herein.

In the present embodiment, the start signal generating circuit 101 may include a plurality of logic gates and a plurality of D-type flip-flops, such as the first to fourth logic gates 2011-2014 and the first to fourth D-type flip-flops 2021-2024. The first logic gate 2011 has two input terminals and an output terminal, one input terminal receives the first enable signal emOE1, and the other input terminal receives the second enable signal emOE 2. The second logic gate 2012 also has two input terminals and an output terminal, but one input terminal receives the second enable signal emOE2, and the other input terminal receives the third enable signal emOE 3. The third logic gate 2013 also has two input terminals and an output terminal, but one input terminal receives the third enable signal emOE3, and the other input terminal receives the first enable signal emOE 1.

Then, the data input terminal (D) of the first D-type flip-flop 2021 is electrically coupled to the output terminal of the first logic gate 2011, and the clock input terminal of the first D-type flip-flop 2021 receives the third enable signal emOE 3. Similarly, the data input of the second D-type flip-flop 2022 is electrically coupled to the output of the second logic gate 2012, and the clock input of the second D-type flip-flop 2022 receives the first enable signal emOE 1. The data input terminal of the third D-type flip-flop 2023 is electrically coupled to the output terminal of the third logic gate 2013, and the clock input terminal of the third D-type flip-flop 2023 receives the second enable signal emOE 2.

In addition, the fourth logic gate 2014 has three input terminals and one output terminal, and the three input terminals are electrically coupled to the non-inverting output terminals (Q) of the first to third D-type flip-flops 2021 to 2023, respectively. The data input terminal of the fourth D-type flip-flop 2024 is electrically coupled to the output terminal of the fourth logic gate 2014, and the clock input terminal of the fourth D-type flip-flop 2024 receives the third enable signal emOE3 and outputs the start signal i-STP at the non-inverting output terminal of the fourth D-type flip-flop 2024.

In the present embodiment, the first logic gate 2011, the second logic gate 2012 and the third logic gate 2013 may all be an OR gate (OR), the fourth logic gate 2014 may be an inverse OR gate (NOR), the first D-type flip-flop 2021, the second D-type flip-flop 2022 and the third D-type flip-flop 2023 may all be positive edge triggered D-type flip-flops, and the fourth D-type flip-flop 2024 may be a negative edge triggered D-type flip-flop, as shown in fig. 2, but the present invention is not limited thereto. In addition, since the operation principles of the or gate, the nor gate, the positive edge triggered D-type flip-flop and the negative edge triggered D-type flip-flop are well known in the art, the details of the first to fourth logic gates 2011-2014 and the first to fourth D-type flip-flops 2021-2024 are not repeated herein.

However, based on the above teachings, it should be understood by those skilled in the art that the present invention can utilize a plurality of logic circuit elements (i.e., the first to fourth logic gates 2011-2014 and the first to fourth D-type flip-flops 2021-2024) to perform the operation on the first to third enable signals emOE 1-emOE 3 to obtain the start signal i-STP that the first to third shift register circuits 103-107 have to commonly receive. In addition, since the start signal i-STP is generally generated only before the display device displays a picture, a set of waveforms of the first to third enable signals emOE1 to emOE3 may be additionally designed to generate the start signal i-STP. That is, the original waveforms of the first to third enable signals emOE1 to emOE3 will not be used to generate the start signal i-STP during the period when the display device normally displays one frame.

Referring to fig. 3A and 3B together, fig. 3A is a timing diagram illustrating first to third enable signals in the gate driver of fig. 1 during a first period. The first period may be, for example, any period before the display device displays one screen. As shown in fig. 3A, during the first period, the rising edge and the falling edge of the first enable signal emOE1 are earlier than the rising edge and the falling edge of the second enable signal emOE2, and the rising edge and the falling edge of the second enable signal emOE2 are earlier than the rising edge and the falling edge of the third enable signal emOE 3. Therefore, when the display device displays a picture, the start signal generating circuit 101 of fig. 2 generates the high-level start signal i-STP according to the waveform.

Similarly, fig. 3B is a timing diagram illustrating the first to third enable signals in the gate driver of fig. 1 during a second period. The second period of time may be any period of time when the display device normally displays one screen, for example. As shown in fig. 3B, in the second period, the rising edge of the third enable signal emOE3 is earlier than the rising edge of the second enable signal emOE2, the rising edge of the second enable signal emOE2 is earlier than the rising edge of the first enable signal emOE1, the falling edge of the second enable signal emOE2 is earlier than the falling edge of the first enable signal emOE1, and the falling edge of the first enable signal emOE1 is earlier than the falling edge of the third enable signal emOE 3. Therefore, the start signal generating circuit 101 in fig. 2 does not generate the start signal i-STP according to the waveforms during the period when the display device normally displays one screen.

It should be noted that the waveforms of the first to third enable signals emOE1 to emOE3 used in fig. 3A and 3B are only examples, and are not intended to limit the present invention. In other words, one skilled in the art should be able to design different timing waveforms according to actual requirements or applications. Next, to further explain the application of reducing the number of input signal pins on the gate driver, the present invention further provides an embodiment of a display device. Referring to fig. 4, fig. 4 is a functional block diagram of a display device according to an embodiment of the present invention. In fig. 4, the same elements as those in fig. 1 are denoted by the same reference numerals, and therefore, the details thereof will not be described herein.

As shown in fig. 4, the display device 4 may include a timing controller 40, a start signal generating circuit 101, a gate driver 42, a data driver 44, and a plurality of pixel units 46. The timing controller 40 is configured to generate a first enable signal emOE1, a second enable signal emOE2, and a third enable signal emOE 3. The start signal generating circuit 101 is electrically coupled to the timing controller 40, and the start signal generating circuit 101 is configured to receive the first enable signal emOE1, the second enable signal emOE2, and the third enable signal emOE3, and generate a start signal i-STP.

The gate driver 42 is electrically coupled to the timing controller 40 and the start signal generating circuit 101, and the gate driver 42 receives the first enable signal emOE1, the second enable signal emOE2, the third enable signal emOE3 and the start signal i-STP, and outputs a plurality of gate driving signals according to the first enable signal emOE1, the second enable signal emOE2, the third enable signal emOE3 and the start signal i-STP, such as the gate driving signal G shown in fig. 4₁～G_M(i.e., M is a positive integer greater than 1). In addition, the data driver 44 is used for outputting a plurality of display data, such as the display data S shown in FIG. 4₁～S_P(i.e., P is a positive integer greater than 1). Each pixel unit 46 and gate driver42 and a data driver 44, and each pixel unit 46 is used for receiving a gate driving signal G_i(i.e., i is a positive integer from 1 to M) to determine whether to receive the display data S₁～S_P。

However, as mentioned above, since the clock signal (not shown) originally received by the gate driver 42 is integrated with the first enable signal emOE1, the second enable signal emOE2 or the third enable signal emOE3 into one signal, the number of the input signal pins of the gate driver 42 can be reduced to three, while still meeting the operation requirement of the display device 4. In addition, the start signal generating circuit 101 of the present embodiment may also be configured in the gate driver 42, so that referring to fig. 5 together, fig. 5 is a functional block diagram of a display device according to another embodiment of the present invention. In fig. 5, the same elements as those in fig. 4 are denoted by the same reference numerals, and therefore, the details thereof will not be described herein.

In the display device 5 of fig. 5, the gate driver 52 actively includes a start signal generating circuit 101. Since the start signal i-STP commonly received by the shift register circuits 520 in the gate driver 52 can be generated by the start signal generating circuit 101 in the gate driver 52, the number of input signal pins of the gate driver 52 is omitted. In summary, the present invention is not limited to the specific configuration of the start signal generating circuit 101, and one skilled in the art should be able to design the start signal generating circuit according to actual needs or applications.

In addition, the start signal generating circuit 101 can be implemented as described in the previous embodiments, and therefore, the details thereof will not be further described herein. Furthermore, since the waveforms of the first to third enable signals emOE1 to emOE3 are additionally designed to generate the start signal i-STP, the waveforms of the first to third enable signals emOE1 to emOE3 generated by the timing controller 40 may be similar to those of the previous embodiments, and thus the details thereof will not be further described herein.

In summary, the display device and the gate driver thereof according to the embodiments of the invention can integrate the clock signal and the enable signal into the same signal, and perform the operation processing on the enable signal by using a plurality of logic circuit elements to obtain the start signal required by the gate driver, thereby reducing the number of input signal pins on the gate driver.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A gate driver, comprising:

the starting signal generating circuit is used for receiving a first enabling signal, a second enabling signal and a third enabling signal and generating a starting signal;

a first shift register circuit electrically coupled to the start signal generating circuit, the first shift register circuit receiving the first enable signal and the start signal and generating at least one first gate driving signal;

a second shift register circuit electrically coupled to the start signal generating circuit, the second shift register circuit receiving the second enable signal and the start signal and generating at least one second gate driving signal; and

and a third shift register circuit electrically coupled to the start signal generating circuit, the third shift register circuit receiving the third enable signal and the start signal and generating at least a third gate driving signal.

2. The gate driver of claim 1, wherein the start signal generating circuit comprises:

a first logic gate having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the first logic gate receives the first enable signal, and the second input terminal of the first logic gate receives the second enable signal;

a second logic gate having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the second logic gate receives the second enable signal, and the second input terminal of the second logic gate receives the third enable signal;

a third logic gate having a first input terminal, a second input terminal and an output terminal, the first input terminal of the third logic gate receiving the third enable signal, the second input terminal of the third logic gate receiving the first enable signal;

a first D-type flip-flop having a data input terminal, a clock input terminal, and a positive phase output terminal, the data input terminal of the first D-type flip-flop being electrically coupled to the output terminal of the first logic gate, the clock input terminal of the first D-type flip-flop receiving the third enable signal;

a second D-type flip-flop having a data input terminal, a clock input terminal and a positive phase output terminal, the data input terminal of the second D-type flip-flop being electrically coupled to the output terminal of the second logic gate, the clock input terminal of the second D-type flip-flop receiving the first enable signal;

a third D-type flip-flop having a data input terminal, a clock input terminal, and a positive phase output terminal, the data input terminal of the third D-type flip-flop being electrically coupled to the output terminal of the third logic gate, the clock input terminal of the third D-type flip-flop receiving the second enable signal;

a fourth logic gate having a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal of the fourth logic gate is electrically coupled to the positive phase output terminal of the first D-type flip-flop, the second input terminal of the fourth logic gate is electrically coupled to the positive phase output terminal of the second D-type flip-flop, and the third input terminal of the fourth logic gate is electrically coupled to the positive phase output terminal of the third D-type flip-flop; and

a fourth D-type flip-flop having a data input terminal, a clock input terminal, and a positive phase output terminal, wherein the data input terminal of the fourth D-type flip-flop is electrically coupled to the output terminal of the fourth logic gate, the clock input terminal of the fourth D-type flip-flop receives the third enable signal, and the positive phase output terminal of the fourth D-type flip-flop outputs the start signal.

3. The gate driver of claim 2, wherein the first logic gate, the second logic gate and the third logic gate are OR gates, the first D-type flip-flop, the second D-type flip-flop and the third D-type flip-flop are positive edge triggered D-type flip-flops, the fourth logic gate is an anti-OR gate, and the fourth D-type flip-flop is a negative edge triggered D-type flip-flop.

4. The gate driver of claim 3, wherein a rising edge and a falling edge of the first enable signal are earlier than a rising edge and a falling edge of the second enable signal, and a rising edge and a falling edge of the second enable signal are earlier than a rising edge and a falling edge of the third enable signal, during a first period, a rising edge of the third enable signal is earlier than a rising edge of the second enable signal, a rising edge of the second enable signal is earlier than a rising edge of the first enable signal, a falling edge of the second enable signal is earlier than a falling edge of the first enable signal, and a falling edge of the first enable signal is earlier than a falling edge of the third enable signal.

5. A display device, comprising:

the timing controller is used for generating a first enabling signal, a second enabling signal and a third enabling signal;

the starting signal generating circuit is electrically coupled with the time schedule controller and is used for receiving the first enabling signal, the second enabling signal and the third enabling signal and generating a starting signal;

a gate driver electrically coupled to the timing controller and the start signal generating circuit, the gate driver receiving the first enable signal, the second enable signal, the third enable signal and the start signal and outputting a plurality of gate driving signals according to the first enable signal, the second enable signal, the third enable signal and the start signal;

a data driver for outputting a plurality of display data; and

and each pixel unit is electrically coupled with the grid driver and the data driver and is used for determining whether to receive the display data according to the received grid driving signal.

6. The display device according to claim 5, wherein the start signal generating circuit is disposed in the gate driver.

7. The display device of claim 5, wherein the start signal generating circuit comprises:

8. The display device of claim 7, wherein the first logic gate, the second logic gate, and the third logic gate are OR gates, the first D-type flip-flop, the second D-type flip-flop, and the third D-type flip-flop are positive edge triggered D-type flip-flops, the fourth logic gate is an inverse OR gate, and the fourth D-type flip-flop is a negative edge triggered D-type flip-flop.

9. The display device as claimed in claim 8, wherein a rising edge and a falling edge of the first enable signal are earlier than a rising edge and a falling edge of the second enable signal, a rising edge and a falling edge of the second enable signal are earlier than a rising edge and a falling edge of the third enable signal in a first period, a rising edge of the third enable signal is earlier than a rising edge of the second enable signal, a rising edge of the second enable signal is earlier than a rising edge of the first enable signal, a falling edge of the second enable signal is earlier than a falling edge of the first enable signal, and a falling edge of the first enable signal is earlier than a falling edge of the third enable signal in a second period.