CN108649073A - Power semiconductor - Google Patents
Power semiconductor Download PDFInfo
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- CN108649073A CN108649073A CN201810650267.3A CN201810650267A CN108649073A CN 108649073 A CN108649073 A CN 108649073A CN 201810650267 A CN201810650267 A CN 201810650267A CN 108649073 A CN108649073 A CN 108649073A
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- Prior art keywords
- doping
- power semiconductor
- semiconductor layer
- area
- absorption area
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 239000000969 carrier Substances 0.000 claims abstract description 51
- 238000010521 absorption reaction Methods 0.000 claims abstract description 48
- 229910001385 heavy metal Inorganic materials 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000011133 lead Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 208000033999 Device damage Diseases 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000006096 absorbing agent Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of power semiconductor, including：The semiconductor layer of first kind doping；Positioned at the gate structure of the semiconductor layer surface；The body area of Second Type doping in the semiconductor layer of the gate structure both sides；The Carriers Absorption area in semiconductor layer between the body area.The power semiconductor has higher anti-SEGR abilities.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of power semiconductors.
Background technology
The core member device of vertical conduction bilateral diffusion MOS structure (VDMOS) device power integrated circuit and power integrated system
One of part.The grid and source electrode of VDMOS drains in the upper surface of substrate positioned at the lower surface of substrate.Source electrode and drain electrode is serving as a contrast
The opposite plane at bottom, when electric current flows to source electrode from drain electrode, electric current is flowed in silicon chip internal vertical, therefore can adequately be answered
With the area of silicon chip, to improve the ability by electric current.
Power VDMOSFET device has the advantages of bipolar transistor and MOS transistor concurrently, and switching speed is fast, input impedance is high, drives
It is dynamic low in energy consumption, there is negative temperature coefficient, no second breakdown to be widely used in fields such as Aeronautics and Astronautics, nuclear energy.But
Power VDMOSFET device is easy to be irradiated by various rays and charged particle, especially easily be weighed under space radiation environment
Ion induces single event burnout effect (SEB) and single event gate rupture effect (SEGR), causes device damage.
How to improve the anti-SEGR abilities of device is current urgent problem to be solved.
Invention content
The technical problem to be solved by the invention is to provide a kind of power semiconductor, the single-particle for improving device is burnt
Ruin effect (SEB) and single event gate rupture effect (SEGR).
To solve the above-mentioned problems, the present invention provides a kind of power semiconductors, including：The half of first kind doping
Conductor layer；Positioned at the gate structure of the semiconductor layer surface；Second in the semiconductor layer of the gate structure both sides
The body area of type doping；The Carriers Absorption area in semiconductor layer between the body area.
Optionally, the surface in the Carriers Absorption area and the semiconductor layer surface are coplanar.
Optionally, the minimum range between the Carriers Absorption area edge and the body area is more than 0 and is less than or equal to 2 μ
m。
Optionally, the Carriers Absorption area is adulterated for Second Type.
Optionally, the doping depth in the Carriers Absorption area is less than or equal to the doping depth in the body area.
Optionally, the doping concentration in the Carriers Absorption area is 1e12cm-3~1e18cm-3.
Optionally, doped with heavy metal ion in Carriers Absorption area uptake zone.
Optionally, the doping concentration of the heavy metal ion is 5e13cm-3~5e15cm-3。
Optionally, the semiconductor layer includes the epitaxial layer of at least one layer of first kind doping.
Optionally, the Carriers Absorption area includes multiple discrete sub- uptake zones.
Optionally, 2 μm are smaller than between the adjacent sub- uptake zone.
The power semiconductor of the present invention is provided with Carriers Absorption in the semiconductor layer between the body area of device
Area can be absorbed between device body area due to the excess carriers that heavy ion generates, to improve power semiconductor device
The anti-SEGR abilities of part.
Description of the drawings
Fig. 1 is the structural schematic diagram of the semiconductor devices of the embodiment of the invention.
Specific implementation mode
It elaborates below in conjunction with the accompanying drawings to the specific implementation mode of power semiconductor provided by the invention.
Referring to FIG. 1, the structural schematic diagram of the power semiconductor for the embodiment of the invention.
In the specific implementation mode, the power semiconductor includes the semiconductor layer 100 of first kind doping；It is located at
The gate structure of the semiconductor layer surface；The body of Second Type doping in the semiconductor layer of the gate structure both sides
Area 101；The Carriers Absorption area 104 in semiconductor layer 100 between the body area 101.
In the specific implementation mode, the first kind is doped to n-type doping, and the Second Type is doped to p-type doping；
In other specific implementation modes, the first kind doping can also be that p-type is adulterated, and the Second Type is doped to N-type and mixes
It is miscellaneous.The Doped ions of the n-type doping can be at least one of P, As or Td, and the Doped ions of the p-type doping can be with
For at least one of B, In or Ga.
The semiconductor layer 100 can be the monocrystalline substrate of first kind doping, or may include substrate and position
In the epitaxial layer that the first kind of the substrate surface is adulterated, alternatively, the semiconductor layer 100 can also include multiple stackings
The epitaxial layer of first kind doping.The material of the epitaxial layer can be the semi-conducting materials such as silicon, germanium or germanium silicon.Art technology
Personnel can select suitable construction, material and the described of doping concentration partly to lead according to the performance requirement of power semiconductor
Body layer 100.In the specific implementation mode, the semiconductor layer 100 includes the substrate of N-type heavy doping, and is located at the substrate
The epitaxial layer that the N-type on surface is lightly doped.
The gate structure include grid 111, the gate dielectric layer 112 between grid 111 and semiconductor layer 100 and
Cover the cap layer 113 of the grid 111, gate dielectric layer 112.
Body area 101 with Second Type doping in the semiconductor layers 100 of 111 both sides of grid, in the specific implementation mode,
It is adulterated for p-type in the body area 101.The part of semiconductor layer 100 for being located at 111 lower section of gate structure between the body area 101 of both sides
Neck region as the power semiconductor.
The source region 102 of first kind doping, in the specific implementation mode, the source region are also formed in the body area 101
102 be n-type doping.
The power semiconductor further includes positioned at the source for connecting the body area 101 on 100 surface of the semiconductor layer
Pole 103 and drain electrode 104 positioned at another surface opposite with the gate structure of the semiconductor layer 100.
In the specific implementation mode, the power semiconductor structure further includes a Carriers Absorption area 104.The carrier
Uptake zone 104 is in the semiconductor layer 100 between the body area 101, specifically the power between the body area 101 half
In the neck region of conductor device.There is complex centre in the Carriers Absorption area 104, produced after heavy ion bombardment device can be absorbed
Raw electron-hole pair avoids the carrier generated from being accumulated in surface neck region, to reduce the electricity of the peak value in gate dielectric layer 112
, and then improve the anti-SEGR abilities of device.The complex centre includes dislocation ring or deep energy level.
The Carriers Absorption area 104 can be that the first kind is adulterated, or Second Type adulterates.In the specific reality
It applies in mode, the doping type in the Carriers Absorption area 104 is consistent with the doping type in body area 101, is p-type doping, with
The doping type of semiconductor layer 100 on the contrary, advantageously reduce the grid charge of device, and the breakdown voltage of device will not be caused compared with
Big influence.
In other specific implementation modes, the doping type in the Carriers Absorption area 104 can also be mixed with body area 101
Miscellany type is on the contrary, consistent with the doping type of semiconductor layer 100.When the doping type in the Carriers Absorption area 104 with partly lead
Under the doping type unanimous circumstances of body layer 100, it is easy to affect greatly breakdown voltage parameter.It can be by carrier
The parameter adjustments such as the doping concentration of uptake zone 104, to reduce the influence to breakdown voltage parameter to the greatest extent.
The Carriers Absorption area 104 be the first kind adulterate or Second Type adulterate when doping concentration can be more than,
Less than or equal to the doping concentration in the body area 101, specifically, can be 1e12cm-3~1e18cm-3.When uptake zone 104
When doping type is Second Type, doping concentration is bigger, is more conducive to the absorption of carrier.Those skilled in the art can be
On the doping concentration scope, closed according to the performance requirement etc. of the doping type in the Carriers Absorption area 104, device
The adjustment of reason.
In other specific implementation modes, the Carriers Absorption area 104 can also attach most importance to metal ion mixing, described heavy
Metal ion can be at least one of platinum, gold, silver, copper or lead.Heavy ion doping can be in the Carriers Absorption area 104
Deep energy level is formed, the excess carriers of heavy ion generation can be absorbed.Meanwhile beavy metal impurity belongs to deep energy level defect, it will not
It is apparent to influence device doping and device performance.The doping concentration of the heavy metal ion can be 5e13cm-3~5e15cm-3。
Those skilled in the art can be on the doping concentration scope, and according to the resistance to pressure request to device, rationally adjustment is with much money
Belong to the doping concentration of ion.
In the specific implementation mode, surface and 100 surface co-planar of the semiconductor layer in the Carriers Absorption area 104,
It is arranged inside from 100 surface of semiconductor layer of the gate structure bottom to semiconductor layer 100.So that the carrier is inhaled
Area 104 and the gate dielectric layer 112 are received apart from closest, can utmostly reduce the electricity generated after heavy ion bombardment device
Influence of the son-hole to gate dielectric layer 112.Also, since the Carriers Absorption area 104 is located at the surface of semiconductor layer 100
Near, it is formed by modes such as ion implanting or diffusions, is easy to realize.
In other specific implementation modes, the Carriers Absorption area 104 can be fully located in the semiconductor layer 100
Portion, the distance between the surface in the Carriers Absorption area 104 and the surface of the semiconductor layer 100 are less than 1 μm, to carry as possible
Absorption of the high Carriers Absorption area 104 to neck excess carriers.
Minimum range between 104 edge of Carriers Absorption area and the body area 101 is more than 0 and is less than or equal to 2 μm.
The Carriers Absorption area 104 is mainly used for the excess carriers of 100 neck of semiconductor layer between absorber area 101, therefore
The Carriers Absorption area 104 is closer apart from the body area 101, and assimilation effect is better.If apart from too long, assimilation effect can become
Difference.Due to being formed with the Carriers Absorption area 104 in the neck region, in order to meet the requirement of breakdown voltage and conducting resistance,
It needs to adjust accordingly the width in neck region accordingly, the neck region width is the distance between two individual areas 101.
Excessive carrier is mainly inhaled in the Carriers Absorption area 104 by edge, so Carriers Absorption area 104
Side source pattern has an impact Carriers Absorption effect, especially the part edge adjacent with body area 101.According to the conducting to device
The requirement of the parameters such as resistance, breakdown voltage can be adjusted the pattern in Carriers Absorption area 104.Close to 101 side of body area
Edge can be arc, or other shapes vertical with 100 surface of semiconductor layer.
In the specific implementation mode of the present invention, the doping depth in the Carriers Absorption area 104 is less than or equal to described
The doping depth in body area 101, to avoid the breakdown voltage of device is reduced；In other specific implementation modes, if to device
Breakdown voltage is of less demanding, and the doping depth in the Carriers Absorption area 104 can also be slightly larger than the doping depth in the body area 101
Degree.
In the specific implementation mode, the Carriers Absorption area 104 is a complete continuous doped region, in other tools
A in body embodiment, the Carriers Absorption area 104 can also include multiple discrete uptake zones.It is inhaled to improve each height
Absorbability of the area to carrier is received, 2 μm are smaller than between the adjacent sub- uptake zone.
The power semiconductor of the specific implementation mode of the present invention is provided with current-carrying in the semiconductor layer between body area
Sub- uptake zone can be absorbed between device body area due to the excess carriers that heavy ion generates, to improve power half
The anti-SEGR abilities of conductor device.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (11)
1. a kind of power semiconductor, which is characterized in that including：
The semiconductor layer of first kind doping；
Positioned at the gate structure of the semiconductor layer surface；
The body area of Second Type doping in the semiconductor layer of the gate structure both sides；
The Carriers Absorption area in semiconductor layer between the body area.
2. power semiconductor according to claim 1, which is characterized in that the surface in the Carriers Absorption area and institute
It is coplanar to state semiconductor layer surface.
3. power semiconductor according to claim 1, which is characterized in that the Carriers Absorption area edge with it is described
Minimum range between body area is more than 0 and is less than or equal to 2 μm.
4. power semiconductor according to claim 1, which is characterized in that the Carriers Absorption area is Second Type
Doping.
5. power semiconductor according to claim 1, which is characterized in that the doping depth in the Carriers Absorption area
Less than or equal to the doping depth in the body area.
6. power semiconductor according to claim 1, which is characterized in that the doping concentration in the Carriers Absorption area
For 1e12cm-3~1e18cm-3。
7. power semiconductor according to claim 1, which is characterized in that mixed in uptake zone in the Carriers Absorption area
It is miscellaneous to have heavy metal ion.
8. power semiconductor according to claim 7, which is characterized in that the doping concentration of the heavy metal ion is
5e13cm-3~5e15cm-3。
9. power semiconductor according to claim 1, which is characterized in that the semiconductor layer includes at least one layer of the
The epitaxial layer of one type doping.
10. power semiconductor according to claim 1, which is characterized in that the Carriers Absorption area includes multiple
Discrete sub- uptake zone.
11. power semiconductor according to claim 10, which is characterized in that between the adjacent sub- uptake zone
It is smaller than 2 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810650267.3A CN108649073A (en) | 2018-06-22 | 2018-06-22 | Power semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810650267.3A CN108649073A (en) | 2018-06-22 | 2018-06-22 | Power semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108649073A true CN108649073A (en) | 2018-10-12 |
Family
ID=63753090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810650267.3A Pending CN108649073A (en) | 2018-06-22 | 2018-06-22 | Power semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108649073A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4656493A (en) * | 1982-05-10 | 1987-04-07 | General Electric Company | Bidirectional, high-speed power MOSFET devices with deep level recombination centers in base region |
| US5262336A (en) * | 1986-03-21 | 1993-11-16 | Advanced Power Technology, Inc. | IGBT process to produce platinum lifetime control |
| CN1505170A (en) * | 2002-11-29 | 2004-06-16 | ���µ�����ҵ��ʽ���� | SiC-MISFET and method for fabricating the same |
| JP2004179501A (en) * | 2002-11-28 | 2004-06-24 | Sharp Corp | Semiconductor film, its manufacturing method, semiconductor device, its manufacturing method, and semiconductor manufacturing apparatus |
| US20110057202A1 (en) * | 2009-09-09 | 2011-03-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| CN102931093A (en) * | 2012-11-21 | 2013-02-13 | 杭州士兰集成电路有限公司 | N-channel depletion type power MOSFET device and manufacturing method thereof |
| JP2015095534A (en) * | 2013-11-12 | 2015-05-18 | 住友重機械工業株式会社 | Method for manufacturing semiconductor device and device for manufacturing semiconductor |
| US20160240649A1 (en) * | 2015-02-13 | 2016-08-18 | The United States Of America As Represented By The Secretary Of The Navy | Controlling current or mitigating electromagnetic or radiation interference effects using multiple and different semi-conductive channel regions generating structures |
| CN106653856A (en) * | 2016-12-14 | 2017-05-10 | 中国电子科技集团公司第四十七研究所 | VDMOS device capable of resisting single event burnout and manufacturing method of VDMOS device |
| CN107331707A (en) * | 2017-06-29 | 2017-11-07 | 电子科技大学 | VDMOS device with anti-single particle effect |
| CN208271906U (en) * | 2018-06-22 | 2018-12-21 | 重庆平伟实业股份有限公司 | Power semiconductor |
-
2018
- 2018-06-22 CN CN201810650267.3A patent/CN108649073A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4656493A (en) * | 1982-05-10 | 1987-04-07 | General Electric Company | Bidirectional, high-speed power MOSFET devices with deep level recombination centers in base region |
| US5262336A (en) * | 1986-03-21 | 1993-11-16 | Advanced Power Technology, Inc. | IGBT process to produce platinum lifetime control |
| JP2004179501A (en) * | 2002-11-28 | 2004-06-24 | Sharp Corp | Semiconductor film, its manufacturing method, semiconductor device, its manufacturing method, and semiconductor manufacturing apparatus |
| CN1505170A (en) * | 2002-11-29 | 2004-06-16 | ���µ�����ҵ��ʽ���� | SiC-MISFET and method for fabricating the same |
| US20110057202A1 (en) * | 2009-09-09 | 2011-03-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| CN102931093A (en) * | 2012-11-21 | 2013-02-13 | 杭州士兰集成电路有限公司 | N-channel depletion type power MOSFET device and manufacturing method thereof |
| JP2015095534A (en) * | 2013-11-12 | 2015-05-18 | 住友重機械工業株式会社 | Method for manufacturing semiconductor device and device for manufacturing semiconductor |
| US20160240649A1 (en) * | 2015-02-13 | 2016-08-18 | The United States Of America As Represented By The Secretary Of The Navy | Controlling current or mitigating electromagnetic or radiation interference effects using multiple and different semi-conductive channel regions generating structures |
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