CN108630632B - 用于改进的集成电路封装的方法和装置 - Google Patents

用于改进的集成电路封装的方法和装置 Download PDF

Info

Publication number
CN108630632B
CN108630632B CN201810198394.4A CN201810198394A CN108630632B CN 108630632 B CN108630632 B CN 108630632B CN 201810198394 A CN201810198394 A CN 201810198394A CN 108630632 B CN108630632 B CN 108630632B
Authority
CN
China
Prior art keywords
package
leadframe
solder joint
die
molding compound
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810198394.4A
Other languages
English (en)
Other versions
CN108630632A (zh
Inventor
M·涩谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN108630632A publication Critical patent/CN108630632A/zh
Application granted granted Critical
Publication of CN108630632B publication Critical patent/CN108630632B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29006—Layer connector larger than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本申请公开了用于改进的集成电路封装的方法和装置。在描述的示例(图7C)中，集成电路(IC)封装(700)包括放置在管芯附接焊盘上的IC管芯；电连接至IC管芯上的端子的多个引线，该引线包括基底金属；以及模塑化合物材料(712)，该模塑化合物材料(712)封装部分的IC管芯、管芯附接焊盘和多个引线；具有焊料接合加强片(725)的多个引线。焊料接合加强片(725)包括第一侧面(725‑I)、与第一侧面相对的第二侧面(725‑II)、第三侧面(725‑III)、与第三侧面相对并且平行于第三侧面的第四侧面(725‑IV)，形成焊料接合加强片的末端部分的第五侧面，焊料接合加强片包括第二、第三和第四侧面上和第五侧面的部分上的可焊接金属层(720)。

Description

用于改进的集成电路封装的方法和装置
技术领域
本公开总体涉及集成电路封装，并且更具体地涉及集成电路封装上的焊料接合加强片的形成。
背景技术
引线框架条带用于制造封装的集成电路。引线框架条带由通过切割槽(sawstreet)连接在一起的多个个体的引线框架组成。嵌入式引线框架条带是引线框架条带，集成电路管芯被附接至该引线框架条带，并被嵌入模塑化合物中。引线框架条带包括具有导电引线框架引线的引线框架和用于附接集成电路管芯的管芯附接焊盘。导电引线框架引线可被机械地连接用于处理中的稳定性，但在封装过程的完成之前其被电分离。集成电路管芯上的端子在封装的集成电路的完成之前被电连接到引线框架引线。在一些封装的集成电路中，键合线被使用以将集成电路管芯上的端子耦合到引线框架的引线。在其它封装的集成电路中，集成电路管芯上的端子使用导电焊料球或焊料柱被直接地安装到引线框架的引线。
封装的集成电路(PIC)(诸如小型无引线(SON)PIC和方形扁平无引线(QFN)PIC)通过以下步骤来封装：使用管芯附接材料将IC管芯附接至金属引线框架条带，制作从IC管芯到引线框架引线的电连接，将IC管芯和引线框架条带封装在模塑化合物中，并且然后通过锯切或激光切割，切割通过切割槽，分离个体的封装，从而切单个体的SON或QFN封装，该操作称为“切单(singulation)”。然后可通过其它方式将切单的SON PIC或QFN PIC焊接或电连接至成为一块电子设备的印刷电路板(PCB)上的引线。SON或QFN封装被称为“无引线”封装，因为用于在PIC和印刷电路板之间的电连接的引线框架的引线被定位在PIC的外围处，并且不像在诸如J-引线和双列直插式(DIP)封装的在前封装中那样延伸离开封装，节省了电路板上的面积。典型地，在PIC的端子和印刷电路板上的迹线之间形成焊料连接。QFN和SON封装在板面积上仅比集成电路管芯稍大，并且有时被称为“接近芯片级”封装，使末端设备中更小的电路板尺寸和更高的集成成为可能。
引线框架条带通常由基底金属(base metal)(诸如铜或镀有可焊接金属层的铜合金)制成。引线框架条带有时被称为“预镀的”引线框架条带，因为可以由引线框架制造商在引线框架条带上提供可焊接金属层。一种这样的可焊接金属层是电镀镍层，随后是电镀钯层。有时使用化学镀和电镀金属层。其他可焊接金属包括银、锡、金、铂、焊料及其合金。可焊接金属层意在防止引线框架基底金属的氧化，当基底金属暴露于空气中时发生这种氧化。焊料不能适当地润湿(wet)形成的任何氧化层，并且焊料不能形成到被氧化的基底金属的可靠的焊料接合。
在封装的集成电路的切单期间，切穿了可焊接金属层和引线框架条带的基底金属。引线框架的基底金属在切单过程中被暴露在PIC的侧壁上，并且当暴露于空气中时可能氧化。因此，改进是可取的。
发明内容
在所描述的示例中，集成电路(IC)封装包括放置在管芯附接焊盘上的IC管芯；电连接至IC管芯上的端子的多个引线，多个引线的每个包括基底金属；以及模塑化合物材料，该模塑化合物材料封装部分的IC管芯、管芯附接焊盘和多个引线；具有从IC封装的外围延伸的焊料接合加强片的多个引线。焊料接合加强片包括：在第一方向纵向延伸的第一侧面，与第一侧面相对并且平行于第一侧面的第二侧面，被定向在垂直于第一方向的第二方向的第三侧面，与第三侧面相对并且平行于第三侧面的第四侧面，形成焊料接合加强片的末端部分的第五侧面，焊料接合加强片包括在第二、第三和第四侧面上以及第五侧面的部分上的可焊接金属层。
附图说明
图1A和图2A是示出的在切单以前的具有集成电路管芯的引线框架条带的部分的横截面。
图1B和图2B是示出的在切单以后的具有集成电路管芯的引线框架条带的部分的横截面。
图3是焊接到印刷电路板(PCB)上的引线的集成电路封装的部分的横截面。
图4A和图4B是集成电路封装的透视视图。
图5是用于形成具有焊料接合加强片的集成电路封装的实施例方法的流程图。
图6A和图6B是说明用于形成焊料接合加强片的实施例切单步骤的横截面。
图7A至图7E在一系列视图中说明了用于形成水平焊料接合加强片和用于形成加固的水平焊料接合的方法实施例。
图8A至图8D在一系列透视视图中说明了用于形成垂直焊料接合加强片和用于形成加固的垂直焊料接合的附加的方法实施例。
具体实施方式
不同图中相应的数字和符号一般是指相应的部分，除非另有说明。图不是必须地按比例绘制的。
图1A是示出引线框架条带108的横截面。在此处图中，引线框架条带被示出为具有面向上的前侧表面，IC管芯被安装在该表面上。相对的表面，引线框架条带的背侧表面，在图中被示出为面向下，部分的背侧表面可以形成IC封装的外部端子。然而，图中所示的设备的定向是用于解释的，并且不影响实施例的操作。图1A中引线框架条带108被示出具有附接至引线框架条带108的前侧表面的两个IC管芯110。ID管芯由管芯附接材料114键合到引线框架管芯安装焊盘102。键合线122将集成电路管芯110的端子116电连接至引线框架引线104。部分的IC管芯110、键合线122和引线框架条带108被封装在模塑化合物112中。管芯安装焊盘102的背侧表面和引线框架引线104的背侧表面没有用模塑化合物112封装。引线框架条带108包括在基底金属上的可焊接金属层120。引线框架条带108可被提供给封装过程，其包括预镀的材料，该预镀的材料包括可焊接金属层120。可替代地，在封装过程中可焊接金属层120可以在之前的步骤(未显示)被应用于引线框架条带108的基底金属。集成电路管芯110通过切割槽112被彼此隔开。切割槽112是引线框架条带108和模塑化合物112的限定区域，其中集成电路器件可在以后的过程步骤中通过切割穿过切割槽被分离。在引线框架引线104和管芯安装焊盘102的背侧表面上的暴露的可焊接金属层120形成外部PIC端子124和126(见图1B)。当PIC为了使用被安装时，焊料接合(图1A中未示出)将被用于将这些外部PIC端子124和126电连接至印刷电路板(PCB)上的引线。
图1B是显示在由锯切或激光切割或其他方法移除切割槽118(图1A)以切单(切单是将安装到引线框架条带的多个经模塑的IC管芯分离成为单个封装的IC的过程)PIC 100之后，图1A的两个PIC 100的横截面。切单过程切割穿过模塑化合物112、可焊接金属层120和引线框架条带108的基底金属，在PIC 100上形成侧壁。机械锯切、激光切割工具，和其他方法可以用来切单PIC 100。切单可以用一种工具进行或者可替代地，切单可以用一种以上类型的工具或通过在多个步骤中执行的方法进行。
图2A是示出两个集成电路管芯210的横截面，该两个集成电路管芯210使用球键合214被“倒装芯片”安装(使用面向下的端子216安装集成电路管芯)到引线框架条带208的引线框架引线204。在图2A-2B中，为了清楚起见，对于图1A-1B中所示的相似的元件使用相似的参考标记。例如，图1A-1B中的模塑化合物112对应于图2A-2B中的模塑化合物212。在倒装芯片安装中，当与引线键合封装(其中端子116被布置成背对引线框架108表面(见图1A))相比时，集成电路管芯被描述为“倒装的”。部分的引线框架条带208、IC管芯210和球键合214被封装在模塑化合物212中。这两个PIC 200是由切割槽218接合在一起。注意，如图2A所示在倒装芯片安装的封装中，没有管芯焊盘，且没有附接至管芯焊盘，管芯210在端子216处由引线框架208支撑。散热板(heat slug)或其他热导体可用于从管芯210制作热通路。在另一种方法中，热导电填料颗粒可以被并入模塑化合物212以改善从管芯210的热传导。
图2B是示出在通过锯切或激光切割移除切割槽218(图2A)以切单PIC 200之后的图2A的两个PIC 200的横截面。锯切切割穿过模塑化合物212、可焊接金属层220和引线框架条带208的基底金属以在切单的PIC 200上形成侧壁。引线框架焊盘204的底部表面未用模塑化合物212封装。引线框架焊盘204的底部表面上的可焊接金属220保持暴露并形成外部PIC端子224和226(见图2B)，该外部PIC端子224和226用于将PIC 200附接至PCB(未示出)上的引线。
引线框架条带108(图1A)和208(图2A)典型地由诸如铜或铜合金的基底金属制成，该基底金属镀有可焊接金属层，如120和220所示。一种这样的可焊接金属层是电镀的镍层，然后是电镀的钯层。其它可焊接金属包括银、锡、金、铂、焊料及其合金。使用ENIG(化学镀镍/浸金)、ENEPIG(化学镀镍/化学镀钯/浸金)和其它化学镀和电镀金属层。有时在可焊接金属层中使用多层交替材料以降低铜离子从基底金属迁移通过化学镀或电镀可焊接材料的可能性。可焊接金属层120和220防止当基底金属暴露于空气时发生的引线框架基底金属的氧化。当发生氧化时，当之后使用焊料安装过程将PIC安装到印刷电路板(PCB)时，焊料不能适当地润湿氧化层并形成可靠的焊料接合。
如图1B和2B中的横截面所示，在引线框架条带和模塑化合物的切单期间，可焊接金属层120和220以及引线框架条带108和208的基底金属通过锯切或激光切割被切割穿过。然后，图1A-1B和图2A-2B中的引线框架108和208的基底金属在切单期间被暴露在PIC 100和PIC 200的侧壁上，并且暴露的基底金属随后在暴露于空气时可被氧化。
图3是用焊料接合328和330被焊接到印刷电路板(PCB)334的PIC 300的横截面。注意在图3中，为了清楚起见，对于图1A-1B中示出的相似的元件使用相似的参考标记。例如，图3中的集成电路管芯310对应于图1A-1B中的集成电路管芯110。集成电路管芯310包括端子316。管芯附接314将IC管芯310附接至引线框架条带308的管芯焊盘302。键合线322将端子316电连接至引线框架引线304。模塑化合物312部分地封装集成电路管芯310、键合线322、包括管芯焊盘302和引线框架引线304的引线框架条带308。焊料接合328和330将PIC300的底部上的外部PIC端子324和326连接至PCB 334的表面上的导电引线336。可焊接金属层320覆盖引线框架条带307的背侧表面，并且端子324、326包括可焊接层320。如图3所示，氧化层332可以形成在引线框架引线304的垂直侧面上，其中在切单期间基底金属被暴露。焊料330不润湿氧化层332，防止形成坚固、可靠的焊料接合330。
图4A是PIC 400的透视图。图4A示出在切单期间暴露的PIC 400的侧壁。切单切割形成侧壁(参见图1B和图2B中的PIC 100和PIC 200)，其包括模塑化合物412中的垂直表面和引线框架引线404中的垂直表面。可焊接金属层420包住引线框架引线404，除了在切单期间暴露的引线框架引线404的基底金属的侧壁之外。被暴露在PIC 400的侧壁上的引线框架引线404的侧壁包括当暴露于空气时氧化的基底金属。
图4B是示出在引线框架引线404的底部上的外部端子与PCB 434上的导电引线之间形成焊料接合430之后的图4A的PIC 400的透视图。(在图4B中，外部端子和在PCB 434上的导电引线不可见，因为在该视图中焊料430覆盖导电引线)。焊料430润湿覆盖外部PIC端子的可焊接金属420，但是不润湿或粘附至形成在引线框架引线404的侧壁上的暴露的基底金属上的氧化层(例如，参见图3中的332)。这种焊料接合(如图3和图4B中分别示出的330和430)可能是弱的，并且可能脱层，导致PCB集成电路失效。当使用PCB时可能发生的脱层可导致末端设备的现场故障，需要修理或更换末端设备。
图5是在PIC的制造中使用具有焊料接合加强片(SJRT)的实施例的主要步骤的流程图。
在步骤502中，在切割槽中从嵌入式引线框架条带的前侧制作第一切口。第一切口延伸穿过切割槽中的模塑化合物并且进入切割槽中的引线框架条带的前侧表面。在一个示例实施例中，使用宽的切单锯条制作切口。(在可替代的实施例中，也可以使用激光切割，或者在另一个可替代的实施例中，可以使用利用更窄的锯条的多次通过来形成宽切口。此外，可以使用执行第一切口的其它方法)。典型地，当从引线框架条带的前侧切割时，可支撑嵌入式引线框架条带的背侧。一种这样的支撑方式是胶带(tape)。
图6A是示出步骤502的结果的横截面。注意，为了清楚起见，在图6A-图6B中使用的参考标记相似于图1A-图1B中所示的相似元件。例如，图6A中的模塑化合物612对应于图1A中的模塑化合物112。图6A示出了由切割槽618接合在一起的两个PIC 600。首先从嵌入式引线框架条带608的前侧切割切割槽618中的模塑化合物612和引线框架608，留下切割槽材料618的薄带621。在该示例实施例中，切割槽618的薄带621具有在第一切口后剩余的大约40μm+/-10μm的厚度“T”，连接两个PIC 600的底部。在另外的可替代的实施例中，带621的厚度T可以变化。在一个示例实施例中，第一切口由切单锯条制作，在一个示例中，所使用的切单锯条是300μm宽。薄带621包括引线框架材料的薄部分(在图6A中可见)，并且还包括在切割槽618中的第一切口之后留下的模塑化合物材料(在图6A的横截面中不可见)。来自引线框架条带的前侧的切口将在切割槽618中的薄带621中的引线框架条带的基底金属暴露，因为进入引线框架条带608中的切口从在其中制作切口的引线框架条带的前侧移除可焊接金属620。在图6A中，IC管芯610通过管芯附接614被附接至引线框架管芯安装焊盘602。管芯610上的端子616使用引线键合622被电连接至引线框架引线604。引线框架608的基底金属的表面被涂有可焊接金属层620。部分的IC管芯610、引线框架管芯安装焊盘602和引线框架引线604以及引线键合616被封装在模塑化合物612中以形成具有由切割槽618接合在一起的PIC600的嵌入式引线框架条带。管芯安装焊盘602和引线框架引线604的背侧表面未由模塑化合物612封装，并且这些暴露的部分形成外部PIC端子624和626。在这些外部PIC端子624和626与PCB(图6A-图6B中未示出)上的引线之间将制成的焊料接合被用来将PIC 600安装在PCB上。
返回图5，在步骤504中，制作穿过切割槽621的薄带的第二切口。该步骤完全地分离PIC 600；也就是说，它是切单步骤。切割槽材料664的薄突出部(ledge)保持附接至PIC600的底部并围绕PIC 600的底部。在一个实施例中，从引线框架条带的背侧制作第二切口。在一种方法中，使用切单锯。在一个可替代的方法中，使用激光切割操作。
图5中的步骤504的结果在图6B的横截面中示出。在第二切割步骤中切割穿过剩余切割槽618的薄带621的中心，完成PIC 600的切单。在步骤502中，第二切口比第一切口更窄。切单之后，切割槽材料的薄突出部664保持附接至PIC 600的底部并围绕PIC 600的底部。在一个示例实施例中，切单锯被用于制作第二切口。在一个示例实施例中，用于制作这个切口的薄切单刀片约为200μm宽。在一个可替代的实施例中，可以使用激光切割。在该第二次切割之后，附接至每个PIC的剩余切割槽材料的突出部664具有如图6B中的L所示的长度，该长度是从PIC的外部边界测量的大约50μm+/-20μm长，并且突出部664具有大约40μm+/-10μm厚的图6A中所示的厚度T。当薄的剩余带623从背侧(如图中画出的引线框架条带的下表面)切割穿过时，典型地支撑嵌入式引线框架条带的前侧(如图中画出的上表面)。一种这样的支撑方式是胶带(tape)。
如参见图6B，实施例包括在PIC 600的引线626的突出部664中形成的焊料接合加强片。如下面进一步描述的，焊料接合加强片提供可焊接金属层620的附加区域，以提供用于焊料的增加的可润湿区域，以在PIC的外部端子和PCB之间形成可靠的焊料接合。注意，形成由于实施例的第一切割操作和第二切割操作导致的表面的在突出部664中的焊料接合加强片的部分不被可焊接金属层620覆盖，因为切割操作暴露引线框架条带608的基底金属。
图7A-图7E在一系列视图中示出了形成实施例的方法。注意，在图7A-图7E中，为了清楚起见，对于图6A-图6B中所示的相似元件使用相似的参考标记。例如，模塑化合物712对应于图6A-图6B中的模塑化合物612。
图7A是示出在切单处理之后的PIC 700的侧壁的透视图。围绕PIC 700的基底的切割槽材料的突出部764由焊料接合加强片(SJRT)725组成，其中模塑化合物723的部分留在SJRT 725之间。
再次参照图5，在步骤506中，剩余在SJRT 725之间的模塑化合物材料723被移除。
图7B在透视图中说明了在执行图5中的步骤506之后的一个实施例。在SJRT 725之间的剩余模塑化合物材料723(参见图7A)可以通过激光切割移除，或者可以通过对模塑化合物部分723施加压力并折断它们来移除。
在图7B中，SJRT 725在SJRT的部分上显示有可焊接的金属层720。这分别在图7C-图7D所示的PIC 700的右侧视图和前侧视图中进一步显示。
在图7C中，在图7B的透视图中的PIC 700被显示在右侧视图中。在图7C中，视图查看SJRT 725的末端部分(参见图7B)。如图7C所示，SJRT 725具有标记为725-I的第一侧面，其对应于引线框架条带的前侧部分，其中基底金属在步骤502中通过第一切割操作被暴露。第一侧面在第一方向纵向延伸，远离PIC 700的基底的外围。相对的第二侧面725-II平行于第一侧面，并由可焊接金属720覆盖，第二侧面对应于引线框架条带708的背侧表面。第三侧面725-III被定向在垂直于第一侧面725-I的第一方向的第二方向，并由可焊接金属层720覆盖，以及相对的第四侧面725-IV平行于第三侧面725-III并且也由可焊接金属层720覆盖。SJRT 725的第五侧面，由步骤504的第二切割操作形成的SJRT 725的末端部分，在图7D的前侧视图中被标记为725-V。如图7B和图7C所示，该第五侧面由可焊接金属层720部分地覆盖，并且还包括通过第二切割操作暴露的引线框架条带708的基底金属。由于SJRT 725远离PIC在平行于PIC 700的基底的方向延伸，这些SJRT 725可以被描述为相对于PIC 700的“水平的SJRT”。
图7E在投影视图中显示PIC 700，其包括在焊接到PCB 734之后的SJRT 725。SJRT725的底部表面和侧面被涂有可焊接材料(在图7E中不可见)，因此焊料容易形成到SJRT725的底部和侧面的焊料接合。焊料接合730将PCB 734上的导电引线(在图7E中被遮蔽不可见)连接至PIC 700的底部上的外部端子(在图7E中被遮蔽不可见，例如，见图6B中的624、626)，并且也连接至SJRT 725的底部和侧面。在PCB 734上的引线与SJRT 725的底部和侧面之间的扩大的焊料接合730(当与不使用实施例而在PIC引线上形成的焊料接合相比时)显著地增强焊料接合730，并显著地减少了PCB安装的封装集成电路的故障。这些优点在很少额外成本的情况下实现。
再次参照图5，可选的步骤508可以被执行(在图8A至图8D中的一系列透视图中示出)。在图8A至8D中，为了清楚起见，对于图6A-图6B中所示的相似元件使用相似的参考标记。例如，模塑化合物812对应于图6A-图6B中的模塑化合物612。图8A-图8D在一系列透视图中示出了过程，其中SJRT 825从初始水平位置被弯曲到垂直位置，以与PIC 800的侧壁并排并且抵靠PIC 800的侧壁结束。该方法减少了PIC 800的占用区(footprint)(PCB的板面积)，并且还增加了焊料接合830的强度和可靠性(参见图8D)。因为SJRT在过程中向上被弯曲，所以SJRT 825可以被描述为关于PIC 800的“垂直的SJRT”。
在图8A中，将具有围绕PIC 800的基底的切割槽材料的突出部864的PIC 800放置在制动台854上。切割槽材料的突出部864由SJRT 825组成，其中模塑化合物823的部分留在SJRT 825之间。
在图8B中，制动器856通过铰链(hinge)852被连接至制动台854，制动器856被升高以向切割槽材料的突出部864施加向上的压力。这将SJRT 825从水平定向弯曲到抵靠PIC800的垂直侧壁的垂直定向。向上的压力还导致留在SJRT 825之间的模塑材料823的部分折断。在另一个可替代的实施例中，如果期望，可在弯曲SJRT 825之前使用激光切割移除模塑材料823的部分。
在图8C中，示出在弯曲操作完成之后的PIC 800。所示的SJRT 825现在垂直地定向并位于与PIC 800的侧壁并排。SJRT 825的垂直底部表面和侧面被涂有可焊接层820。
如图8D所示，当具有垂直SJRT 825的PIC 800被焊接到PCB 834上的引线时，显著地更高的焊料接合830被形成。焊料接合830的增加的高度提供了增加的强度和可靠性。
在此处展现的用于说明实施例的所描述的示例示出了QFN集成电路封装。然而，实施例并不限于此，并且实施例的方法和布置可以被应用于期望增加焊料接合可靠性的其它封装类型。
在所描述的实施例中修改是可能的，并且在权利要求的范围内，其它可替代的实施例是可能的。

Claims (20)

1.一种集成电路封装即IC封装，其包含：
IC管芯，其被放置在管芯附接焊盘上；
多个引线，其被电连接至所述IC管芯上的端子，所述多个引线中的每一个包括基底金属；以及
模塑化合物材料，其封装部分的所述IC管芯、所述管芯附接焊盘和所述多个引线；
所述多个引线具有从所述IC封装的外围延伸的焊料接合加强片，其中所述外围包括所述多个引线中的每一个的表面，所述表面与所述模塑化合物的表面齐平，所述焊料接合加强片包括在第一方向纵向延伸的第一侧面、与所述第一侧面相对并且平行于所述第一侧面的第二侧面、被定向在垂直于所述第一方向的第二方向的第三侧面、与所述第三侧面相对并且平行于所述第三侧面的第四侧面、形成所述焊料接合加强片的末端部分的第五侧面，所述焊料接合加强片包括所述第二、第三和第四侧面上以及所述第五侧面的部分上的可焊接金属层。
2.根据权利要求1所述的IC封装，其中，所述IC封装是选自小型无引线封装即SON封装和方形扁平无引线封装即QFN封装中的一种。
3.根据权利要求1所述的IC封装，其中，所述焊料接合加强片包括从IC封装的所述外围向外延伸的引线框架材料。
4.根据权利要求1所述的IC封装，其中，所述焊料接合加强片包括所述可焊接金属层，所述可焊接金属层包括选自镍、金、钯及其合金中的至少一种。
5.根据权利要求1所述的IC封装，其中，所述焊料接合加强片具有在约30μm至50μm的范围内的厚度。
6.根据权利要求1所述的IC封装，其中，所述焊料接合加强片具有从所述IC封装的所述外围延伸的在约30μm至70μm的范围内的长度。
7.根据权利要求1所述的IC封装，其中，部分的所述焊料接合加强片从所述IC封装的基底水平地向外突出。
8.根据权利要求1所述的IC封装，其中，部分的所述焊料接合加强片从所述IC封装的所述基底向外突出，并且与所述IC封装的垂直侧壁并排延伸。
9.一种集成电路封装即IC封装，其包含：
封装附接至管芯焊盘的IC管芯的部分的模塑化合物、由引线框架材料形成的引线以及在所述IC管芯的端子和由引线框架材料形成的所述引线之间形成的电连接；以及
焊料接合加强片，其从所述IC封装的所述引线中的一个向外突出，其中所述焊料接合加强片具有被纵向定向在第一方向的第一侧面、与所述第一侧面相对并且与所述第一侧面平行的第二侧面、被定向在垂直于所述第一侧面的第二方向的第三侧面、与所述第三侧面相对并且与所述第三侧面平行的第四侧面、以及形成所述焊料接合加强片的末端部分的第五侧面，并且所述焊料接合加强片包括引线框架基底金属，所述引线框架基底金属具有在所述第二侧面、第三侧面和第四侧面上和所述第五侧面的一部分上的可焊接金属层，其中所述封装的所述引线中的一个包括与所述模塑化合物的表面齐平的表面。
10.根据权利要求9所述的IC封装，其中，所述焊料接合加强片包括切割槽引线框架材料。
11.根据权利要求9所述的IC封装，其中，所述焊料接合加强片包括所述可焊接金属层，所述可焊接金属层是选自：镍层、金层、钯层和镍层加钯层中的一种。
12.根据权利要求9所述的IC封装，其中，所述焊料接合加强片具有在约30μm至50μm的范围内的厚度。
13.根据权利要求9所述的IC封装，其中，所述焊料接合加强片具有从所述IC封装的外围在所述第一方向纵向延伸的约30μm至70μm的长度。
14.根据权利要求9所述的IC封装，其中，所述焊料接合加强片从所述IC封装的基底水平地突出。
15.根据权利要求9所述的IC封装，其中，所述焊料接合加强片与所述IC封装的垂直侧壁并排延伸。
16.一种用于形成集成电路封装即IC封装的方法，其包含：
提供引线框架材料的嵌入式引线框架条带，其具有第一侧面和与所述第一侧面相对的第二侧面，其中集成电路管芯即IC管芯被附接至所述引线框架条带的所述第一侧面并且被封装在模塑化合物材料中，所述集成电路管芯由切割槽区域间隔开；
从所述嵌入式引线框架条带的所述第一侧面，在所述IC管芯中的IC管芯之间的切割槽中，制作第一宽度的第一切口穿过所述模塑化合物并且进入所述引线框架条带的所述第一侧面，在邻近的IC管芯之间的所述切割槽中留下所述引线框架材料和模塑化合物材料的薄带；
穿过在所述切割槽中的所述引线框架材料和模塑化合物材料的所述薄带，制作小于所述第一宽度的第二宽度的第二切口，以形成由多个焊料接合加强片组成的切割槽材料的突出部，该多个焊料接合加强片由模塑化合物材料分开；并且
从所述焊料接合加强片之间移除所述模塑化合物材料，
其中所述焊料接合加强片具有被定向在第一方向的第一侧面，与所述第一侧面相对并且与所述第一侧面平行的第二侧面，被定向在垂直于所述第一侧面的第二方向的第三侧面，与所述第三侧面相对并且与所述第三侧面平行的第四侧面，以及形成所述焊料接合加强片的末端部分的第五侧面，所述第二侧面、第三侧面和所述第四侧面被可焊接金属层覆盖，并且所述第五侧面被所述可焊接金属层部分地覆盖。
17.根据权利要求16所述的方法，其中，所述引线框架材料和模塑化合物材料的所述薄带具有在30μm至50μm的范围内的厚度。
18.根据权利要求16所述的方法，其中，所述焊料接合加强片具有从所述IC封装的外围在第一方向纵向延伸的在约30μm至70μm的范围内的长度。
19.根据权利要求18所述的方法，进一步包括将所述焊料接合加强片弯曲成抵靠所封装的集成电路的所述模塑化合物的侧面的垂直定向。
20.根据权利要求16所述的方法，其中，所封装的集成电路是方形扁平无引线封装即QFN封装的集成电路。
CN201810198394.4A 2017-03-19 2018-03-12 用于改进的集成电路封装的方法和装置 Active CN108630632B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/462,881 US11004742B2 (en) 2017-03-19 2017-03-19 Methods and apparatus for an improved integrated circuit package
US15/462,881 2017-03-19

Publications (2)

Publication Number Publication Date
CN108630632A CN108630632A (zh) 2018-10-09
CN108630632B true CN108630632B (zh) 2024-04-26

Family

ID=63520725

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810198394.4A Active CN108630632B (zh) 2017-03-19 2018-03-12 用于改进的集成电路封装的方法和装置

Country Status (2)

Country Link
US (2) US11004742B2 (zh)
CN (1) CN108630632B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109788643A (zh) * 2017-11-10 2019-05-21 泰连公司 铝基可焊接的触头
US20190287918A1 (en) * 2018-03-13 2019-09-19 Texas Instruments Incorporated Integrated circuit (ic) packages with shields and methods of producing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060180904A1 (en) * 2005-02-14 2006-08-17 Stats Chippac Ltd. Non-leaded integrated circuit package system
CN101133491A (zh) * 2004-12-30 2008-02-27 德州仪器公司 不含铅且多层被预镀敷的引线框
CN101834166A (zh) * 2009-03-09 2010-09-15 Asat有限公司 具有支架触点以及管芯附垫的无引脚集成电路封装
US20140306330A1 (en) * 2013-03-09 2014-10-16 Adventive Ipbank Low Profile Leaded Semiconductor Package

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7691676B1 (en) 2008-11-14 2010-04-06 Powertech Technology Inc. Mold array process for semiconductor packages
US8400784B2 (en) * 2009-08-10 2013-03-19 Silergy Technology Flip chip package for monolithic switching regulator
US20140357022A1 (en) 2013-06-04 2014-12-04 Cambridge Silicon Radio Limited A qfn with wettable flank

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101133491A (zh) * 2004-12-30 2008-02-27 德州仪器公司 不含铅且多层被预镀敷的引线框
US20060180904A1 (en) * 2005-02-14 2006-08-17 Stats Chippac Ltd. Non-leaded integrated circuit package system
CN101834166A (zh) * 2009-03-09 2010-09-15 Asat有限公司 具有支架触点以及管芯附垫的无引脚集成电路封装
US20140306330A1 (en) * 2013-03-09 2014-10-16 Adventive Ipbank Low Profile Leaded Semiconductor Package

Also Published As

Publication number Publication date
US20180269135A1 (en) 2018-09-20
CN108630632A (zh) 2018-10-09
US20210265214A1 (en) 2021-08-26
US11004742B2 (en) 2021-05-11

Similar Documents

Publication Publication Date Title
US7368328B2 (en) Semiconductor device having post-mold nickel/palladium/gold plated leads
JP6129645B2 (ja) 半導体装置および半導体装置の製造方法
TWI587457B (zh) 樹脂密封型半導體裝置及其製造方法
TWI291756B (en) Low cost lead-free preplated leadframe having improved adhesion and solderability
US8685795B2 (en) Flank wettable semiconductor device
JP5100967B2 (ja) リードフレーム、これを利用した半導体チップパッケージ及びその製造方法
US9385072B2 (en) Method of manufacturing semiconductor device and semiconductor device
US9059185B2 (en) Copper leadframe finish for copper wire bonding
JP2014007363A (ja) 半導体装置の製造方法および半導体装置
WO2008027694A2 (en) Stackable packages for three-dimensional packaging of semiconductor dice
US20210265214A1 (en) Methods and apparatus for an improved integrated circuit package
US9553068B2 (en) Integrated circuit (“IC”) assembly includes an IC die with a top metallization layer and a conductive epoxy layer applied to the top metallization layer
US9099484B2 (en) Method of manufacturing semiconductor device
US20140097527A1 (en) Method of manufacture integrated circuit package
JP2017108191A (ja) 半導体装置
JP2004335947A (ja) 半導体装置及び半導体装置の作製方法
JP4311294B2 (ja) 電子装置およびその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant