US20140097527A1 - Method of manufacture integrated circuit package - Google Patents

Method of manufacture integrated circuit package Download PDF

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Publication number
US20140097527A1
US20140097527A1 US13/644,647 US201213644647A US2014097527A1 US 20140097527 A1 US20140097527 A1 US 20140097527A1 US 201213644647 A US201213644647 A US 201213644647A US 2014097527 A1 US2014097527 A1 US 2014097527A1
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United States
Prior art keywords
leadframe
shunt
integrated circuit
tape
circuit device
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Granted
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US13/644,647
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US8697496B1 (en
Inventor
Donald Charles Abbott
Ubol Annie Udompanyavit
Brian Eugene Parks
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Texas Instruments Inc
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Texas Instruments Inc
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Priority to US13/644,647 priority Critical patent/US8697496B1/en
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PARKS, BRIAN EUGENE, ABBOTT, DONALD CHARLES, UDOMPANYAVIT, UBOL ANNIE
Priority to US14/189,874 priority patent/US20140175626A1/en
Publication of US20140097527A1 publication Critical patent/US20140097527A1/en
Application granted granted Critical
Publication of US8697496B1 publication Critical patent/US8697496B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation

Definitions

  • An integrated circuit package serves to physically and electrically connect an integrated circuit device (housed within the integrated circuit package) to a printed circuit board.
  • One type of integrated circuit package is known as a “flat no-leads package”. This type of package is a surface-mount technology that connects an integrated circuit device to surfaces of the printed circuit board without the use of through-holes. Perimeter lands on the package bottom provide electrical connections to the printed circuit board.
  • Flat no-leads packages typically include a planar copper leadframe substrate upon which the integrated circuit device is mounted. The leadframe and the integrated circuit device are typically encapsulated within a molding material.
  • Flat no-lead packages generally include an exposed thermal pad to improve heat transfer out of the integrated circuit device (and into the printed circuit board).
  • QFN quad-flat no-leads
  • DFN dual-flat no-leads
  • a rectangular copper alloy slug or shunt be included in the package with one surface exposed for soldering.
  • FIG. 1 is a plan view of exemplary block of connected leadframe sheets.
  • FIG. 2 is a plan view of one of the leadframe sheets of FIG. 1 .
  • FIG. 3 is a plan view of an exemplary leadframe from the leadframe sheet of FIG. 2 .
  • FIG. 4 is a cross-section view of the leadframe of FIG. 3 , taken along the line 4 - 4 in FIG. 3 .
  • FIG. 5 is a cross-section view similar to that of FIG. 4 , but showing the leadframe of FIG. 3 having tape applied to its lower surface.
  • FIG. 6 is a plan view of the leadframe of FIG. 3 , illustrating a shunt supported on the tape shown in FIG. 5 , an integrated circuit device mounted on a die pad of the leadframe and wirebonding between the integrated circuit device, the shunt and the leadframe.
  • FIG. 7 is a cross-section view of the leadframe of FIG. 6 , taken along the line 7 - 7 in FIG. 6 .
  • FIG. 8 is a perspective view of a completed integrated circuit package.
  • FIG. 9 illustrates by flow diagram, selected steps in an exemplary method for manufacturing an integrated circuit package according to the present disclosure.
  • FIG. 10 illustrates by flow diagram, one embodiment of a method of manufacturing an integrated circuit package.
  • FIG. 11 illustrates by flow diagram, another embodiment of a method of manufacturing an integrated circuit package.
  • a rectangular copper alloy slug or shunt be included in the package with one surface exposed for soldering.
  • the copper alloy used in the shunt may, for example, be of the type sold under the trademark MANGANIN®, and may, for example, have a composition of about 86% copper, 12% manganese, and 2% nickel. Because of the relatively high cost of this alloy, it is advantageous to have the leadframe formed from a less expensive leadframe alloy, for example, the alloy sold under the trade designation “CDA194”. CDA194 is well suited and characterized both thermally and mechanically for use in leadframes. It is also formulated to facilitate stamping and etching of leadframes.
  • an integrated circuit package along with a method of manufacturing the package, are disclosed herein.
  • the disclosed package and method of manufacture provide the ability, for example, to incorporate a slug or shunt made of a more expensive copper alloy (e.g., MANGANIN®) into a package having its leadframe manufactured from a less expensive leadframe alloy.
  • MANGANIN® a more expensive copper alloy
  • the alloy CDA194 is widely used for leadframes and is readily available from rolling mills. MANGANIN®, however, is generally less widely used and available.
  • FIG. 1 illustrates a block 10 of connected leadframe sheets 22 , 24 , 26 , and 28 .
  • FIG. 2 illustrates the leadframe sheet 22 in further detail, it being understood that the remaining leadframe sheets 24 , 26 , and 28 may be substantially identical to the leadframe sheet 22 .
  • the leadframe sheet 22 may include a plurality (e.g., eighty-eight, as depicted in FIG. 2 ) of leadframes 30 including the individual leadframes 32 , 34 , 36 , 38 and 40 .
  • FIG. 3 illustrates the leadframe 40 in further detail, it being understood that the remainder of the leadframes 30 may be substantially identical to the leadframe 40 . It is noted that, for purposes of illustrative efficiency, the package and method of manufacture will be described herein specifically in conjunction with the exemplary leadframe 40 . It is to be understood, however, that the methodology described may be carried out on all of the leadframes 30 while they are still connected to one another in the leadframe sheet 22 and while the leadframe sheets 22 , 24 , 26 , and 28 are still connected to one another in the leadframe block 10 .
  • the leadframe 40 may include a frame portion 42 having an upper surface 44 and an oppositely disposed lower surface 46 ( FIG. 4 ).
  • a plurality of tabs 50 may extend inwardly from the frame 42 , as shown.
  • the tops of the tabs 50 are the targets for wire bonding connections to the integrated circuit device (in a manner that will be described in further detail herein).
  • the right side (as viewed in the orientation of FIG. 3 ) of the leadframe 40 may be occupied by a die mounting pad 70 for mounting an integrated circuit device, in a manner as will be described in further detail herein.
  • the left side of the leadframe 40 may include an open space 80 that extends completely through the leadframe, i.e., the open space 80 extends from the upper surface 44 to the lower surface 46 of the leadframe 40 .
  • the leadframe 40 may be constructed from a relatively inexpensive leadframe alloy, for example, the alloy sold under the trade designation “CDA194”.
  • the leadframe 40 may be constructed of copper or another copper alloy, other metal or metal alloy.
  • tape 90 may be adhered to the lower surface 46 of the leadframe 40 such that it extends beneath the entire extent of the leadframe.
  • Tape 90 may include an upper surface 92 and an oppositely disposed lower surface 94 .
  • the upper surface 92 of the tape 90 may be adhered to the lower surface 46 of the frame portion 42 in areas where the tape 90 underlies the frame portion 42 .
  • the tape 90 may, for example, be either a pressure sensitive adhesive tape or a thermoplastic tape and may have a thickness “A”, for example, of about 2 mil-50 ⁇ m. It is noted that the relative thickness of the tape 90 has been exaggerated in FIG. 5 for purposes of illustrative clarity.
  • a shunt 100 may be inserted into the open space 80 of the leadframe 40 .
  • the shunt 100 may be located such that it does not touch any part of the leadframe frame portion 42 and is supported only by the tape 90 .
  • the shunt 100 may be placed within the open space 80 of the leadframe 40 using conventional die mount, pick and place equipment. It is noted that the shunt 100 may be formed in a large sheet of interconnected shunts (not shown). The shunts may then be separated from one another prior to insertion into the leadframes.
  • the shunt 100 may, for example, be formed from a relatively expensive material such as a copper alloy sold under the trademark MANGANIN®. The shunt may be pre-plated or post-plated, as desired.
  • an integrated circuit device 110 may be mounted to the leadframe 40 , as shown. More specifically, the Integrated circuit device 110 can be attached to the die mounting pad 70 in a conventional manner, using an adhesive material such as epoxy or silver filled epoxy.
  • the integrated circuit device 110 may be electrically connected to the shunt 100 and the leadframe 40 , for example, using bonding wires.
  • Bonding wires 102 and 104 may extend between the shunt 100 and the pads 112 and 114 , respectively, on the integrated circuit device 110 .
  • a bonding wire 106 may extend between the integrated circuit device pad 116 and the top of the leadframe tab 56 .
  • a bonding wire 108 may extend between the integrated circuit device pad 118 and the top of the leadframe tab 58 .
  • FIG. 6 only four bonding wires have been shown in FIG. 6 . It is to be understood, however, that many more bonding wires may be provided to establish the desired connections between the integrated circuit device 110 , the leadframe 40 and shunt 100 .
  • the leadframe 40 , integrated circuit device 110 and shunt 100 may be encapsulated within a molding material (e.g., the molding material 122 , FIG. 8 ) in a conventional manner.
  • the molding material may, for example, be a plastic material such as epoxy or other conventional insulating material.
  • the molding material 122 may be formed in an injection molding process or it may be applied as a coating.
  • the tape 90 may be removed from the leadframe 40 .
  • the individual leadframes in the leadframe sheet 22 may be separated into individual integrated circuit packages, such as the integrated circuit package 120 , FIG. 8 .
  • the tabs 50 may be electrically isolated from one another in a conventional manner.
  • FIG. 8 schematically illustrates the completed integrated circuit package 120 after encapsulation and separation have been completed, in a manner as described above .
  • the molding material 122 may encompass the leadframe 40 , the shunt 100 and the integrated circuit device 110 , except for the bottom 101 of the shunt 100 , the bottom 111 of the die pad and the bottoms of the tabs 50 (e.g., the bottoms 156 , 158 , and 162 of the tabs 56 , 58 , and 62 , respectively). These areas are left exposed (i.e., not covered by the molding material 122 ) in order to facilitate later soldering to an underlying printed circuit board or the like.
  • Use of the tape 90 serves to prevent molding material from covering these surfaces during the encapsulation process.
  • the bottoms of the tabs 50 facilitate later solder connection of the integrated circuit package 120 to corresponding pads on an underlying printed circuit board or the like.
  • a distinct electrical pathway will be established from each pad on the integrated circuit device 110 (e.g., one of the integrated circuit device pads 112 , 114 , 116 , 118 , FIG. 6 ) and a corresponding pad on the printed circuit board.
  • FIG. 9 is a flowchart illustrating an exemplary method of manufacturing described herein.
  • step 202 includes providing a sheet 22 ( FIGS. 1-2 ) containing a plurality of interconnected leadframes 30 , each leadframe (e.g., the leadframe 40 , FIG. 3 ) having a die mounting pad 70 and an open space 80 extending therethrough.
  • Step 204 includes applying tape 90 ( FIGS. 5-6 ) to a lower surface of the leadframes 30 .
  • Step 206 encompasses providing a shunt sheet containing a plurality of interconnected shunts (e.g., the shunt 100 , FIG. 6 ).
  • Step 208 includes separating the shunt sheet into individual shunts (e.g., the shunt 100 , FIG. 6 ).
  • Step 210 describes, using a pick and place apparatus, installing one shunt 100 ( FIG. 6 ) into the open space 80 of each leadframe 40 , such that the shunt 100 is supported on the tape 90 and does not touch any portion of the leadframe 40 .
  • Step 212 includes, using a pick and place apparatus, mounting an integrated circuit device 110 ( FIG. 6 ) onto the die mounting pad 70 of each leadframe.
  • Step 214 includes wirebonding the integrated circuit device 110 to portions of the leadframe 40 and to the shunt 100 ( FIG. 6 ).
  • Step 216 includes encapsulating the leadframe 40 , shunt 100 and integrated circuit device 110 in a molding material 122 ( FIG. 8 ).
  • Step 218 encompasses removing the tape 90 from the lower surface of the leadframe 40 .
  • step 220 includes separating the individual leadframe units from one another to form a completed integrated circuit package 120 ( FIG. 8 ). This separating step may, for example, be accomplished by a sawing process.
  • FIG. 10 is a flowchart depicting one embodiment of a method of manufacturing an integrated circuit package.
  • step 302 includes providing at least one lead frame having an upper surface, an oppositely disposed lower surface and at least one open space extending through the at least one leadframe from the upper surface to the lower surface.
  • step 304 includes attaching an integrated circuit device to a portion of the upper surface of the at least one leadframe.
  • Step 306 includes applying tape to the lower surface of the at least one leadframe.
  • Step 308 includes placing a shunt at least partially in the open space such that it is in contact with the tape.
  • Step 310 includes electrically connecting the integrated circuit device to the shunt and to the at least one leadframe.
  • Step 312 includes encompassing at least portions of the at least one leadframe, the integrated circuit device and the shunt with a molding material.
  • step 314 includes, thereafter, removing the tape from the lower surface of the at least one leadframe
  • FIG. 11 is a flowchart depicting another embodiment of a method of manufacturing an integrated circuit package.
  • step 402 includes providing at least one lead frame having an upper surface, an oppositely disposed lower surface and at least one open space extending through the at least one leadframe from the upper surface to the lower surface.
  • step 404 includes attaching an integrated circuit device to a portion of the upper surface of the at least one leadframe.
  • Step 406 includes placing a shunt at least partially in the open space such that it is not in contact with any portion of the at least one leadframe.
  • Step 408 includes electrically connecting the integrated circuit device to the shunt and to the at least one leadframe.
  • step 410 includes, while maintaining the shunt not in contact with any portion of the at least one leadframe, encompassing at least portions of the at least one leadframe, the integrated circuit device and the shunt with a molding material.
  • the package and method described herein provide many advantages.
  • the present method uses a relatively inexpensive tape 90 to hold the shunt 100 in place within the leadframe.
  • Other applications use rivets to hold the shunt in place or tape which ultimately becomes encapsulated and incorporated in the finished device to secure the shunt on the leadframe.
  • This type of tape is expensive as it must be die cut to a picture frame form.
  • the use of tape in this manner provides additional interfaces where later delamination might occur within the finished package.
  • the use of rivets is disadvantageous for several reasons. Riveted attachments, for example, tend to take up more space—particularly since the rivets generally require tie straps extending from the leadframe. Further, a more complex leadframe and shunt result when rivets are used.
  • the use of rivets negatively impacts the hermeticity of the overall package since additional paths for moisture ingress are created (i.e., the tie straps to which the rivets attach, one located at each end of the shunt).
  • the shunt 100 is fully encapsulated on five sides with only the bottom surface 101 exposed.
  • the present package and method also allow customization of the shunt 100 ; the shunt, for example, can be formed from a different alloy than the leadframe 40 and/or the shunt 100 can be selectively plated with any desired material without the need to also plate the leadframe 40 . Further, the size and shape of the shunt 100 can be easily changed with no need to change the configuration of the leadframe 40 (as long as the shunt 100 fits in the leadframe open space 80 ).

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

An integrated circuit package may be formed using a leadframe having an open space extending therethrough. A shunt is located within the open space such that it is not in contact with any portion of the leadframe. Tape may be applied to the lower surface of the leadframe to support the shunt and hold it in place relative to the leadframe until wirebonding and encapsulation have been completed. Thereafter, the tape may be removed.

Description

    BACKGROUND
  • An integrated circuit package serves to physically and electrically connect an integrated circuit device (housed within the integrated circuit package) to a printed circuit board. One type of integrated circuit package is known as a “flat no-leads package”. This type of package is a surface-mount technology that connects an integrated circuit device to surfaces of the printed circuit board without the use of through-holes. Perimeter lands on the package bottom provide electrical connections to the printed circuit board. Flat no-leads packages typically include a planar copper leadframe substrate upon which the integrated circuit device is mounted. The leadframe and the integrated circuit device are typically encapsulated within a molding material. Flat no-lead packages generally include an exposed thermal pad to improve heat transfer out of the integrated circuit device (and into the printed circuit board). There are various types of flat no-leads packages in use, including QFN (quad-flat no-leads) and DFN (dual-flat no-leads) variations.
  • For certain integrated circuit package applications, it is required that a rectangular copper alloy slug or shunt be included in the package with one surface exposed for soldering.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a plan view of exemplary block of connected leadframe sheets.
  • FIG. 2 is a plan view of one of the leadframe sheets of FIG. 1.
  • FIG. 3 is a plan view of an exemplary leadframe from the leadframe sheet of FIG. 2.
  • FIG. 4 is a cross-section view of the leadframe of FIG. 3, taken along the line 4-4 in FIG. 3.
  • FIG. 5 is a cross-section view similar to that of FIG. 4, but showing the leadframe of FIG. 3 having tape applied to its lower surface.
  • FIG. 6 is a plan view of the leadframe of FIG. 3, illustrating a shunt supported on the tape shown in FIG. 5, an integrated circuit device mounted on a die pad of the leadframe and wirebonding between the integrated circuit device, the shunt and the leadframe.
  • FIG. 7 is a cross-section view of the leadframe of FIG. 6, taken along the line 7-7 in FIG. 6.
  • FIG. 8 is a perspective view of a completed integrated circuit package.
  • FIG. 9 illustrates by flow diagram, selected steps in an exemplary method for manufacturing an integrated circuit package according to the present disclosure.
  • FIG. 10 illustrates by flow diagram, one embodiment of a method of manufacturing an integrated circuit package.
  • FIG. 11 illustrates by flow diagram, another embodiment of a method of manufacturing an integrated circuit package.
    •  DETAILED DESCRIPTION
  • As discussed previously, for certain integrated circuit package applications, it is required that a rectangular copper alloy slug or shunt be included in the package with one surface exposed for soldering. The copper alloy used in the shunt may, for example, be of the type sold under the trademark MANGANIN®, and may, for example, have a composition of about 86% copper, 12% manganese, and 2% nickel. Because of the relatively high cost of this alloy, it is advantageous to have the leadframe formed from a less expensive leadframe alloy, for example, the alloy sold under the trade designation “CDA194”. CDA194 is well suited and characterized both thermally and mechanically for use in leadframes. It is also formulated to facilitate stamping and etching of leadframes.
  • In general terms, an integrated circuit package, along with a method of manufacturing the package, are disclosed herein. The disclosed package and method of manufacture provide the ability, for example, to incorporate a slug or shunt made of a more expensive copper alloy (e.g., MANGANIN®) into a package having its leadframe manufactured from a less expensive leadframe alloy. The alloy CDA194, as mentioned above, is widely used for leadframes and is readily available from rolling mills. MANGANIN®, however, is generally less widely used and available.
  • The process of manufacturing the package disclosed herein begins by providing a leadframe, e.g., the leadframe 40, FIG. 3. FIG. 1 illustrates a block 10 of connected leadframe sheets 22, 24, 26, and 28. FIG. 2 illustrates the leadframe sheet 22 in further detail, it being understood that the remaining leadframe sheets 24, 26, and 28 may be substantially identical to the leadframe sheet 22. With reference to FIG. 2, the leadframe sheet 22 may include a plurality (e.g., eighty-eight, as depicted in FIG. 2) of leadframes 30 including the individual leadframes 32, 34, 36, 38 and 40.
  • FIG. 3 illustrates the leadframe 40 in further detail, it being understood that the remainder of the leadframes 30 may be substantially identical to the leadframe 40. It is noted that, for purposes of illustrative efficiency, the package and method of manufacture will be described herein specifically in conjunction with the exemplary leadframe 40. It is to be understood, however, that the methodology described may be carried out on all of the leadframes 30 while they are still connected to one another in the leadframe sheet 22 and while the leadframe sheets 22, 24, 26, and 28 are still connected to one another in the leadframe block 10.
  • With reference now to FIG. 3, the leadframe 40 may include a frame portion 42 having an upper surface 44 and an oppositely disposed lower surface 46 (FIG. 4). A plurality of tabs 50, including the individual tabs 56, 58, and 62, may extend inwardly from the frame 42, as shown. The tops of the tabs 50 are the targets for wire bonding connections to the integrated circuit device (in a manner that will be described in further detail herein). With reference again to FIG. 3, the right side (as viewed in the orientation of FIG. 3) of the leadframe 40 may be occupied by a die mounting pad 70 for mounting an integrated circuit device, in a manner as will be described in further detail herein. The left side of the leadframe 40 may include an open space 80 that extends completely through the leadframe, i.e., the open space 80 extends from the upper surface 44 to the lower surface 46 of the leadframe 40.
  • The leadframe 40 may be constructed from a relatively inexpensive leadframe alloy, for example, the alloy sold under the trade designation “CDA194”. Alternatively, the leadframe 40 may be constructed of copper or another copper alloy, other metal or metal alloy.
  • Continuing with the description of the methodology, and with reference now to FIG. 5, tape 90 may be adhered to the lower surface 46 of the leadframe 40 such that it extends beneath the entire extent of the leadframe. Tape 90 may include an upper surface 92 and an oppositely disposed lower surface 94. To adhere the tape 90 to the leadframe 40, the upper surface 92 of the tape 90 may be adhered to the lower surface 46 of the frame portion 42 in areas where the tape 90 underlies the frame portion 42. The tape 90 may, for example, be either a pressure sensitive adhesive tape or a thermoplastic tape and may have a thickness “A”, for example, of about 2 mil-50 μm. It is noted that the relative thickness of the tape 90 has been exaggerated in FIG. 5 for purposes of illustrative clarity.
  • With reference to FIGS. 6 and 7, after the tape 90 has been applied, a shunt 100 may be inserted into the open space 80 of the leadframe 40. As can be appreciated from FIG. 6, the shunt 100 may be located such that it does not touch any part of the leadframe frame portion 42 and is supported only by the tape 90. The shunt 100 may be placed within the open space 80 of the leadframe 40 using conventional die mount, pick and place equipment. It is noted that the shunt 100 may be formed in a large sheet of interconnected shunts (not shown). The shunts may then be separated from one another prior to insertion into the leadframes. The shunt 100 may, for example, be formed from a relatively expensive material such as a copper alloy sold under the trademark MANGANIN®. The shunt may be pre-plated or post-plated, as desired.
  • With further reference to FIGS. 6 and 7, an integrated circuit device 110 may be mounted to the leadframe 40, as shown. More specifically, the Integrated circuit device 110 can be attached to the die mounting pad 70 in a conventional manner, using an adhesive material such as epoxy or silver filled epoxy.
  • Next, with continued reference to FIGS. 6 and 7, the integrated circuit device 110 may be electrically connected to the shunt 100 and the leadframe 40, for example, using bonding wires. Bonding wires 102 and 104, for example, may extend between the shunt 100 and the pads 112 and 114, respectively, on the integrated circuit device 110. A bonding wire 106 may extend between the integrated circuit device pad 116 and the top of the leadframe tab 56. In a similar manner, a bonding wire 108 may extend between the integrated circuit device pad 118 and the top of the leadframe tab 58. For purposes of illustrative clarity, only four bonding wires have been shown in FIG. 6. It is to be understood, however, that many more bonding wires may be provided to establish the desired connections between the integrated circuit device 110, the leadframe 40 and shunt 100.
  • After wire bonding has been completed, in a manner as described above, the leadframe 40, integrated circuit device 110 and shunt 100 may be encapsulated within a molding material (e.g., the molding material 122, FIG. 8) in a conventional manner. The molding material may, for example, be a plastic material such as epoxy or other conventional insulating material. The molding material 122 may be formed in an injection molding process or it may be applied as a coating.
  • Once the molding material has been applied and it has hardened, it serves to secure the location of the shunt 100 relative to the leadframe 40. Accordingly, after the encapsulation step has been completed, the tape 90 may be removed from the leadframe 40. Thereafter, the individual leadframes in the leadframe sheet 22 may be separated into individual integrated circuit packages, such as the integrated circuit package 120, FIG. 8. After encapsulation and separation have been completed, in a manner as described above, the tabs 50 may be electrically isolated from one another in a conventional manner.
  • FIG. 8 schematically illustrates the completed integrated circuit package 120 after encapsulation and separation have been completed, in a manner as described above . As can be seen from FIG. 8, the molding material 122 may encompass the leadframe 40, the shunt 100 and the integrated circuit device 110, except for the bottom 101 of the shunt 100, the bottom 111 of the die pad and the bottoms of the tabs 50 (e.g., the bottoms 156, 158, and 162 of the tabs 56, 58, and 62, respectively). These areas are left exposed (i.e., not covered by the molding material 122) in order to facilitate later soldering to an underlying printed circuit board or the like. Use of the tape 90, in a manner as previously described herein, serves to prevent molding material from covering these surfaces during the encapsulation process.
  • The bottoms of the tabs 50 (e.g., the bottoms 156, 158, and 162 of the tabs 56, 58, and 62, respectively) facilitate later solder connection of the integrated circuit package 120 to corresponding pads on an underlying printed circuit board or the like. As can be appreciated, once the integrated circuit package 120 has been attached, for example, to an underlying printed circuit board, a distinct electrical pathway will be established from each pad on the integrated circuit device 110 (e.g., one of the integrated circuit device pads 112, 114, 116, 118, FIG. 6) and a corresponding pad on the printed circuit board. With reference, for example, to the tab 58, electrical continuity will be established between the corresponding printed circuit board pad and the tab 58 via a solder joint extending between the printed circuit board pad and the bottom 158 of the electrically conductive tab 58. Continuity is also established between the top of the tab 58 and the pad 118 of the integrated circuit device via the bonding wire 108. Accordingly, in this manner, a continuous and distinct electrical pathway is established between the pad 118 of the integrated circuit device 110 and a corresponding pad on the underlying printed circuit board.
  • FIG. 9 is a flowchart illustrating an exemplary method of manufacturing described herein. With reference now to FIG. 9, step 202 includes providing a sheet 22 (FIGS. 1-2) containing a plurality of interconnected leadframes 30, each leadframe (e.g., the leadframe 40, FIG. 3) having a die mounting pad 70 and an open space 80 extending therethrough. Step 204 includes applying tape 90 (FIGS. 5-6) to a lower surface of the leadframes 30. Step 206 encompasses providing a shunt sheet containing a plurality of interconnected shunts (e.g., the shunt 100, FIG. 6). Step 208 includes separating the shunt sheet into individual shunts (e.g., the shunt 100, FIG. 6). Step 210 describes, using a pick and place apparatus, installing one shunt 100 (FIG. 6) into the open space 80 of each leadframe 40, such that the shunt 100 is supported on the tape 90 and does not touch any portion of the leadframe 40. Step 212 includes, using a pick and place apparatus, mounting an integrated circuit device 110 (FIG. 6) onto the die mounting pad 70 of each leadframe. Step 214 includes wirebonding the integrated circuit device 110 to portions of the leadframe 40 and to the shunt 100 (FIG. 6). Step 216 includes encapsulating the leadframe 40, shunt 100 and integrated circuit device 110 in a molding material 122 (FIG. 8). Step 218 encompasses removing the tape 90 from the lower surface of the leadframe 40. Finally, step 220 includes separating the individual leadframe units from one another to form a completed integrated circuit package 120 (FIG. 8). This separating step may, for example, be accomplished by a sawing process.
  • FIG. 10 is a flowchart depicting one embodiment of a method of manufacturing an integrated circuit package. With reference now to FIG. 10, step 302 includes providing at least one lead frame having an upper surface, an oppositely disposed lower surface and at least one open space extending through the at least one leadframe from the upper surface to the lower surface. Step 304 includes attaching an integrated circuit device to a portion of the upper surface of the at least one leadframe. Step 306 includes applying tape to the lower surface of the at least one leadframe. Step 308 includes placing a shunt at least partially in the open space such that it is in contact with the tape. Step 310 includes electrically connecting the integrated circuit device to the shunt and to the at least one leadframe. Step 312 includes encompassing at least portions of the at least one leadframe, the integrated circuit device and the shunt with a molding material. Finally, step 314 includes, thereafter, removing the tape from the lower surface of the at least one leadframe
  • FIG. 11 is a flowchart depicting another embodiment of a method of manufacturing an integrated circuit package. With reference now to FIG. 11, step 402 includes providing at least one lead frame having an upper surface, an oppositely disposed lower surface and at least one open space extending through the at least one leadframe from the upper surface to the lower surface. Step 404 includes attaching an integrated circuit device to a portion of the upper surface of the at least one leadframe. Step 406 includes placing a shunt at least partially in the open space such that it is not in contact with any portion of the at least one leadframe. Step 408 includes electrically connecting the integrated circuit device to the shunt and to the at least one leadframe. Finally, step 410 includes, while maintaining the shunt not in contact with any portion of the at least one leadframe, encompassing at least portions of the at least one leadframe, the integrated circuit device and the shunt with a molding material.
  • As can be appreciated, the package and method described herein provide many advantages. The present method, for example, uses a relatively inexpensive tape 90 to hold the shunt 100 in place within the leadframe. Other applications use rivets to hold the shunt in place or tape which ultimately becomes encapsulated and incorporated in the finished device to secure the shunt on the leadframe. This type of tape is expensive as it must be die cut to a picture frame form. Further, the use of tape in this manner provides additional interfaces where later delamination might occur within the finished package. The use of rivets is disadvantageous for several reasons. Riveted attachments, for example, tend to take up more space—particularly since the rivets generally require tie straps extending from the leadframe. Further, a more complex leadframe and shunt result when rivets are used. Most significantly, the use of rivets negatively impacts the hermeticity of the overall package since additional paths for moisture ingress are created (i.e., the tie straps to which the rivets attach, one located at each end of the shunt). In the present process using the tape 90, the shunt 100 is fully encapsulated on five sides with only the bottom surface 101 exposed.
  • Another advantage provided by the package and method described herein is that, since the tape 90 is removed after encapsulation, it does not become part of the final package and, thus, does not pose a risk of causing delamination between the mold compound and the tape. The present package and method also allow customization of the shunt 100; the shunt, for example, can be formed from a different alloy than the leadframe 40 and/or the shunt 100 can be selectively plated with any desired material without the need to also plate the leadframe 40. Further, the size and shape of the shunt 100 can be easily changed with no need to change the configuration of the leadframe 40 (as long as the shunt 100 fits in the leadframe open space 80).
  • The foregoing description of specific embodiments has been presented for purposes of illustration and description. The specific embodiments described are not intended to be exhaustive or to suggest a constraint to the precise forms disclosed, and many modifications and variations are possible in light of the above teaching. The illustrated embodiments were chosen and described in order to best explain principles and practical application, to thereby enable others skilled in the art to best utilize the various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the disclosure herein be defined only by the claims appended hereto and their equivalents, except as limited by the prior art.

Claims (20)

1. A method of manufacturing an integrated circuit package, comprising:
providing at least one lead frame having an upper surface, an oppositely disposed lower surface and at least one open space extending through the at least one leadframe from said upper surface to said lower surface;
attaching an integrated circuit device to a portion of said upper surface of said at least one leadframe;
applying tape to the lower surface of said at least one leadframe;
placing a shunt at least partially in said open space such that it is in contact with said tape;
electrically connecting said integrated circuit device to said shunt and to said at least one leadframe;
encompassing at least portions of said at least one leadframe, said integrated circuit device and said shunt with a molding material; and
thereafter, removing said tape from said lower surface of said at least one leadframe.
2. The method of claim 1 and further wherein:
said shunt is formed from an alloy comprising copper, manganese, and nickel.
3. The method of claim 1 and further wherein:
said applying tape to the lower surface of said at least one leadframe comprises applying a pressure sensitive adhesive tape to said lower surface of said at least one leadframe.
4. The method of claim 1 and further wherein:
said applying tape to the lower surface of said at least one leadframe comprises applying a thermoplastic tape to said lower surface of said at least one leadframe.
5. The method of claim 1 and further wherein:
said shunt is not in contact with any portion of said at least one leadframe.
6. The method of claim 1 and further wherein:
said placing a shunt at least partially in said open space such that it is in contact with said tape comprises fully supporting said shunt on said tape.
7. The method of claim 1 and further wherein:
said providing at least one lead frame comprises providing a plurality of leadframes interconnected in a sheet; and
said applying tape to the lower surface of said at least one leadframe comprises applying tape to lower surfaces of said plurality of leadframes.
8. An integrated circuit package comprising:
a lead frame having an upper surface, an oppositely disposed lower surface and at least one opening extending through the leadframe from said upper surface to said lower surface;
an integrated circuit device attached to a portion of said upper surface of said leadframe;
a shunt positioned at least partially in said opening; and
wherein, said shunt is not in contact with any portion of said leadframe.
9. The integrated circuit package of claim 8 and further wherein:
said integrated circuit device is electrically connected to said shunt and to said leadframe.
10. The integrated circuit device of claim 9 and further wherein:
said integrated circuit device is electrically connected to said shunt and to said leadframe by wire bonds.
11. The integrated circuit package of claim 8 and further comprising:
a molding material encompassing at least portions of said leadframe, said integrated circuit device and said shunt.
12. The integrated circuit package of claim 8 and further wherein:
said shunt is formed from an alloy comprising copper, manganese, and nickel.
13. A method of manufacturing an integrated circuit package, comprising:
providing at least one lead frame having an upper surface, an oppositely disposed lower surface and at least one open space extending through the at least one leadframe from said upper surface to said lower surface;
attaching an integrated circuit device to a portion of said upper surface of said at least one leadframe;
placing a shunt at least partially in said open space such that it is not in contact with any portion of said at least one leadframe;
electrically connecting said integrated circuit device to said shunt and to said at least one leadframe; and
while maintaining said shunt not in contact with any portion of said at least one leadframe, encompassing at least portions of said at least one leadframe, said integrated circuit device and said shunt with a molding material.
14. The method of claim 13 and further comprising:
applying tape to the lower surface of said at least one leadframe prior to said electrically connecting said integrated circuit device to said shunt and to said at least one leadframe; and
wherein, said placing a shunt at least partially in said open space such that it is not in contact with any portion of said at least one leadframe comprises supporting said shunt on said tape.
15. The method of claim 14 and further comprising:
removing said tape from said lower surface of said at least one leadframe after said encompassing at least portions of said at least one leadframe, said integrated circuit device and said shunt with a molding material.
16. The method of claim 13 and further wherein:
said shunt is formed from an alloy comprising copper, manganese, and nickel.
17. The method of claim 14 and further wherein:
said applying tape to the lower surface of said at least one leadframe comprises applying a pressure sensitive adhesive tape to said lower surface of said at least one leadframe.
18. The method of claim 14 and further wherein:
said applying tape to the lower surface of said at least one leadframe comprises applying a thermoplastic tape to said lower surface of said at least one leadframe.
19. The method of claim 14 and further wherein:
said supporting said shunt on said tape comprises supporting said shunt only with said tape.
20. The method of claim 13 and further wherein:
said providing at least one lead frame comprises providing a plurality of leadframes interconnected in a sheet.
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US10365303B2 (en) 2016-04-28 2019-07-30 Texas Instruments Incorporated Shunt strip
US20170323708A1 (en) 2016-05-03 2017-11-09 Texas Instruments Incorporated Component sheet and method of singulating
US10335875B2 (en) 2016-05-26 2019-07-02 Texas Instruments Incorporated Methods and devices for dicing components from a sheet of copper alloy
CN111128944B (en) * 2019-12-30 2021-12-10 南通南平电子科技有限公司 High-performance capacitor lead frame

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US7847391B2 (en) * 2008-07-01 2010-12-07 Texas Instruments Incorporated Manufacturing method for integrating a shunt resistor into a semiconductor package
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US9704812B1 (en) * 2016-05-06 2017-07-11 Atmel Corporation Double-sided electronic package

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