CN108616216B - Charge pump bleeder circuit - Google Patents
Charge pump bleeder circuit Download PDFInfo
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- CN108616216B CN108616216B CN201611128462.7A CN201611128462A CN108616216B CN 108616216 B CN108616216 B CN 108616216B CN 201611128462 A CN201611128462 A CN 201611128462A CN 108616216 B CN108616216 B CN 108616216B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
Abstract
The embodiment of the invention discloses a charge pump bleeder circuit, which comprises: the at least two discharging units are connected with the discharging nodes of the charge pumps of each stage in a one-to-one correspondence manner and are used for discharging the discharging nodes of the charge pumps of each stage under the control of a discharging control signal; the discharge time sequence control unit is connected with the at least two discharge units in a one-to-one correspondence manner and is used for generating a discharge control signal with a set time sequence relation under the control of the first enabling signal and the second enabling signal so that the discharge control signal controls the at least two discharge units to discharge sequentially according to the set time sequence relation, the purpose of enabling each discharge node of the charge pump circuit to discharge more safely is achieved, and the reliability of the charge pump is improved.
Description
Technical Field
Embodiments of the present invention relate to circuit technology, and in particular, to a charge pump bleeder circuit.
Background
The nonvolatile flash Memory medium (nor flash/nand flash) is a common Memory chip, has the advantages of a random access Memory (Random Access Memory, RAM) and a Read-Only Memory (ROM), cannot lose data when power is lost, and is a Memory capable of electrically erasing and writing in a system, and meanwhile, the high integration level and low cost of the nonvolatile flash Memory medium make the nonvolatile flash Memory become the main stream of the market. In nor flash/nand flash, a very high voltage, for example, up to 30V is used when programming or erasing a memory cell, and if such a high voltage is reached, a plurality of stages of charge pumps are required to be connected in series to achieve the high voltage when the external power is 3.3V or 1.8V. Specifically, referring to the schematic circuit structures of five-stage serial charge pumps shown in fig. 1 and 2, high-voltage output can be realized, wherein pulse signals CLK and CLKB are mutually opposite high-low level signals, and step-by-step voltage rise is realized through the high-level pulse signals with the value of power supply VDD and the energy storage capacitor.
However, when the charge pump stops operating in a high voltage state, there is a very high voltage at the charge pump nodes of each stage in series, such as nodes N1-N10 in fig. 1 and 2, and the high voltage at each node may cause breakdown of the transistor when used by a user, so that the voltage at each node needs to be discharged. The existing bleeder circuits bleed all nodes together, but there is a problem: if one of the two adjacent nodes discharges faster and the other discharges slower, then the transistor between the two adjacent nodes may break down due to excessive voltage difference, resulting in damage to the entire charge pump circuit, and thus improvement is needed for this problem.
Disclosure of Invention
The invention provides a charge pump bleeder circuit, which achieves the aim of safer discharging of each discharging node of the charge pump circuit and improves the reliability of the charge pump.
In a first aspect, embodiments of the present invention provide a charge pump bleeder circuit, the circuit comprising:
the at least two discharging units are connected with the discharging nodes of the charge pumps of each stage in a one-to-one correspondence manner and are used for discharging the discharging nodes of the charge pumps of each stage under the control of a discharging control signal;
the discharge time sequence control unit is connected with the at least two discharge units in a one-to-one correspondence manner and is used for generating a discharge control signal with a set time sequence relation under the control of the first enabling signal and the second enabling signal so that the discharge control signal controls the at least two discharge units to discharge sequentially according to the set time sequence relation.
Further, the method comprises the steps of, the discharge unit includes: and one end of the control switch is connected with the discharge node of the charge pump, and the other end of the control switch is grounded and used for closing the control switch under the control of a discharge control signal to discharge the discharge node of the charge pump.
Further, the discharge timing control unit includes: the first capacitor, the second capacitor … …, the nth capacitor, the first and gate, the second and gate … …, the nth and gate, the first inverter and the second inverter … …, and the (2 n-1) th inverter, wherein n is the total number of discharge nodes of each stage of charge pump and n is greater than or equal to 2.
Further, n is equal to 5, and correspondingly, the input end of the first inverter is connected with a first enabling signal, and the output end of the first inverter is connected with the second input end of the first AND gate, the input end of the second inverter and the upper polar plate of the first capacitor; the lower polar plate of the first capacitor is grounded; the first input end of the first AND gate is connected with the second enabling signal, and the output end of the first AND gate outputs a fifth discharge control signal;
the output end of the second inverter is connected with the input end of a third inverter, and the output end of the third inverter is connected with the second input end of the second AND gate, the upper polar plate of the second capacitor and the input end of the fourth inverter; the lower polar plate of the second capacitor is grounded; the first input end of the second AND gate is connected with a second enabling signal, and the output end of the second AND gate outputs a fourth discharging control signal;
the output end of the fourth inverter is connected with the input end of a fifth inverter, and the output end of the fifth inverter is connected with the second input end of the third AND gate, the upper polar plate of the third capacitor and the input end of the sixth inverter; the lower polar plate of the third capacitor is grounded; the first input end of the third AND gate is connected with the second enabling signal, and the output end of the third AND gate outputs a third discharge control signal;
the output end of the sixth inverter is connected with the input end of the seventh inverter, and the output end of the seventh inverter is connected with the second input end of the fourth AND gate, the upper polar plate of the fourth capacitor and the input end of the eighth inverter; the lower polar plate of the fourth capacitor is grounded; the first input end of the fourth AND gate is connected with a second enabling signal, and the output end of the fourth AND gate outputs a second discharging control signal;
the output end of the eighth inverter is connected with the input end of the ninth inverter, and the output end of the ninth inverter is connected with the second input end of the fifth AND gate; the first input end of the fifth AND gate is connected with the second enabling signal, and the output end of the fifth AND gate outputs a first discharging control signal.
In a second aspect, an embodiment of the present invention further provides a charge pump, including the bleeder circuit described in the first aspect.
The embodiment of the invention provides a charge pump bleeder circuit, which comprises: the at least two discharging units are connected with the discharging nodes of the charge pumps of each stage in a one-to-one correspondence manner and are used for discharging the discharging nodes of the charge pumps of each stage under the control of a discharging control signal; the discharge time sequence control unit is connected with the at least two discharge units in a one-to-one correspondence manner and is used for generating a discharge control signal with a set time sequence relation under the control of the first enabling signal and the second enabling signal so that the discharge control signal controls the at least two discharge units to discharge sequentially according to the set time sequence relation, the purpose of enabling each discharge node of the charge pump circuit to discharge more safely is achieved, and the reliability of the charge pump is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional five-stage series NMOS transistor charge pump;
FIG. 2 is a schematic diagram of a circuit configuration of a prior art five-stage series PMOS transistor charge pump;
fig. 3 is a schematic diagram of a charge pump bleeder circuit according to a first embodiment of the present invention;
FIG. 4 is a schematic diagram showing a charge pump according to an embodiment of the present invention, wherein each discharge node is discharged under the control of discharge control signals with different timings;
fig. 5 is a schematic circuit diagram of a discharge unit according to a second embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a discharge timing control unit according to a second embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 3 is a schematic structural diagram of a charge pump bleeder circuit according to a first embodiment of the present invention, which is suitable for discharging at least two charge pump discharge nodes. Referring specifically to fig. 3, the charge pump bleeder circuit provided in this embodiment specifically includes:
at least two discharge units 310, in this embodiment, five discharge units are specifically explained as examples, and the five discharge units are a first discharge unit 311, a second discharge unit 312, a third discharge unit 313, a fourth discharge unit 314, and a fifth discharge unit 315, which are respectively connected in one-to-one correspondence with discharge nodes N6, N7, N8, N9, and N10 (refer to discharge nodes N6, N7, N8, N9, and N10 in fig. 2) of each stage of charge pump, and are used for discharging the discharge nodes N6, N7, N8, N9, and N10 of each stage of charge pump under the control of discharge control signals V1, V2, V3, V4, and V5;
the discharge timing control unit 320 is connected to the five discharge units in a one-to-one correspondence manner, and is configured to generate discharge control signals V1, V2, V3, V4, and V5 with a set timing relationship under the control of the first enable signal EN and the second enable signal DISH, so that the discharge control signals V1, V2, V3, V4, and V5 control the five discharge units to sequentially perform discharge according to the set timing relationship.
Specifically, the set timing relationship may be that the discharge control signal V5 is first valid, the fifth discharge unit 315 is first valid, the discharge node N10 with the highest voltage in the charge pump circuit (see fig. 2) is preferentially discharged, the discharge control signals V4, V3, V2 and V1 are sequentially valid, the fourth discharge unit 314, the third discharge unit 313, the second discharge unit 312 and the first discharge unit 311 are sequentially started to sequentially discharge the discharge nodes N9, N8, N7 and N6, and since the voltage of the discharge node N10 is gradually reduced when the discharge node N10 starts to discharge, but the discharge node N9 does not start to discharge, the voltage difference between the two nodes is gradually increased, and when the voltage difference between the two nodes is greater than the threshold voltage of the NMOS transistor between the two nodes, the NMOS transistor between the two nodes is turned on, so that the voltage of the discharge node N9 is discharged through the discharge unit of the discharge node N10, and the voltage difference between the discharge node N9 is not greater than the threshold voltage of the NMOS transistor between the two nodes, and the reliability of the discharge transistor between the two nodes is not ensured, and the reliability of the charge pump is improved. The discharging principle of the other discharging nodes is the same as that of the discharging node N10, and will not be described in detail. Similarly, the principle of discharging the discharge nodes N1, N2, N3, N4, and N5 of the NMOS transistor charge pump circuit in fig. 1 is the same as the above-described discharge principle, and the reliability of the charge pump can be improved as well.
In particular, referring to a simulation diagram of discharging each discharging node of the charge pump under the control of discharging control signals with different time sequences shown in fig. 4, where the horizontal axis represents time (μs) and the vertical axis represents voltage (V), it can be seen that each discharging node discharges in sequence, and the voltage difference between two connected discharging nodes does not exceed the threshold voltage of the transistor between the two discharging nodes, that is, the voltage difference between the discharging nodes at each stage is within a safety range.
The charge pump bleeder circuit provided in this embodiment includes: the at least two discharging units are connected with the discharging nodes of the charge pumps of each stage in a one-to-one correspondence manner and are used for discharging the discharging nodes of the charge pumps of each stage under the control of a discharging control signal; the discharge time sequence control unit is connected with the at least two discharge units in a one-to-one correspondence manner and is used for generating a discharge control signal with a set time sequence relationship under the control of a first enabling signal and a second enabling signal, the discharge control signals control the at least two discharge units to discharge sequentially according to a set time sequence relationship, so that the purpose of safer discharge of each discharge node of the charge pump circuit is achieved, and the reliability of the charge pump is improved.
Example two
Fig. 5 is a schematic circuit diagram of a discharge unit according to a second embodiment of the present invention, where the discharge unit 310 and the discharge timing control unit 320 are optimized based on the above embodiment, and specifically, see fig. 5 and 6:
the discharge unit 310 includes: the control switch 311, one end of the control switch 311 is connected with the discharge node N1/N2/N3/N4 … … of the charge pump, and the other end is grounded and used for closing the control switch under the control of a discharge control signal Vn (V1/V2/V3/V4 … …) to discharge the discharge node of the charge pump; wherein the control switch 311 can be any switch whose on/off can be controlled by a control signal, the type of the switch is not limited here as long as the switch can realize the corresponding function.
The discharge timing control unit 320 includes: the first capacitor, the second capacitor … …, the nth capacitor, the first and gate, the second and gate … …, the nth and gate, the first inverter, the second inverter … …, and the (2 n-1) th inverter, where n is the total number of discharge nodes of each stage of charge pump and n is equal to or greater than 2, and n is equal to 5, as shown in fig. 6, the discharge timing control unit 320 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first and gate Y1, a second and gate Y2, a third and gate Y3, a fourth and gate Y4, a fifth and gate Y5, a first inverter T1, a second inverter T2, a third inverter T3, a fourth inverter T4, a fifth inverter T5, a sixth inverter T6, a seventh inverter T7, an eighth inverter T8, and a ninth inverter T9, where an input terminal of the first inverter T1 is connected to a first enable signal, an input terminal of the first and an output terminal of the first and the second and the first and gate plate C1 are connected to the second input terminal of the first and gate plate C1; the lower polar plate of the first capacitor C1 is grounded GND; the first input end of the first AND gate Y1 is connected with the second enabling signal DISH, and the output end outputs a fifth discharging control signal V5;
the output end of the second inverter T2 is connected with the input end of a third inverter T3, and the output end of the third inverter T3 is connected with the second input end of the second AND gate Y2, the upper polar plate of the second capacitor C2 and the input end of the fourth inverter T4; the lower polar plate of the second capacitor C2 is grounded GND; the first input end of the second AND gate Y2 is connected with a second enabling signal DISH, and the output end outputs a fourth discharging control signal V4;
the output end of the fourth inverter T4 is connected with the input end of the fifth inverter T5, and the output end of the fifth inverter T5 is connected with the second input end of the third AND gate Y3, the upper polar plate of the third capacitor C3 and the input end of the sixth inverter T6; the lower polar plate of the third capacitor C3 is grounded GND; the first input end of the third AND gate Y3 is connected with the second enabling signal DISH, and the output end outputs a third discharging control signal V3;
the output end of the sixth inverter T6 is connected with the input end of the seventh inverter T7, and the output end of the seventh inverter T7 is connected with the second input end of the fourth AND gate Y4, the upper polar plate of the fourth capacitor C4 and the input end of the eighth inverter T8; the lower polar plate of the fourth capacitor C4 is grounded GND; the first input end of the fourth AND gate Y4 is connected with the second enabling signal DISH, and the output end outputs a second discharging control signal V2;
the output end of the eighth inverter T8 is connected with the input end of the ninth inverter T9, and the output end of the ninth inverter T9 is connected with the second input end of the fifth AND gate Y5; the first input terminal of the fifth and gate Y5 is connected to the second enable signal DISH, and the output terminal outputs the first discharge control signal V1.
The discharge timing control unit 320 of the above-described structure operates on the principle that: when the charge pump stops working and needs to discharge each discharge node, the second enable signal DISH becomes high level, the first enable signal EN also becomes high level, at this time, the rising edge of the fifth discharge control signal V5 comes first, the fifth discharge unit controlled by the fifth discharge control signal V5 works first, the discharge node N10 discharges first, the fourth discharge unit controlled by the fourth discharge control signal V4 starts working due to the delay effect of the first capacitor C1, the discharge node N9 starts to discharge, the rising edge of the first discharge control signal V1 comes last, the first discharge unit controlled by the first discharge control signal V1 works last, and the discharge node N6 discharges last according to the same principle. The time sequence control can ensure that the voltage difference between the discharge nodes is not excessive, thereby ensuring the reliability of the charge pump chip.
According to the technical scheme of the embodiment, on the basis of the first embodiment, the discharge unit 310 and the discharge time sequence control unit 320 are specifically optimized, the purpose of enabling each discharge node of the charge pump circuit to discharge more safely is achieved, and the reliability of the charge pump is improved.
On the basis of the technical scheme, the embodiment of the invention also provides a charge pump which comprises the bleeder circuit.
Note that the number of the components to be processed, the foregoing description is only of the preferred embodiments of the invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (5)
1. A charge pump bleeder circuit, comprising:
the at least two discharging units are connected with the discharging nodes of the charge pumps of each stage in a one-to-one correspondence manner and are used for discharging the discharging nodes of the charge pumps of each stage under the control of a discharging control signal;
the discharge time sequence control unit is connected with the at least two discharge units in a one-to-one correspondence manner and is used for generating a discharge control signal with a set time sequence relation under the control of the first enabling signal and the second enabling signal so that the discharge control signal controls the at least two discharge units to discharge sequentially according to the set time sequence relation.
2. The circuit of claim 1, wherein the discharge unit comprises: and one end of the control switch is connected with the discharge node of the charge pump, and the other end of the control switch is grounded and used for closing the control switch under the control of a discharge control signal to discharge the discharge node of the charge pump.
3. The circuit according to claim 1 or 2, wherein the discharge timing control unit includes: the first capacitor, the second capacitor … …, the nth capacitor, the first and gate, the second and gate … …, the nth and gate, the first inverter and the second inverter … …, and the (2 n-1) th inverter, wherein n is the total number of discharge nodes of each stage of charge pump and n is greater than or equal to 2.
4. A circuit according to claim 3, wherein n is equal to 5, and the input terminal of the first inverter is connected to the first enable signal, and the output terminal is connected to the second input terminal of the first and gate, the input terminal of the second inverter, and the upper plate of the first capacitor; the lower polar plate of the first capacitor is grounded; the first input end of the first AND gate is connected with the second enabling signal, and the output end of the first AND gate outputs a fifth discharge control signal;
the output end of the second inverter is connected with the input end of a third inverter, and the output end of the third inverter is connected with the second input end of the second AND gate, the upper polar plate of the second capacitor and the input end of the fourth inverter; the lower polar plate of the second capacitor is grounded; the first input end of the second AND gate is connected with a second enabling signal, and the output end of the second AND gate outputs a fourth discharging control signal;
the output end of the fourth inverter is connected with the input end of a fifth inverter, and the output end of the fifth inverter is connected with the second input end of the third AND gate, the upper polar plate of the third capacitor and the input end of the sixth inverter; the lower polar plate of the third capacitor is grounded; the first input end of the third AND gate is connected with the second enabling signal, and the output end of the third AND gate outputs a third discharge control signal;
the output end of the sixth inverter is connected with the input end of the seventh inverter, and the output end of the seventh inverter is connected with the second input end of the fourth AND gate, the upper polar plate of the fourth capacitor and the input end of the eighth inverter; the lower polar plate of the fourth capacitor is grounded; the first input end of the fourth AND gate is connected with a second enabling signal, and the output end of the fourth AND gate outputs a second discharging control signal;
the output end of the eighth inverter is connected with the input end of the ninth inverter, and the output end of the ninth inverter is connected with the second input end of the fifth AND gate; the first input end of the fifth AND gate is connected with the second enabling signal, and the output end of the fifth AND gate outputs a first discharging control signal.
5. A charge pump comprising a bleeder circuit as claimed in any one of claims 1 to 4.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611128462.7A CN108616216B (en) | 2016-12-09 | 2016-12-09 | Charge pump bleeder circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611128462.7A CN108616216B (en) | 2016-12-09 | 2016-12-09 | Charge pump bleeder circuit |
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| CN108616216A CN108616216A (en) | 2018-10-02 |
| CN108616216B true CN108616216B (en) | 2023-10-10 |
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| CN109713892B (en) * | 2018-12-29 | 2020-10-30 | 普冉半导体(上海)股份有限公司 | Charge pump discharge circuit and discharge method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159094A (en) * | 1995-11-08 | 1997-09-10 | 索尼公司 | Internal power supply circuit |
| JP2001145334A (en) * | 1999-11-15 | 2001-05-25 | Nec Corp | Booster circuit |
| CN101436825A (en) * | 2007-11-12 | 2009-05-20 | 旺宏电子股份有限公司 | Multiple-stage charge pump |
| CN104952403A (en) * | 2014-03-27 | 2015-09-30 | 精工爱普生株式会社 | Driver, electro-optical device, and electronic device |
| CN206481217U (en) * | 2016-12-09 | 2017-09-08 | 北京兆易创新科技股份有限公司 | A kind of charge pump leadage circuit and charge pump |
-
2016
- 2016-12-09 CN CN201611128462.7A patent/CN108616216B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159094A (en) * | 1995-11-08 | 1997-09-10 | 索尼公司 | Internal power supply circuit |
| JP2001145334A (en) * | 1999-11-15 | 2001-05-25 | Nec Corp | Booster circuit |
| CN101436825A (en) * | 2007-11-12 | 2009-05-20 | 旺宏电子股份有限公司 | Multiple-stage charge pump |
| CN104952403A (en) * | 2014-03-27 | 2015-09-30 | 精工爱普生株式会社 | Driver, electro-optical device, and electronic device |
| CN206481217U (en) * | 2016-12-09 | 2017-09-08 | 北京兆易创新科技股份有限公司 | A kind of charge pump leadage circuit and charge pump |
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