CN108614800A - FC-AE-ASM protocol processing chip circuit structures - Google Patents
FC-AE-ASM protocol processing chip circuit structures Download PDFInfo
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- CN108614800A CN108614800A CN201611139641.0A CN201611139641A CN108614800A CN 108614800 A CN108614800 A CN 108614800A CN 201611139641 A CN201611139641 A CN 201611139641A CN 108614800 A CN108614800 A CN 108614800A
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- asm
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
- G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
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Abstract
The invention belongs to computer hardware technologies, are related to a kind of circuit structure of FC AE ASM protocol processing chips.FC AE ASM protocol processing chip circuit structures of the present invention include processor module, General Porcess Unit, host interface module, FC AE ASM protocol process module.Processor module and General Porcess Unit are linked together by PLB buses and OPB buses, meanwhile, FC AE ASM protocol process module is also connected in PLB buses.In addition, host interface module is connect with FC AE ASM protocol process module by internal interface.The present invention realizes FC AE ASM protocol chips, while having the function of on-chip processor and piece outdoor main unit dual control chip system.
Description
Technical field
The invention belongs to computer hardware technologies, are related to a kind of circuit structure of FC-AE-ASM protocol processing chips.
Background technology
The anonymity of FC-AE-ASM (optical-fibre channel avionics environment anonymity submit message) protocol definition FC (optical-fibre channel) carries
Hand over message, the country not yet realizes the chip of the agreement, external since technology blockage also can be with without detailed enforceable data
It uses for reference.
Invention content
Goal of the invention：
The present invention, which provides, a kind of can realize FC-AE-ASM agreements by the circuit structure of FC-AE-ASM protocol chips
Chip.
Technical solution：
The user data of host memory is moved on piece to send by DMA sendaisles and is buffered, will be sent in buffering
Data are packaged according to FC-AE-ASM agreements and are sent to FC networks；The FC-AE-ASM protocol frame solutions that will be received from FC networks
Frame, and the user data obtained after frame decoding is stored on piece to receive and is buffered, start DMA receiving channels and on piece is received into buffering
User data is moved to host memory.
A kind of FC-AE-ASM protocol processing chips circuit structure, including processor module, General Porcess Unit, host connect
Mouth mold block, FC-AE-ASM protocol process module, processor module and General Porcess Unit are connected by PLB buses with OPB buses
Together, meanwhile, FC-AE-ASM protocol process module is also connected in PLB buses, and host interface module is assisted with FC-AE-ASM
View processing module is connected by internal interface, wherein processor module realizes the management of Resources on Chip, and General Porcess Unit is used
Software load when chip powers on, host interface module provide management interface and data channel, FC-AE-ASM for piece outdoor main unit
Protocol process module realizes the data encapsulation for meeting FC-AE-ASM agreements and solution packet function.
The FC-AE-ASM protocol process module includes sending buffering, sending control channel, receive buffering, receive control
Channel and register group and information exchange area, wherein register group connects PLB buses, while passing through register interface and master
Machine interface module connects, and information exchange area connects host interface module and PLB buses, sends buffering connection host interface module
With transmission control channel, buffering connection host interface module and reception control channel are received, control channel and register group are sent
With transmission buffering connection, control channel and register group and reception buffering connection are received.
Register group is defined to be led outside with the relevant one group of register of FC-AE-ASM protocol processes, processor module and piece
Machine can configure this group of register to complete the transmission-receiving function of FC-AE-ASM frames, and information exchange area is realized by twoport, place
The exchange of chunk data can be carried out by information exchange area by managing device module and piece outdoor main unit, and piece outdoor main unit leads to data to be sent
It crosses DMA sendaisles to move to the transmission buffering of on piece, sends control channel and be packaged concurrently to sending the data in buffering
It send to FC networks, receives control channel and parse the FC-AE-ASM protocol frames received from FC networks, and by the number after parsing
The data-moving in buffering will be received to piece outdoor main unit memory by DMA receiving channels to buffering, piece outdoor main unit is received according to storage.
The transmission control channel and reception control channel of the FC-AE-ASM protocol process module connect comprising two-way FC
Mouthful.
The processor is PowerPC460 processors, and working frequency is 250MHz and 125MHz.
The General Porcess Unit, software load when being powered on for chip, including internal chiasma switch module
CrossBar, command memory I-SRAM, data storage D-SRAM, external memory controller interface EMC, general purpose timer
TIMER, bus interface IIC, universal input output GPIO, serial ports UART, interrupt control unit VIC are internally integrated；In addition, in described
Portion cross switch module CrossBar, command memory I-SRAM, data storage D-SRAM, external memory controller interface
EMC is connected in PLB buses, the general purpose timer TIMER, be internally integrated bus interface IIC, universal input output GPIO,
Serial ports UART is connected in OPB buses, and interrupt control unit VIC is connect with processor, OPB buses and PLB buses pass through bridge simultaneously
Connection.
The PLB buses use 128 bit data widths, OPB buses to use 64 or 32 bit data widths.
The host interface module uses PCIe host interface, wherein the PCIe host interface compatible with PCI e v1.1 rule
Model, operating mode are 4 lines, while backward compatible 1 line, line rate 2.5Gbps.
Advantageous effect：
It is an advantage of the invention that：A kind of FC-AE-ASM protocol processing chips circuit structure provided by the invention, passes through PCIe
Host interface module and FC-AE-ASM protocol process module realize envelope of the piece outdoor main unit user data to FC-AE-ASM agreements
The frame decoding function of function and FC-AE-ASM protocol frames to piece outdoor main unit user data is filled, while passing through processor module and host
Interface module realizes the dual control management of on-chip processor and piece outdoor main unit to FC-AE-ASM protocol chips, entire chip circuit
The chip for realizing FC-AE-ASM agreements has broken external monopolization, has milestone significance.
Description of the drawings：
Fig. 1 is FC-AE-ASM protocol processing chip circuit structure diagrams；
In figure, 1- processor modules, 2- General Porcess Unit, 3- host interface modules, 4-FC-AE-ASM protocol processes moulds
It is deposited outside block, 5- internal chiasma switch module CrossBar, 6- command memory I-SRAM, 7- data storages D-SRAM, 8-
Memory controller interface EMC, 9- general purpose timer TIMER, 10- are internally integrated the output of bus interface IIC, 11- universal input
GPIO, 12- serial ports UART, 13- interrupt control unit VIC, 14- information exchange area, 15- register groups, 16- send control channel,
17- receives control channel, 18- on pieces send buffering, 19- on pieces receive buffering.
Specific implementation mode
The present invention will be further described with reference to the accompanying drawings and examples:
Referring to Fig. 1, FC-AE-ASM protocol processing chips circuit structure of the present invention includes processor module 1, general procedure
Unit 2, host interface module 3, FC-AE-ASM protocol process module 4, processor 1 and General Porcess Unit 2 pass through PLB buses
It links together with OPB buses, meanwhile, FC-AE-ASM protocol process module 4 is connected in PLB buses.In addition, host interface
Module 3 is connect with FC-AE-ASM protocol process module 4.Wherein, processor module 1 realizes the management of Resources on Chip, general place
Software load when reason unit 2 is powered on for chip, host interface module 3 provides management interface for piece outdoor main unit and data are logical
Road, FC-AE-ASM protocol process module 4 realize the data encapsulation for meeting FC-AE-ASM agreements and solution packet function.
The FC-AE-ASM protocol process module 4 includes sending buffering 18, sending control channel 16, receive buffering 19, connect
Receive control channel 17 and register group 15 and information exchange area 14, wherein register group 15 connects PLB buses, passes through simultaneously
Register interface is connect with host interface module 3, and information exchange area 14 connects host interface module 3 and PLB buses, is sent slow
18 connection host interface module 3 of punching and transmission control channel 16, receive 19 connection host interface module 3 of buffering and reception control is logical
Road 17, sends control channel 18 and register group 15 and sends buffering 18 and connect, reception control channel 17 and register group 15 and
Receive 19 connection of buffering.
Register group 15 define with the relevant one group of register of FC-AE-ASM protocol processes, outside processor module 1 and piece
Host can configure this group of register to complete the transmission-receiving function of FC-AE-ASM frames, and information exchange area 14 is by twoport reality
Existing, processor module 1 and piece outdoor main unit can be by the exchanges of the progress of information exchange area 14 chunk data, and piece outdoor main unit will be to be sent
Data by DMA sendaisles move on piece transmission buffer 18, send control channel 16 to send buffering 18 in number
According to being packaged and being sent to FC networks, receives control channel 17 and solve the FC-AE-ASM protocol frames received from FC networks
Analysis, and the reception that the data after parsing are stored on piece is buffered 19, piece outdoor main unit will be received in buffering by DMA receiving channels
Data-moving to piece outdoor main unit memory.
The transmission control channel 16 and reception control channel 17 of the FC-AE-ASM protocol process module 4 include bilateral
Road FC interfaces.Binary channels FC interfaces realize FC-AE-ASM agreements；Line rate 1.0625Gbps, 2.125Gbps may be selected；It adopts
High speed serial parallel exchange circuit is realized with analog circuit, using digital circuit FC-AE-ASM agreements and other functions；Simulation with
Numerical portion interface uses self defined interface.
The processor module 1 is PowerPC460, PowerPC470 and similar processor；The processor running frequency
It may be selected；Selection mode is that piece outer pin wire jumper selects and software configuration selects.Processor module 1 is for controlling entire chip
Work and management.
The General Porcess Unit 2 includes internal chiasma switch module CrossBar5, command memory I-SRAM6, data
Memory D-SRAM7, external memory controller interface EMC8, bus interface IIC10, general purpose timer are internally integrated
TIMER9, universal input output GPIO11, serial ports UART12, interrupt control unit VIC13；The internal chiasma switch module
CrossBar5, command memory I-SRAM6, data storage D-SRAM7, external memory controller interface EMC8 are connected to
It is described to be internally integrated bus interface IIC10, general purpose timer TIMER9, universal input output GPIO11, serial ports in PLB buses
UART12 is connected in OPB buses, and interrupt control unit VIC13 is connect with processor module 1, OPB buses and PLB buses are logical simultaneously
It passes a bridge and connects.
The PLB buses use 128 bit data widths, OPB buses to use 64 or 32 bit data widths.
The host interface module 3 uses PCIe host interface, wherein the PCIe host interface compatible with PCI e v1.1
Specification, 4Lanes is backward compatible 1Lane；Line rate 2.5Gbps.Host interface module 3 is realized external for connecting external host
Control and management of the host to FC-AE-ASM protocol processing chips.
A kind of FC-AE-ASM protocol processing chips circuit structure provided by the invention by PCIe host interface modules and
FC-AE-ASM protocol process module realizes encapsulation function and FC-AE- of the piece outdoor main unit user data to FC-AE-ASM agreements
ASM protocol frames while being realized to the frame decoding function of piece outdoor main unit user data by processor module and host interface module
The dual control management of on-chip processor and piece outdoor main unit to FC-AE-ASM protocol chips, entire chip circuit realize FC-AE-ASM
The chip of agreement.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is explained in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that：It still may be used
With technical scheme described in the above embodiments is modified or equivalent replacement of some of the technical features；
And these modifications or replacements, various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (8)
1. a kind of FC-AE-ASM protocol processing chips circuit structure, which is characterized in that including processor module, general procedure list
Member, host interface module, FC-AE-ASM protocol process module, processor module and General Porcess Unit by PLB buses and
OPB buses link together, meanwhile, FC-AE-ASM protocol process module is also connected in PLB buses, in addition, host interface mould
Block is connect with FC-AE-ASM protocol process module by internal interface, wherein processor module realizes the pipe of Resources on Chip
Reason, software load when General Porcess Unit is powered on for chip, host interface module provide management interface for piece outdoor main unit
And data channel, FC-AE-ASM protocol process module realize the data encapsulation for meeting FC-AE-ASM agreements and solution packet function.
2. FC-AE-ASM protocol processing chips circuit structure according to claim 1, which is characterized in that the FC-AE-
ASM protocol process module include send buffering, send control channel, receive buffering, receive control channel and register group and
Information exchange area, wherein register group connects PLB buses, while being connect with host interface module by register interface, information
Interactive areas connects host interface module and PLB buses, sends buffering connection host interface module and sends control channel, receives
Buffering connects host interface module and receives control channel, sends control channel and register group and transmission buffering connection, receives
Control channel and register group and reception buffering connection.
3. FC-AE-ASM protocol processing chips circuit structure according to claim 2, which is characterized in that register group is fixed
Justice and FC-AE-ASM protocol processes relevant one group of registers, processor module and piece outdoor main unit can be to this group of registers
It is configured to complete the transmission-receiving function of FC-AE-ASM frames, information exchange area is realized by twoport, processor module and piece outdoor main unit
The exchange of chunk data can be carried out by information exchange area, piece outdoor main unit moves data to be sent by DMA sendaisles
Transmission on piece buffers, and sends control channel and is packaged and is sent to FC networks to sending the data in buffering, and receives control
Channel processed parses the FC-AE-ASM protocol frames received from FC networks, and the data after parsing are stored to reception and are buffered,
Piece outdoor main unit will receive the data-moving in buffering to piece outdoor main unit memory by DMA receiving channels.
4. FC-AE-ASM protocol processing chips circuit structure according to claim 2, which is characterized in that the FC-AE-
ASM protocol process module starts control channel and receives control channel to include two-way FC interfaces.
5. FC-AE-ASM protocol processing chips circuit structure according to claim 1, which is characterized in that the processor
For PowerPC460 processors, working frequency is 250MHz and 125MHz.
6. FC-AE-ASM protocol processing chips circuit structure according to claim 1, which is characterized in that the general place
Software load of reason unit when being powered on for chip, including internal chiasma switch module CrossBar, command memory I-SRAM,
Data storage D-SRAM, external memory controller interface EMC, general purpose timer TIMER, be internally integrated bus interface IIC,
Universal input exports GPIO, serial ports UART, interrupt control unit VIC；In addition, the internal chiasma switch module CrossBar, referring to
Memory I-SRAM, data storage D-SRAM, external memory controller interface EMC is enabled to be connected in PLB buses, it is described logical
With timer TIMER, be internally integrated bus interface IIC, universal input output GPIO, serial ports UART are connected in OPB buses, in
It is disconnected that controller VIC is connect with processor, OPB buses and PLB buses are connect by bridging simultaneously.
7. FC-AE-ASM protocol processing chips circuit structure according to claim 1, which is characterized in that the PLB buses
Using 128 bit data widths, OPB buses use 64 or 32 bit data widths.
8. FC-AE-ASM protocol processing chips circuit structure according to claim 1, which is characterized in that the host connects
Mouth mold block uses PCIe host interface, wherein and the PCIe host interface compatible with PCI e v1.1 specifications, operating mode are 4 lines,
Backward compatible 1 line simultaneously, line rate 2.5Gbps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201611139641.0A CN108614800A (en) | 2016-12-12 | 2016-12-12 | FC-AE-ASM protocol processing chip circuit structures |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611139641.0A CN108614800A (en) | 2016-12-12 | 2016-12-12 | FC-AE-ASM protocol processing chip circuit structures |
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| CN201611139641.0A Pending CN108614800A (en) | 2016-12-12 | 2016-12-12 | FC-AE-ASM protocol processing chip circuit structures |
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Cited By (1)
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| CN109684101A (en) * | 2018-12-12 | 2019-04-26 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of FC_AE_ASM network protocol processing engine circuit |
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Application publication date: 20181002 |