CN109684101B - FC_AE_ASM protocol processing engine circuit - Google Patents
FC_AE_ASM protocol processing engine circuit Download PDFInfo
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- CN109684101B CN109684101B CN201811523231.5A CN201811523231A CN109684101B CN 109684101 B CN109684101 B CN 109684101B CN 201811523231 A CN201811523231 A CN 201811523231A CN 109684101 B CN109684101 B CN 109684101B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/546—Message passing systems or structures, e.g. queues
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/12—Protocol engines
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Abstract
The invention belongs to the technical field of computers, and provides an FC_AE_ASM protocol processing engine circuit, which comprises: the system comprises an FC_AE_ASM message processing module (1), a host interface module (2), an FC-2 processing module (3), a time synchronization module (4) and a register access interface module (5). The invention provides a pure hardware circuit implementation method for the application of the FC-AE-ASM protocol, which is not limited by the number of supporting message IDs and the shared buffer area of the same type of messages, and has the advantages of configurable buffer area number, strong expansibility and more flexible use.
Description
Technical Field
The invention belongs to the technical field of computers, and relates to an FC_AE_ASM protocol processing engine circuit.
Background
The FC (fiber Channel) is a first choice of a new generation of airborne main communication network of a fighter plane by the inherent technical advantages of high Gbit transmission rate, high anti-interference capability, light weight, suitability for high-speed long-distance transmission and the like, the implementation of the FC_AE_ASM protocol is the core and key of FC network development, and the FC_AE_ASM protocol processing engine circuit provided by the invention does not limit the number of supporting message IDs and the shared buffer area of the same type of messages, and has the advantages of configurable buffer area number, strong expansibility and flexible use.
Disclosure of Invention
The invention aims to:
the invention provides an FC_AE_ASM protocol processing engine circuit, which does not limit the number of supporting message IDs and the shared buffer area of the same type of messages, and has the advantages of configurable buffer area number, strong expansibility and more flexible use.
The technical scheme is as follows:
the technical scheme of the invention is as follows:
an fcae ASM protocol processing engine circuit comprising: the system comprises an FC_AE_ASM message processing module 1, a host interface module 2, an FC-2 processing module 3, a time synchronization module 4 and a register access interface module 5;
fc_ae_asm message processing module 1: the receiving and dispatching scheduling is carried out according to the network data message types, the receiving and dispatching of each data type adopts a queue management mode, the data is organized in an ASM format, and the configuration management of ASM messages is realized through a register access interface module 5;
host interface module 2: the method comprises the steps of realizing the access of a host to internal resources of the FC_AE_ASM message processing module 1, the interruption of the FC_AE_ASM message processing module 1 to the host, and the DMA access of the FC_AE_ASM message processing module 1 to a host memory;
FC-2 processing module 3: the method comprises the steps that messages processed by the FC_AE_ASM message processing module 1 are organized into FC frames and sent to an FC network; the FC frame is received and submitted to the FC_AE_ASM message processing module 1 for processing;
time synchronization module 4: realizing local equipment RTC clock, global task system RTC clock and global network calendar time;
register access interface module 5: an interface for controlling internal resource access of the FC-ASM protocol processing module is provided.
The fc_ae_asm message processing module 1 adopts a scheduling mode based on a service queue type, and the message transceiving flow is as follows:
and (3) message sending:
-message transmission supports configuration of three service type queues, an urgent message transmission queue, an event message transmission queue, and a stream message transmission queue;
-wherein the immediate message and event message send queues support a maximum of 32 buffer unit management, and the streaming message send queues support a maximum of 16 buffer unit management;
-filling the data to be transmitted into any logic space (1-32) in the pre-allocated queue when the emergency or event message is transmitted, and filling the address of the data to be transmitted into the buffer management register when the stream message is transmitted;
-subsequently completing the message transmission scheduling by the transmission scheduler according to the priority configuration information.
And (3) receiving a message:
-message receiving supports configuration of three service type queues, namely an emergency message sending queue, an event message sending queue and a stream message sending queue;
wherein the urgent message and event message reception queues support a maximum of 512 buffer unit management,
the streaming message receive queue supports a maximum of 32 buffer unit management. All message IDs share memory space in the same type of queue;
when an emergency or event message is received, the logic stores the same type of data into the currently available logic units according to the sequence of the reception, and then informs the user of taking the data;
when receiving the stream message, the logic stores the received complete data into the currently available logic units according to the sequence, and then informs the user to fetch the data.
The beneficial effects are that:
the invention provides a pure hardware circuit implementation method for the application of the FC-AE-ASM protocol, which is not limited by the number of supporting message IDs and the shared buffer area of the same type of messages, and has the advantages of configurable buffer area number, strong expansibility and more flexible use.
Drawings
Fig. 1 is a circuit configuration diagram of the fc_ae_asm protocol processing engine.
Detailed Description
The technical scheme of the invention is clearly and completely described below with reference to the accompanying drawings and the specific embodiments. It is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments, and that all other embodiments obtained by a person skilled in the art without making creative efforts based on the embodiments in the present invention are within the protection scope of the present invention.
As shown in fig. 1, an fc_ae_asm protocol processing engine circuit, which is characterized in that the circuit comprises 5 parts: the system comprises an FC_AE_ASM message processing module 1, a host interface module 2, an FC-2 processing module 3, a time synchronization module 4 and a register access interface module 5. Wherein:
fc_ae_asm message processing module 1: the receiving and dispatching scheduling is carried out according to the network data message types, the receiving and dispatching of each data type adopts a queue management mode, the data is organized in an ASM format, and the configuration management of ASM messages is realized through a register access interface module 5;
host interface module 2: the method comprises the steps of realizing the access of a host to internal resources of the FC_AE_ASM message processing module 1, the interruption of the FC_AE_ASM message processing module 1 to the host, and the DMA access of the FC_AE_ASM message processing module 1 to a host memory;
FC-2 processing module 3: the method comprises the steps that messages processed by the FC_AE_ASM message processing module 1 are organized into FC frames and sent to an FC network; the FC frame is received and submitted to the FC_AE_ASM message processing module 1 for processing;
time synchronization module 4: realizing local equipment RTC clock, global task system RTC clock and global network calendar time;
register access interface module 5: an interface for controlling internal resource access of the FC-ASM protocol processing module is provided.
An fc_ae_asm protocol processing engine circuit, wherein the fc_ae_asm message processing module 1 adopts a scheduling mode based on a service queue type, and the messaging flow is as follows:
a. and (3) message sending:
-message transmission supports configuration of three service type queues, an urgent message transmission queue, an event message transmission queue, and a stream message transmission queue;
-wherein the immediate message and event message send queues support a maximum of 32 buffer unit management, and the streaming message send queues support a maximum of 16 buffer unit management;
-filling the data to be transmitted into any logic space (1-32) in the pre-allocated queue when the emergency or event message is transmitted, and filling the address of the data to be transmitted into the buffer management register when the stream message is transmitted;
-subsequently completing the message transmission scheduling by the transmission scheduler according to the priority configuration information.
b. And (3) receiving a message:
-message receiving supports configuration of three service type queues, namely an emergency message sending queue, an event message sending queue and a stream message sending queue;
-wherein the urgent message and event message receive queues support a maximum of 512 buffer units management, and the stream message receive queues support a maximum of 32 buffer units management. All message IDs share memory space in the same type of queue;
when an emergency or event message is received, the logic stores the same type of data into the currently available logic units according to the sequence of the reception, and then informs the user of taking the data;
when receiving the stream message, the logic stores the received complete data into the currently available logic units according to the sequence, and then informs the user to fetch the data.
Claims (1)
1. An fcae ASM protocol processing engine circuit, comprising: the system comprises an FC_AE_ASM message processing module (1), a host interface module (2), an FC-2 processing module (3), a time synchronization module (4) and a register access interface module (5);
fc_ae_asm message processing module (1): the receiving and dispatching are carried out according to the network data message types, the receiving and dispatching of each data type adopts a queue management mode, the data is organized in an ASM format, and the configuration management of ASM messages is realized through a register access interface module (5);
host interface module (2): the method comprises the steps of realizing the access of a host to internal resources of an FC_AE_ASM message processing module (1), the interruption of the FC_AE_ASM message processing module (1) to the host, and the DMA access of the FC_AE_ASM message processing module (1) to a host memory;
FC-2 processing module (3): the method comprises the steps of organizing information processed by an FC_AE_ASM information processing module (1) into FC frames and sending the FC frames to an FC network; completing the receiving of the FC frame and submitting the FC frame to an FC_AE_ASM message processing module (1) for processing;
time synchronization module (4): realizing local equipment RTC clock, global task system RTC clock and global network calendar time;
register access interface module (5): an interface for controlling the internal resource access of the FC-ASM protocol processing module is provided,
the FC_AE_ASM message processing module (1) adopts a scheduling mode based on a service queue type, and the message receiving and transmitting flow is as follows:
a. and (3) message sending:
-message transmission supports configuration of three service type queues, an urgent message transmission queue, an event message transmission queue, and a stream message transmission queue;
-wherein the immediate message and event message send queues support a maximum of 32 buffer unit management, and the streaming message send queues support a maximum of 16 buffer unit management;
-filling the data to be transmitted into any logic space (1-32) in the pre-allocated queue when the emergency or event message is transmitted, and filling the address of the data to be transmitted into the buffer management register when the stream message is transmitted;
-subsequently completing, by the transmission scheduler, message transmission scheduling according to the priority configuration information;
b. and (3) receiving a message:
-message receiving supports configuration of three service type queues, namely an emergency message sending queue, an event message sending queue and a stream message sending queue;
-wherein the urgent message and event message receive queues support a maximum of 512 buffer unit management, and the stream message receive queues support a maximum of 32 buffer unit management; all message IDs share memory space in the same type of queue;
when an emergency or event message is received, the logic stores the same type of data into the currently available logic units according to the sequence of the reception, and then informs the user of taking the data;
when receiving the stream message, the logic stores the received complete data into the currently available logic units according to the sequence, and then informs the user to fetch the data.
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| CN109684101B true CN109684101B (en) | 2023-07-07 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101795266A (en) * | 2009-12-31 | 2010-08-04 | 中国航空工业集团公司第六三一研究所 | Avionics any source multicast (ASM) protocol controller |
| CN102201978A (en) * | 2011-03-21 | 2011-09-28 | 北京航空航天大学 | Avionics fiber channel network multiprotocol controller and controlling method thereof |
| EP2523117A1 (en) * | 2011-05-11 | 2012-11-14 | Telefonaktiebolaget L M Ericsson (publ) | Interface module for HW block |
| CN105515673A (en) * | 2015-11-27 | 2016-04-20 | 中国航空工业集团公司沈阳飞机设计研究所 | Optical fiber channel node card |
| CN108614800A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | FC-AE-ASM protocol processing chip circuit structures |
| CN108614756A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | FC-AE-ASM protocol processing chips with temp monitoring function |
-
2018
- 2018-12-12 CN CN201811523231.5A patent/CN109684101B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101795266A (en) * | 2009-12-31 | 2010-08-04 | 中国航空工业集团公司第六三一研究所 | Avionics any source multicast (ASM) protocol controller |
| CN102201978A (en) * | 2011-03-21 | 2011-09-28 | 北京航空航天大学 | Avionics fiber channel network multiprotocol controller and controlling method thereof |
| EP2523117A1 (en) * | 2011-05-11 | 2012-11-14 | Telefonaktiebolaget L M Ericsson (publ) | Interface module for HW block |
| CN105515673A (en) * | 2015-11-27 | 2016-04-20 | 中国航空工业集团公司沈阳飞机设计研究所 | Optical fiber channel node card |
| CN108614800A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | FC-AE-ASM protocol processing chip circuit structures |
| CN108614756A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | FC-AE-ASM protocol processing chips with temp monitoring function |
Non-Patent Citations (4)
| Title |
|---|
| FC-AE-ASM协议优化设计;李攀等;《计算机工程与科学》;20170215(第02期);70-74 * |
| FC协议处理芯片设计与实现;李攀;《电子技术应用》;20160905;第42卷(第9期);147-151 * |
| Modeling and Performance Analysis of FC-AE-ASM Which Base on PETRI Net Theory;Bin Liu;《2010 International Conference on Computational Intelligence and Software Engineering》;20101230;1-4 * |
| 李攀.FC协议处理芯片设计与实现.《电子技术应用》.2016,第42卷(第9期), * |
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