CN108569045A - Printer paper correction circuit - Google Patents

Printer paper correction circuit Download PDF

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Publication number
CN108569045A
CN108569045A CN201810571143.6A CN201810571143A CN108569045A CN 108569045 A CN108569045 A CN 108569045A CN 201810571143 A CN201810571143 A CN 201810571143A CN 108569045 A CN108569045 A CN 108569045A
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CN
China
Prior art keywords
resistance
pin
photoisolator
channel mosfet
npn type
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Application number
CN201810571143.6A
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Chinese (zh)
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CN108569045B (en
Inventor
熊浩
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Tianjin Bridge College Of Kunming University Of Science And Technology
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Tianjin Bridge College Of Kunming University Of Science And Technology
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Priority to CN201810571143.6A priority Critical patent/CN108569045B/en
Publication of CN108569045A publication Critical patent/CN108569045A/en
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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J11/00—Devices or arrangements  of selective printing mechanisms, e.g. ink-jet printers or thermal printers, for supporting or handling copy material in sheet or web form
    • B41J11/0045—Guides for printing material
    • B41J11/0055—Lateral guides, e.g. guides for preventing skewed conveyance of printing material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J29/00—Details of, or accessories for, typewriters or selective printing mechanisms not otherwise provided for
    • B41J29/38—Drives, motors, controls or automatic cut-off devices for the entire printing mechanism
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Landscapes

  • Nozzles For Electric Vacuum Cleaners (AREA)
  • Control Of Direct Current Motors (AREA)

Abstract

The present invention provides a kind of printer paper correction circuit comprising XOR gate U1（1）, NAND gate U2:A（2）, resistance R1（3）, photoisolator U3（4）, resistance R6（5）, resistance R2（6）, NPN type triode Q1（7）, direct current correction motor M1（8）, N-channel MOS FET Q3（9）, resistance R3（10）, P-channel MOSFET Q4（11）, NAND gate U2:B（12）, photoisolator U4（13）, resistance R4（14）, resistance R5（15）, resistance R7（16）, NPN type triode Q2（17）, N-channel MOS FET Q5（18）, direct current correction motor M2（19）, P-channel MOSFET Q6（20）.The circuit is by accurately controlling left and right correction motor, can during printing continuous real-time deviation correcting, to which paperboard rate be greatly lowered, simultaneously because what is used is all customary components, circuit cost is very low, 90% or more paperboard rate can be reduced using this circuit, after being especially used for a long time, still can preserve excellent paperboard rate.

Description

Printer paper correction circuit
Technical field
The present invention relates to a kind of printer paper correction circuits.
Background technology
Currently, the laser printer that various laser printers especially price is relatively low, is all not provided with special circuit It is strong inclined to carry out printing paper, it is very big that mechanical systems, this presence such as tool clamping are mainly stepped up using rubber wheel or touched to strong folk prescription formula The problem of, if mold holding paper is tightly more prone to very much paperboard, the longer rubber wheel usage time the more not clamping, can increasingly be easy card Paperboard rate is greatly lowered in paper, a kind of cheap feasible scheme of market in urgent need.
Invention content
The present invention to solve the above-mentioned problems, provides a kind of printer paper correction circuit.The circuit passes through to left and right Correction motor accurately controls, can during printing continuous real-time deviation correcting, to be greatly lowered paperboard rate, at the same by All it is customary components in what is used, circuit cost is very low, can reduce by 90% or more paperboard rate using this circuit, especially make for a long time With later, excellent paperboard rate still can be preserved.
To achieve the above object, the technical solution adopted by the present invention is：It includes XOR gate U1（1）, NAND gate U2:A （2）, resistance R1（3）, photoisolator U3（4）, resistance R6（5）, resistance R2（6）, NPN type triode Q1（7）, direct current correction electricity Machine M1（8）, N-channel MOS FET Q3（9）, resistance R3（10）, P-channel MOSFET Q4（11）, NAND gate U2:B（12）, photoelectricity every From device U4（13）, resistance R4（14）, resistance R5（15）, resistance R7（16）, NPN type triode Q2（17）, N-channel MOS FET Q5 （18）, direct current correction motor M2（19）, P-channel MOSFET Q6（20）.The XOR gate U1（1）Pin 1 meets P1.0 and NAND gate U2:A（2）Pin 2, XOR gate U1（1）Pin 2 meets P1.1 and NAND gate U2:B（12）Pin 5, XOR gate U1（1）Pin 3 connects non- Door U2:A（2）Pin 1 and NAND gate U2:B（12）Pin 4；Photoisolator U3（4）1 connecting resistance R1 of pin（3）Lower end and photoelectricity Isolator U4（13）Pin 1, photoisolator U3（4）Pin 2 meets NAND gate U2:A（2）Pin 3, photoisolator U3（4）Draw 3 connecting resistance R2 of foot（6）Left end, resistance R3（10）Upper end and N-channel MOS FET Q3 control grid, photoisolator U3（4）Pin 4 meet+12V DC power supply and photoisolator U4（13）Pin 4；Resistance R1（3）Upper termination+5V DC power supplies；Photoisolator U4（13）Pin 2 meets NAND gate U2:B（12）Pin 6, photoisolator U4（13）3 connecting resistance R4 of pin（14）Upper end, resistance R （15）Left end and N-channel MOS FET Q5（18）Control grid；NPN type triode Q1（7）Base stage connecting resistance R2（6）Right end, NPN Type triode Q1（7）Emitter ground connection, resistance R（10）Lower end and N-channel MOS FET Q3（9）Source electrode, NPN type triode Q1（7） Collector connecting resistance R6（5）Lower end and P-channel MOSFET Q4（11）Control grid；NPN type triode Q2（17）Base stage connecting resistance R5（15）Right end, NPN type triode Q2（17）Emitter ground connection, resistance R4（14）Lower end and N-channel MOS FET Q5（18）Source Pole, NPN type triode Q2（17）Collector connecting resistance R7（16）Lower end and P-channel MOSFET Q6（20）Control grid；Direct current entangles Inclined motor M1 cathode meet N-channel MOS FET Q3（9）Source electrode, direct current correction motor M1 anodes meet P-channel MOSFET Q4（11）Leakage Pole；Direct current correction motor M2（19）Cathode meets N-channel MOS FET Q5（18）Source electrode, direct current correction motor M2（19）Anode connects P ditches Road MOSFET Q6（20）Drain electrode；+ 24V DC power supply connecting resistances R（5）Upper end, resistance R7（16）Upper end, P-channel MOSFET Q4 （11）Source electrode and P-channel MOSFET Q6（20）Source electrode.
Further, the XOR gate U1（1）Pin 1 meets P1.0 and NAND gate U2:A（2）Pin 2, XOR gate U1（1）Draw Foot 2 meets P1.1 and NAND gate U2:B（12）Pin 5, XOR gate U1（1）Pin 3 meets NOT gate U2:A（2）Pin 1 and NAND gate U2:B （12）Pin 4；Photoisolator U3（4）1 connecting resistance R1 of pin（3）Lower end and photoisolator U4（13）Pin 1, Phototube Coupling Device U3（4）Pin 2 meets NAND gate U2:A（2）Pin 3, photoisolator U3（4）3 connecting resistance R2 of pin（6）Left end, resistance R3 （10）Upper end and N-channel MOS FET Q3 control grid, photoisolator U3（4）Pin 4 connects+12V DC power supply and Phototube Coupling Device U4（13）Pin 4；Resistance R1（3）Upper termination+5V DC power supplies；Photoisolator U4（13）Pin 2 meets NAND gate U2:B （12）Pin 6, photoisolator U4（13）3 connecting resistance R4 of pin（14）Upper end, resistance R（15）Left end and N-channel MOS FET Q5 （18）Control grid；NPN type triode Q1（7）Base stage connecting resistance R2（6）Right end, NPN type triode Q1（7）Emitter ground connection, Resistance R（10）Lower end and N-channel MOS FET Q3（9）Source electrode, NPN type triode Q1（7）Collector connecting resistance R6（5）Lower end and P Channel mosfet Q4（11）Control grid；NPN type triode Q2（17）Base stage connecting resistance R5（15）Right end, NPN type triode Q2 （17）Emitter ground connection, resistance R4（14）Lower end and N-channel MOS FET Q5（18）Source electrode, NPN type triode Q2（17）Collector Connecting resistance R7（16）Lower end and P-channel MOSFET Q6（20）Control grid；Direct current correction motor M1 cathode meet N-channel MOS FET Q3（9）Source electrode, direct current correction motor M1 anodes meet P-channel MOSFET Q4（11）Drain electrode；Direct current correction motor M2（19）Cathode connects N-channel MOS FET Q5（18）Source electrode, direct current correction motor M2（19）Anode meets P-channel MOSFET Q6（20）Drain electrode；+ 24V is straight Galvanic electricity source connecting resistance R（5）Upper end, resistance R7（16）Upper end, P-channel MOSFET Q4（11）Source electrode and P-channel MOSFET Q6 （20）Source electrode.
The XOR gate U1（1）Model 74LS86.
The NAND gate U2:A（2）With NAND gate U2:B（12）Model 74HC03.
The photoisolator U3（4）With NAND gate U2:B（12）Model PC817A.
The NPN type triode Q1（7）With NPN type triode Q2（17）Model 2N1711.
The N-channel MOS FET Q3（9）With N-channel MOS FET Q5（18）Model IRFE024.
The P-channel MOSFET Q4（11）With P-channel MOSFET Q6（20）Model IRFE9024.
The invention has the advantages that：The present invention circuit, can by being accurately controlled to left and right correction motor Continuous real-time deviation correcting during printing, to which paperboard rate be greatly lowered, simultaneously because what is used is all customary components, electricity Road cost is very low, and 90% or more paperboard rate can be reduced using this circuit, after being especially used for a long time, still can preserve excellent Paperboard rate.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments of invention without having to pay creative labor, may be used also for those of ordinary skill in the art With obtain other attached drawings according to these attached drawings.
Fig. 1 is the structural diagram of the present invention.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, printer paper correction circuit includes XOR gate U1（1）, NAND gate U2:A（2）, resistance R1（3）、 Photoisolator U3（4）, resistance R6（5）, resistance R2（6）, NPN type triode Q1（7）, direct current correction motor M1（8）, N-channel MOSFET Q3（9）, resistance R3（10）, P-channel MOSFET Q4（11）, NAND gate U2:B（12）, photoisolator U4（13）, electricity Hinder R4（14）, resistance R5（15）, resistance R7（16）, NPN type triode Q2（17）, N-channel MOS FET Q5（18）, direct current correction Motor M2（19）, P-channel MOSFET Q6（20）.The XOR gate U1（1）Pin 1 meets P1.0 and NAND gate U2:A（2）Pin 2, XOR gate U1（1）Pin 2 meets P1.1 and NAND gate U2:B（12）Pin 5, XOR gate U1（1）Pin 3 meets NOT gate U2:A（2）Pin 1 and NAND gate U2:B（12）Pin 4；Photoisolator U3（4）1 connecting resistance R1 of pin（3）Lower end and photoisolator U4（13） Pin 1, photoisolator U3（4）Pin 2 meets NAND gate U2:A（2）Pin 3, photoisolator U3（4）3 connecting resistance R2 of pin （6）Left end, resistance R3（10）Upper end and N-channel MOS FET Q3 control grid, photoisolator U3（4）Pin 4 connects+12V DC Power supply and photoisolator U4（13）Pin 4；Resistance R1（3）Upper termination+5V DC power supplies；Photoisolator U4（13）Pin 2 Meet NAND gate U2:B（12）Pin 6, photoisolator U4（13）3 connecting resistance R4 of pin（14）Upper end, resistance R（15）Left end and N Channel mosfet Q5（18）Control grid；NPN type triode Q1（7）Base stage connecting resistance R2（6）Right end, NPN type triode Q1 （7）Emitter ground connection, resistance R（10）Lower end and N-channel MOS FET Q3（9）Source electrode, NPN type triode Q1（7）Collector connects electricity Hinder R6（5）Lower end and P-channel MOSFET Q4（11）Control grid；NPN type triode Q2（17）Base stage connecting resistance R5（15）It is right End, NPN type triode Q2（17）Emitter ground connection, resistance R4（14）Lower end and N-channel MOS FET Q5（18）Source electrode, NPN type three Pole pipe Q2（17）Collector connecting resistance R7（16）Lower end and P-channel MOSFET Q6（20）Control grid；Direct current correction motor M1 is negative Pole meets N-channel MOS FET Q3（9）Source electrode, direct current correction motor M1 anodes meet P-channel MOSFET Q4（11）Drain electrode；Direct current is rectified a deviation Motor M2（19）Cathode meets N-channel MOS FET Q5（18）Source electrode, direct current correction motor M2（19）Anode meets P-channel MOSFET Q6 （20）Drain electrode；+ 24V DC power supply connecting resistances R（5）Upper end, resistance R7（16）Upper end, P-channel MOSFET Q4（11）Source electrode and P Channel mosfet Q6（20）Source electrode.The XOR gate U1（1）Model 74LS86.The NAND gate U2:A（2）And NAND gate U2:B（12）Model 74HC03.The photoisolator U3（4）With NAND gate U2:B（12）Model PC817A.It is described NPN type triode Q1（7）With NPN type triode Q2（17）Model 2N1711.The N-channel MOS FET Q3（9）With N ditches Road MOSFET Q5（18）Model IRFE024.The P-channel MOSFET Q4（11）With P-channel MOSFET Q6（20）Type Number be IRFE9024.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention With within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention god.

Claims (3)

  1. The circuit 1. printer paper is rectified a deviation, it is characterised in that：Including XOR gate U1（1）, NAND gate U2:A（2）, resistance R1（3）、 Photoisolator U3（4）, resistance R6（5）, resistance R2（6）, NPN type triode Q1（7）, direct current correction motor M1（8）, N-channel MOSFET Q3（9）, resistance R3（10）, P-channel MOSFET Q4（11）, NAND gate U2:B（12）, photoisolator U4（13）, electricity Hinder R4（14）, resistance R5（15）, resistance R7（16）, NPN type triode Q2（17）, N-channel MOS FET Q5（18）, direct current correction Motor M2（19）, P-channel MOSFET Q6（20）；The XOR gate U1（1）Pin 1 meets P1.0 and NAND gate U2:A（2）Pin 2, XOR gate U1（1）Pin 2 meets P1.1 and NAND gate U2:B（12）Pin 5, XOR gate U1（1）Pin 3 meets NOT gate U2:A（2）Pin 1 and NAND gate U2:B（12）Pin 4；Photoisolator U3（4）1 connecting resistance R1 of pin（3）Lower end and photoisolator U4（13） Pin 1, photoisolator U3（4）Pin 2 meets NAND gate U2:A（2）Pin 3, photoisolator U3（4）3 connecting resistance R2 of pin （6）Left end, resistance R3（10）Upper end and N-channel MOS FET Q3 control grid, photoisolator U3（4）Pin 4 connects+12V DC Power supply and photoisolator U4（13）Pin 4；Resistance R1（3）Upper termination+5V DC power supplies；Photoisolator U4（13）Pin 2 Meet NAND gate U2:B（12）Pin 6, photoisolator U4（13）3 connecting resistance R4 of pin（14）Upper end, resistance R（15）Left end and N Channel mosfet Q5（18）Control grid；NPN type triode Q1（7）Base stage connecting resistance R2（6）Right end, NPN type triode Q1 （7）Emitter ground connection, resistance R（10）Lower end and N-channel MOS FET Q3（9）Source electrode, NPN type triode Q1（7）Collector connects electricity Hinder R6（5）Lower end and P-channel MOSFET Q4（11）Control grid；NPN type triode Q2（17）Base stage connecting resistance R5（15）It is right End, NPN type triode Q2（17）Emitter ground connection, resistance R4（14）Lower end and N-channel MOS FET Q5（18）Source electrode, NPN type three Pole pipe Q2（17）Collector connecting resistance R7（16）Lower end and P-channel MOSFET Q6（20）Control grid；Direct current correction motor M1 is negative Pole meets N-channel MOS FET Q3（9）Source electrode, direct current correction motor M1 anodes meet P-channel MOSFET Q4（11）Drain electrode；Direct current is rectified a deviation Motor M2（19）Cathode meets N-channel MOS FET Q5（18）Source electrode, direct current correction motor M2（19）Anode meets P-channel MOSFET Q6 （20）Drain electrode；+ 24V DC power supply connecting resistances R（5）Upper end, resistance R7（16）Upper end, P-channel MOSFET Q4（11）Source electrode and P Channel mosfet Q6（20）Source electrode.
  2. The circuit 2. printer paper according to claim 1 is rectified a deviation, it is characterised in that：The XOR gate U1（1）Model For 74LS86.
  3. The circuit 3. printer paper according to claim 1 is rectified a deviation, it is characterised in that：The NAND gate U2:A（2）With with NOT gate U2:B（12）Model 74HC03.
CN201810571143.6A 2018-06-06 2018-06-06 Printer paper deviation rectifying circuit Active CN108569045B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810571143.6A CN108569045B (en) 2018-06-06 2018-06-06 Printer paper deviation rectifying circuit

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Application Number Priority Date Filing Date Title
CN201810571143.6A CN108569045B (en) 2018-06-06 2018-06-06 Printer paper deviation rectifying circuit

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CN108569045A true CN108569045A (en) 2018-09-25
CN108569045B CN108569045B (en) 2024-01-30

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030020231A1 (en) * 2001-07-27 2003-01-30 Xerox Corporation Printer sheet deskewing system
CN203126144U (en) * 2013-03-19 2013-08-14 南京富士通计算机设备有限公司 Automatic paper deviation rectifying mechanism of needle printer
CN104773573A (en) * 2015-02-12 2015-07-15 华中科技大学 Deviation rectification control system for flexible film conveying
CN106739555A (en) * 2016-12-30 2017-05-31 南京富士通电子信息科技股份有限公司 A kind of printer paper deviation-rectifying system and method for correcting error
CN208411126U (en) * 2018-06-06 2019-01-22 昆明理工大学津桥学院 Printer paper correction circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030020231A1 (en) * 2001-07-27 2003-01-30 Xerox Corporation Printer sheet deskewing system
CN203126144U (en) * 2013-03-19 2013-08-14 南京富士通计算机设备有限公司 Automatic paper deviation rectifying mechanism of needle printer
CN104773573A (en) * 2015-02-12 2015-07-15 华中科技大学 Deviation rectification control system for flexible film conveying
CN106739555A (en) * 2016-12-30 2017-05-31 南京富士通电子信息科技股份有限公司 A kind of printer paper deviation-rectifying system and method for correcting error
CN208411126U (en) * 2018-06-06 2019-01-22 昆明理工大学津桥学院 Printer paper correction circuit

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