CN105843314B - Low-power consumption low level wake-up circuit - Google Patents
Low-power consumption low level wake-up circuit Download PDFInfo
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- CN105843314B CN105843314B CN201610177524.7A CN201610177524A CN105843314B CN 105843314 B CN105843314 B CN 105843314B CN 201610177524 A CN201610177524 A CN 201610177524A CN 105843314 B CN105843314 B CN 105843314B
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- resistance
- pmos transistor
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- wake
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
Low-power consumption low level wake-up circuit, belongs to field of circuit control, and the present invention exists without before low level signal input to solve conventional one-piece machine wake-up circuit, and quiescent current is big, the problem of quiescent dissipation is high.The present invention includes PMOS transistor P1, diode VD1, resistance R1~R5；Anti-parallel diodes VD1 between PMOS transistor P1 source electrode and drain electrode；PMOS transistor P1 grid connects resistance R1 one end and resistance R2 one end simultaneously, and the resistance R1 other end and PMOS transistor P1 source electrode connect power supply VCC simultaneously；Resistance R1 other end access low imput；PMOS transistor P1 drain electrode connection resistance R3 one end, the resistance R3 other end connects resistance R4 one end and resistance R5 one end simultaneously；Resistance R4 another termination；The resistance R5 other end is used as CPU wake-up signal output ends.
Description
Technical field
The invention belongs to field of circuit control.
Background technology
The wake-up circuit of conventional singlechip CPU is generally high level wake-up circuit, and low level wake-up circuit is larger because of power consumption
And hardly use, traditional wake-up circuit is as shown in figure 1, R20=4R10, VCC=5V in this circuit, when defeated without low level signal
It is fashionable, A point voltages 5V, VT10 conducting, B points voltage is 1V, and CPU is not waken up；When there is low level signal input, VT10 is cut
Only, B points voltage is 5V, and CPU is waken up.This method without low level signal before inputting, and VT10 is constantly in conducting state,
Quiescent current is improved, quiescent dissipation is increased.
The content of the invention
The invention aims to solve conventional one-piece machine wake-up circuit exist without low level signal input before, Static Electro
Stream is big, and there is provided a kind of low-power consumption low level wake-up circuit for the problem of quiescent dissipation is high.
Low-power consumption low level wake-up circuit of the present invention, it includes PMOS transistor P1, diode VD1, resistance R1, electricity
Hinder R2, resistance R3, resistance R4 and resistance R5；
Anti-parallel diodes VD1 between PMOS transistor P1 source electrode and drain electrode；
PMOS transistor P1 grid connects resistance R1 one end and resistance R2 one end simultaneously, the resistance R1 other end and
PMOS transistor P1 source electrode connects power supply VCC simultaneously；Resistance R1 other end access low imput；
PMOS transistor P1 drain electrode connection resistance R3 one end, the resistance R3 other end connects resistance R4 one end simultaneously
With resistance R5 one end；Resistance R4 another termination；The resistance R5 other end is used as CPU wake-up signal output ends.
Advantages of the present invention：Low-power consumption low level wake-up circuit of the present invention is controlled whether using the break-make of metal-oxide-semiconductor
Wake-up signal is inputted, quiescent dissipation is greatly reduced.
Brief description of the drawings
Fig. 1 is the physical circuit figure of traditional wake-up circuit；
Fig. 2 is the physical circuit figure of low-power consumption low level wake-up circuit of the present invention.
Embodiment
Embodiment one：Illustrate present embodiment with reference to Fig. 2, low-power consumption low level is called out described in present embodiment
Awake circuit, it includes PMOS transistor P1, diode VD1, resistance R1, resistance R2, resistance R3, resistance R4 and resistance R5；
Anti-parallel diodes VD1 between PMOS transistor P1 source electrode and drain electrode；
PMOS transistor P1 grid connects resistance R1 one end and resistance R2 one end simultaneously, the resistance R1 other end and
PMOS transistor P1 source electrode connects power supply VCC simultaneously；Resistance R1 other end access low imput；
PMOS transistor P1 drain electrode connection resistance R3 one end, the resistance R3 other end connects resistance R4 one end simultaneously
With resistance R5 one end；Resistance R4 another termination；The resistance R5 other end is used as CPU wake-up signal output ends.
VCC takes 12V, resistance R3 and resistance R4 resistance equal.R1 resistance is more than 1.4 times of R2 resistances.
Operation principle：When being inputted without low level signal, A point voltages are similar to 12V, P1 gate-source voltage UG=US, no
There is US>UGThis turn-on condition, P1 is not turned on, B point no-voltage low levels, and CPU wakes up end without input, and CPU is not waken up.
When there is low level signal input, A point voltages are the voltage after R1, R2 partial pressure, about 5V；P1 source voltage is
12V, because of 12V>5V, i.e. P1 gate-source voltage US>UG, P1 conductings, B points voltage is 6V, CPU wake-up signal output port voltages
Divide obtained voltage equally for R4 and R3, CPU, which wakes up end, input high level signal, and CPU is waken up.
Claims (3)
1. low-power consumption low level wake-up circuit, it is characterised in that it includes PMOS transistor P1, diode VD1, resistance R1, electricity
Hinder R2, resistance R3, resistance R4 and resistance R5；
Anti-parallel diodes VD1 between PMOS transistor P1 source electrode and drain electrode；
PMOS transistor P1 grid connects resistance R1 one end and resistance R2 one end, resistance the R1 other end and PMOS simultaneously
Transistor P1 source electrode connects power supply VCC simultaneously；Resistance R2 other end access low imput；
PMOS transistor P1 drain electrode connection resistance R3 one end, the resistance R3 other end connects resistance R4 one end and electricity simultaneously
Hinder R5 one end；Resistance R4 other end ground connection；The resistance R5 other end is used as CPU wake-up signal output ends.
2. low-power consumption low level wake-up circuit according to claim 1, it is characterised in that VCC takes 12V, resistance R3 and resistance
R4 resistance is equal.
3. low-power consumption low level wake-up circuit according to claim 1 or claim 2, it is characterised in that R1 resistances are more than R2 resistances
1.4 again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610177524.7A CN105843314B (en) | 2016-03-24 | 2016-03-24 | Low-power consumption low level wake-up circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610177524.7A CN105843314B (en) | 2016-03-24 | 2016-03-24 | Low-power consumption low level wake-up circuit |
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| Publication Number | Publication Date |
|---|---|
| CN105843314A CN105843314A (en) | 2016-08-10 |
| CN105843314B true CN105843314B (en) | 2017-10-27 |
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| CN201610177524.7A Active CN105843314B (en) | 2016-03-24 | 2016-03-24 | Low-power consumption low level wake-up circuit |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788485B (en) * | 2016-11-29 | 2019-05-14 | 华南理工大学 | A kind of low-power transmitters |
| CN107145207B (en) * | 2017-05-06 | 2020-04-07 | 湖南融和微电子有限公司 | Wake-up circuit in standby state mode |
| CN107978808A (en) * | 2017-12-06 | 2018-05-01 | 合肥国盛电池科技有限公司 | The vehicle lithium battery group reminded based on online failure |
| CN109888879A (en) * | 2019-03-22 | 2019-06-14 | 威海优微科技有限公司 | A kind of mobile power source circuit Rouser |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7472291B2 (en) * | 2005-04-15 | 2008-12-30 | Shuttle Inc. | Method and apparatus for integrating ACPI functionality and power button functionality into a single power key |
| CN202084963U (en) * | 2011-06-08 | 2011-12-21 | 深圳市萨伏特电池电源有限公司 | Mobile power source capable of preventing failure of touchpad |
| CN103760798B (en) * | 2014-01-03 | 2016-09-28 | 洛阳理工学院 | A kind of solar energy storage intelligent management system |
| CN104300639B (en) * | 2014-10-20 | 2016-06-22 | 中颖电子股份有限公司 | There is low power consumpting state and automatically waken up the power battery pack management system of function |
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