CN208411126U - Printer paper correction circuit - Google Patents
Printer paper correction circuit Download PDFInfo
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- CN208411126U CN208411126U CN201820863569.4U CN201820863569U CN208411126U CN 208411126 U CN208411126 U CN 208411126U CN 201820863569 U CN201820863569 U CN 201820863569U CN 208411126 U CN208411126 U CN 208411126U
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- resistance
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- photoisolator
- channel mosfet
- npn type
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Abstract
The utility model provides a kind of printer paper correction circuit comprising XOR gate U1, NAND gate U2:A, resistance R1, photoisolator U3, resistance R6, resistance R2, NPN type triode Q1, direct current correction motor M1, N-channel MOS FET Q3, resistance R3, P-channel MOSFET Q4, NAND gate U2:B, photoisolator U4, resistance R4, resistance R5, resistance R7, NPN type triode Q2, N-channel MOS FET Q5, direct current correction motor M2, P-channel MOSFET Q6.The circuit passes through the accurate control to left and right correction motor, can during printing continuous real-time deviation correcting, to which paper jam rate be greatly lowered, simultaneously because what is used is all customary components, circuit cost is very low, 90% or more paper jam rate can be reduced using this circuit, after being especially used for a long time, still can save excellent paper jam rate.
Description
Technical field
The utility model relates to a kind of printer paper correction circuits.
Background technique
Currently, the laser printer that various laser printers especially price is relatively low, is all not provided with special circuit
It is strong partially to carry out printing paper, it is very big that mechanical systems, this presence such as tool clamping are mainly stepped up using rubber wheel or touched to strong folk prescription formula
The problem of, if mold holding paper is tightly more easier very much paper jam, the longer rubber wheel the more not clamping using the time, can increasingly be easy card
Paper jam rate is greatly lowered in paper, a kind of cheap feasible scheme of market in urgent need.
Utility model content
The utility model to solve the above-mentioned problems, provides a kind of printer paper correction circuit.The circuit by pair
The accurate control of left and right correction motor, can during printing continuous real-time deviation correcting, so that paper jam rate be greatly lowered,
Simultaneously because what is used is all customary components, circuit cost is very low, can reduce by 90% or more paper jam rate using this circuit, especially
After long-time service, excellent paper jam rate still can be saved.
In order to achieve the above purposes, the technical solution adopted by the utility model is:, and it includes XOR gate U1(1), NAND gate U2:
A(2), resistance R1(3), photoisolator U3(4), resistance R6(5), resistance R2(6), NPN type triode Q1(7), direct current correction
Motor M1(8), N-channel MOS FET Q3(9), resistance R3(10), P-channel MOSFET Q4(11), NAND gate U2:B(12), photoelectricity
Isolator U4(13), resistance R4(14), resistance R5(15), resistance R7(16), NPN type triode Q2(17), N-channel MOS FET
Q5(18), direct current rectify a deviation motor M2(19), P-channel MOSFET Q6(20).The XOR gate U1(1) pin 1 connect P1.0 and with it is non-
Door U2:A(2) pin 2, XOR gate U1(1) pin 2 meets P1.1 and NAND gate U2:B(12) and pin 5, XOR gate U1(1) pin 3 connects
NOT gate U2:A(2) pin 1 and NAND gate U2:B(12) pin 4；Photoisolator U3(4) 1 connecting resistance R1(3 of pin) lower end and light
Electric isolator U4(13) pin 1, photoisolator U3(4) pin 2 meets NAND gate U2:A(2) and pin 3, photoisolator U3(4)
3 connecting resistance R2(6 of pin) left end, resistance R3(10) upper end and N-channel MOS FET Q3 control grid, photoisolator U3(4) draw
Foot 4 connects+12V DC power supply and photoisolator U4(13) pin 4；Resistance R1(3) on termination+5V DC power supply；Phototube Coupling
Device U4(13) pin 2 meets NAND gate U2:B(12) pin 6, photoisolator U4(13) 3 connecting resistance R4(14 of pin) upper end, resistance
R5(15) left end and N-channel MOS FET Q5(18) control grid；NPN type triode Q1(7) base stage connecting resistance R2(6) right end,
NPN type triode Q1(7) emitter ground connection, resistance R3(10) lower end and N-channel MOS FET Q3(9) source electrode, NPN type triode
Q1(7) collector connecting resistance R6(5) lower end and P-channel MOSFET Q4(11) control grid；NPN type triode Q2(17) base stage
Connecting resistance R5(15) right end, NPN type triode Q2(17) emitter ground connection, resistance R4(14) lower end and N-channel MOS FET Q5
(18) source electrode, NPN type triode Q2(17) collector connecting resistance R7(16) lower end and P-channel MOSFET Q6(20) control grid；
Direct current correction motor M1 cathode meet N-channel MOS FET Q3(9) source electrode, direct current correction motor M1 anode meet P-channel MOSFET Q4
(11) it drains；Direct current is rectified a deviation motor M2(19) cathode meets N-channel MOS FET Q5(18) source electrode, direct current rectifies a deviation motor M2(19) just
Pole meets P-channel MOSFET Q6(20) drain electrode；+ 24V DC power supply connecting resistance R6(5) upper end, resistance R7(16) upper end, P-channel
MOSFET Q4(11) source electrode and P-channel MOSFET Q6(20) source electrode.
Further, the XOR gate U1(1) pin 1 meets P1.0 and NAND gate U2:A(2) pin 2, XOR gate U1(1) draw
Foot 2 meets P1.1 and NAND gate U2:B(12) pin 5, XOR gate U1(1) pin 3 meets NOT gate U2:A(2) pin 1 and NAND gate U2:B
(12) pin 4；Photoisolator U3(4) 1 connecting resistance R1(3 of pin) lower end and photoisolator U4(13) pin 1, Phototube Coupling
Device U3(4) pin 2 meets NAND gate U2:A(2) pin 3, photoisolator U3(4) 3 connecting resistance R2(6 of pin) left end, resistance R3
(10) upper end and N-channel MOS FET Q3 control grid, photoisolator U3(4) pin 4 connects+12V DC power supply and Phototube Coupling
Device U4(13) pin 4；Resistance R1(3) on termination+5V DC power supply；Photoisolator U4(13) pin 2 meets NAND gate U2:B
(12) pin 6, photoisolator U4(13) 3 connecting resistance R4(14 of pin) upper end, resistance R5(15) left end and N-channel MOS FET
Q5(18 grid) is controlled；NPN type triode Q1(7) base stage connecting resistance R2(6) right end, NPN type triode Q1(7) emitter connects
Ground, resistance R3(10) lower end and N-channel MOS FET Q3(9) source electrode, NPN type triode Q1(7) collector connecting resistance R6(5) under
End and P-channel MOSFET Q4(11) control grid；NPN type triode Q2(17) base stage connecting resistance R5(15) right end, NPN type three
Pole pipe Q2(17) emitter ground connection, resistance R4(14) lower end and N-channel MOS FET Q5(18) source electrode, NPN type triode Q2(17)
Collector connecting resistance R7(16) lower end and P-channel MOSFET Q6(20) control grid；Direct current correction motor M1 cathode connects N-channel
MOSFET Q3(9) source electrode, direct current correction motor M1 anode meet P-channel MOSFET Q4(11) drain electrode；Direct current correction motor M2
(19) cathode meets N-channel MOS FET Q5(18) source electrode, direct current rectifies a deviation motor M2(19) anode meets P-channel MOSFET Q6(20) leakage
Pole；+ 24V DC power supply connecting resistance R6(5) upper end, resistance R7(16) upper end, P-channel MOSFET Q4(11) source electrode and P-channel
MOSFET Q6(20) source electrode.
The XOR gate U1(1) model 74LS86.
The NAND gate U2:A(2) and NAND gate U2:B(12) model 74HC03.
The photoisolator U3(4) and NAND gate U2:B(12) model PC817A.
The NPN type triode Q1(7) and NPN type triode Q2(17) model 2N1711.
The N-channel MOS FET Q3(9) and N-channel MOS FET Q5(18) model IRFE024.
The P-channel MOSFET Q4(11) and P-channel MOSFET Q6(20) model IRFE9024.
The utility model has the following beneficial effects: the utility model circuit passes through to the accurate of left and right correction motor
Control, can during printing continuous real-time deviation correcting, so that paper jam rate is greatly lowered, simultaneously because what is used is all normal
Element is advised, circuit cost is very low, can reduce by 90% or more paper jam rate using this circuit, still can be with after being especially used for a long time
Save excellent paper jam rate.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, before not making the creative labor property
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of the utility model.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without creative efforts
Every other embodiment obtained, fall within the protection scope of the utility model.
As shown in Figure 1, printer paper correction circuit include XOR gate U1(1), NAND gate U2:A(2), resistance R1(3),
Photoisolator U3(4), resistance R6(5), resistance R2(6), NPN type triode Q1(7), direct current rectify a deviation motor M1(8), N-channel
MOSFET Q3(9), resistance R3(10), P-channel MOSFET Q4(11), NAND gate U2:B(12), photoisolator U4(13), electricity
Hinder R4(14), resistance R5(15), resistance R7(16), NPN type triode Q2(17), N-channel MOS FET Q5(18), direct current correction
Motor M2(19), P-channel MOSFET Q6(20).The XOR gate U1(1) pin 1 meets P1.0 and NAND gate U2:A(2) pin 2,
XOR gate U1(1) pin 2 meets P1.1 and NAND gate U2:B(12) pin 5, XOR gate U1(1) pin 3 meets NOT gate U2:A(2) pin
1 and NAND gate U2:B(12) pin 4；Photoisolator U3(4) 1 connecting resistance R1(3 of pin) lower end and photoisolator U4(13)
Pin 1, photoisolator U3(4) pin 2 meets NAND gate U2:A(2) pin 3, photoisolator U3(4) 3 connecting resistance R2 of pin
(6) left end, resistance R3(10) upper end and N-channel MOS FET Q3 control grid, photoisolator U3(4) pin 4 connects+12V DC
Power supply and photoisolator U4(13) pin 4；Resistance R1(3) on termination+5V DC power supply；Photoisolator U4(13) pin 2
Meet NAND gate U2:B(12) pin 6, photoisolator U4(13) 3 connecting resistance R4(14 of pin) upper end, resistance R5(15) left end and N
Channel mosfet Q5(18) control grid；NPN type triode Q1(7) base stage connecting resistance R2(6) right end, NPN type triode Q1
(7) emitter ground connection, resistance R3(10) lower end and N-channel MOS FET Q3(9) source electrode, NPN type triode Q1(7) collector connects
Resistance R6(5) lower end and P-channel MOSFET Q4(11) control grid；NPN type triode Q2(17) base stage connecting resistance R5(15) it is right
End, NPN type triode Q2(17) emitter ground connection, resistance R4(14) lower end and N-channel MOS FET Q5(18) source electrode, NPN type three
Pole pipe Q2(17) collector connecting resistance R7(16) lower end and P-channel MOSFET Q6(20) control grid；Direct current correction motor M1 is negative
Pole meets N-channel MOS FET Q3(9) source electrode, direct current correction motor M1 anode meet P-channel MOSFET Q4(11) drain electrode；Direct current correction
Motor M2(19) cathode meets N-channel MOS FET Q5(18) source electrode, direct current rectifies a deviation motor M2(19) anode meets P-channel MOSFET Q6
(20) it drains；+ 24V DC power supply connecting resistance R6(5) upper end, resistance R7(16) upper end, P-channel MOSFET Q4(11) source electrode and P
Channel mosfet Q6(20) source electrode.The XOR gate U1(1) model 74LS86.The NAND gate U2:A(2) and NAND gate
U2:B(12 model 74HC03).The photoisolator U3(4) and NAND gate U2:B(12) model PC817A.It is described
NPN type triode Q1(7) and NPN type triode Q2(17) model 2N1711.The N-channel MOS FET Q3(9) and N ditch
Road MOSFET Q5(18) model IRFE024.The P-channel MOSFET Q4(11) and P-channel MOSFET Q6(20) type
Number be IRFE9024.
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
Within the spirit and principle of utility model, any modification, equivalent replacement, improvement and so on should be included in the utility model
Protection scope within.
Claims (7)
1. printer paper rectify a deviation circuit, it is characterised in that: including XOR gate U1(1), NAND gate U2:A(2), resistance R1(3),
Photoisolator U3(4), resistance R6(5), resistance R2(6), NPN type triode Q1(7), direct current rectify a deviation motor M1(8), N-channel
MOSFET Q3(9), resistance R3(10), P-channel MOSFET Q4(11), NAND gate U2:B(12), photoisolator U4(13), electricity
Hinder R4(14), resistance R5(15), resistance R7(16), NPN type triode Q2(17), N-channel MOS FET Q5(18), direct current correction
Motor M2(19), P-channel MOSFET Q6(20)；The XOR gate U1(1) pin 1 meets P1.0 and NAND gate U2:A(2) pin 2,
XOR gate U1(1) pin 2 meets P1.1 and NAND gate U2:B(12) pin 5, XOR gate U1(1) pin 3 meets NOT gate U2:A(2) pin
1 and NAND gate U2:B(12) pin 4；Photoisolator U3(4) 1 connecting resistance R1(3 of pin) lower end and photoisolator U4(13)
Pin 1, photoisolator U3(4) pin 2 meets NAND gate U2:A(2) pin 3, photoisolator U3(4) 3 connecting resistance R2 of pin
(6) left end, resistance R3(10) upper end and N-channel MOS FET Q3 control grid, photoisolator U3(4) pin 4 connects+12V DC
Power supply and photoisolator U4(13) pin 4；Resistance R1(3) on termination+5V DC power supply；Photoisolator U4(13) pin 2
Meet NAND gate U2:B(12) pin 6, photoisolator U4(13) 3 connecting resistance R4(14 of pin) upper end, resistance R5(15) left end and N
Channel mosfet Q5(18) control grid；NPN type triode Q1(7) base stage connecting resistance R2(6) right end, NPN type triode Q1
(7) emitter ground connection, resistance R3(10) lower end and N-channel MOS FET Q3(9) source electrode, NPN type triode Q1(7) collector connects
Resistance R6(5) lower end and P-channel MOSFET Q4(11) control grid；NPN type triode Q2(17) base stage connecting resistance R5(15) it is right
End, NPN type triode Q2(17) emitter ground connection, resistance R4(14) lower end and N-channel MOS FET Q5(18) source electrode, NPN type three
Pole pipe Q2(17) collector connecting resistance R7(16) lower end and P-channel MOSFET Q6(20) control grid；Direct current correction motor M1 is negative
Pole meets N-channel MOS FET Q3(9) source electrode, direct current correction motor M1 anode meet P-channel MOSFET Q4(11) drain electrode；Direct current correction
Motor M2(19) cathode meets N-channel MOS FET Q5(18) source electrode, direct current rectifies a deviation motor M2(19) anode meets P-channel MOSFET Q6
(20) it drains；+ 24V DC power supply connecting resistance R6(5) upper end, resistance R7(16) upper end, P-channel MOSFET Q4(11) source electrode and P
Channel mosfet Q6(20) source electrode.
The circuit 2. printer paper according to claim 1 is rectified a deviation, it is characterised in that: the XOR gate U1(1) model
For 74LS86.
The circuit 3. printer paper according to claim 1 is rectified a deviation, it is characterised in that: the NAND gate U2:A(2) and with
NOT gate U2:B(12) model 74HC03.
The circuit 4. printer paper according to claim 1 is rectified a deviation, it is characterised in that: the photoisolator U3(4) and
NAND gate U2:B(12) model PC817A.
The circuit 5. printer paper according to claim 1 is rectified a deviation, it is characterised in that: the NPN type triode Q1(7) and
NPN type triode Q2(17) model 2N1711.
The circuit 6. printer paper according to claim 1 is rectified a deviation, it is characterised in that: the N-channel MOS FET Q3(9)
With the model IRFE024 of N-channel MOS FET Q5(18).
The circuit 7. printer paper according to claim 1 is rectified a deviation, it is characterised in that: the P-channel MOSFET Q4(11)
With the model IRFE9024 of P-channel MOSFET Q6(20).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820863569.4U CN208411126U (en) | 2018-06-06 | 2018-06-06 | Printer paper correction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820863569.4U CN208411126U (en) | 2018-06-06 | 2018-06-06 | Printer paper correction circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208411126U true CN208411126U (en) | 2019-01-22 |
Family
ID=65111346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820863569.4U Expired - Fee Related CN208411126U (en) | 2018-06-06 | 2018-06-06 | Printer paper correction circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208411126U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108569045A (en) * | 2018-06-06 | 2018-09-25 | 昆明理工大学津桥学院 | Printer paper correction circuit |
-
2018
- 2018-06-06 CN CN201820863569.4U patent/CN208411126U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108569045A (en) * | 2018-06-06 | 2018-09-25 | 昆明理工大学津桥学院 | Printer paper correction circuit |
| CN108569045B (en) * | 2018-06-06 | 2024-01-30 | 昆明理工大学津桥学院 | Printer paper deviation rectifying circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190122 Termination date: 20190606 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |