CN108565315A - Thin film semiconductor's photoelectric device with veining front surface and/or back surface - Google Patents
Thin film semiconductor's photoelectric device with veining front surface and/or back surface Download PDFInfo
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- CN108565315A CN108565315A CN201810340115.3A CN201810340115A CN108565315A CN 108565315 A CN108565315 A CN 108565315A CN 201810340115 A CN201810340115 A CN 201810340115A CN 108565315 A CN108565315 A CN 108565315A
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- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 9
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/52—PV systems with concentrators
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The present invention relates to thin film semiconductor's photoelectric devices with veining front surface and/or back surface.A kind of method for providing veining layer in the opto-electronic device is disclosed.Method includes depositing template layer on the first layer.Template layer has apparent inhomogeneities on thickness or in composition or in the two, including forms one or more islands to provide the possibility of at least one texturizing surfaces of island nitride layer.Method further includes that template layer and first layer are exposed to etch process to generate or change at least one texturizing surfaces.At least one texturizing surfaces changed cause light scattering in operation.
Description
The application be on 08 05th, 2015 the applying date, it is entitled " to have application No. is 201510475349.5
The divisional application of the application of thin film semiconductor's photoelectric device of veining front surface and/or back surface ".
Cross reference to related applications
The application is in " TEXTURING A LAYER IN AN submitting, entitled on January 19th, 2012
The United States Patent (USP) Shen of OPTOELECTRONIC DEVICE FOR IMPROVED ANGLE RANDOMIZATION OF LIGHT "
Part continuation application that please be the 13/354th, No. 175, the U.S. Patent application are hereby incorporated by reference in its entirety by reference.
Technical field
Embodiment of the present invention is usually directed to optoelectronic semiconductor component (such as photovoltaic device including solar cell),
And the method for manufacturing such devices.
Background technology
The purposes of photoelectric device such as photovoltaic device and light emitting diode (LED) becomes wide, because energy efficiency
Importance increases.In photovoltaic device such as solar cell, the knot of solar cell absorbs photon to generate electron hole pair,
The internal electric field that the electron hole pair is tied is separated to generate voltage, to convert light energy into electric energy.Ideal photovoltaic (PV)
The absorber layers of device impinge upon positive all photons of the PV devices towards light source by absorbing, because of open-circuit voltage (Voc)
Or short circuit current (Isc) proportional to luminous intensity.However, several loss mechanisms often interfere with the absorber layers of PV devices, the suction
Acceptor layer absorbs the positive all light for reaching device.For example, certain photons can pass through absorber layers any without generating
Electron hole pair and therefore from not contributeing to produce electricl energy by device.In other cases, the semiconductor layer of PV devices can
To be smooth and therefore can reflect the major part hit in photon, these photons are prevented in order to avoid reaching absorber layers.
Accordingly, there exist to increased efficiency photoelectric device and for compared with conventional photoelectric device manufacture to subtract
Few cost and larger flexibility manufacture the demand of the method for such photoelectric device.
Invention content
The open method for providing the veining layer in photoelectric device.Method includes that template layer is deposited on first layer
On.Template layer is apparent non-uniform on thickness or in composition, including forms one or more islands to provide island
The possibility of at least one texturizing surfaces of nitride layer.Method further includes that template layer and first layer are exposed to etch process to produce
Life changes at least one texturizing surfaces.At least one texturizing surfaces cause light scattering in operation.
The open method for providing photoelectric device.Method includes deposit absorbent body layer and deposition emitter layer.Method is also
Include that the first layer of the first material is deposited in emitter layer and absorber layers.In addition, method includes by the mould of the second material
Plate layer deposits on the first layer.Method further includes that template layer and first layer are exposed to etch process to generate or change at least one
A texturizing surfaces.At least one texturizing surfaces cause light scattering in operation.Finally, method includes that dielectric layer deposition exists
In island nitride layer and by deposition of metal on the dielectric layer.
The open method for providing photoelectric device.Method includes deposition emitter layer and deposit absorbent body layer.Method is also
Include that the first layer of the first material is deposited in emitter layer and absorber layers.In addition, method includes by the mould of the second material
Plate layer deposits on the first layer.Method further includes that template layer and first layer are exposed to etch process to generate or change at least one
A texturizing surfaces.At least one texturizing surfaces cause light scattering in operation.Finally, method includes depositing anti-reflecting layer
In island nitride layer.
Description of the drawings
Therefore attached drawing only the certain embodiments of illustration and is not to be construed as limiting range.
Figure 1A -1C show the top-down view of the template island nitride layer on first layer；
Fig. 2 describes the viewgraph of cross-section of the photovoltaic device according to certain embodiments described herein；
Fig. 3 A, 3B, 3C, 3D, 3E, 3F, 3G and 3H depiction 1 photovoltaic device viewgraph of cross-section, wherein island nitride layer
It is deposited on the base layer；
The viewgraph of cross-section of the photovoltaic device of Fig. 4 depictions 3, wherein semiconductor contact layer and dielectric layer have been deposited over
In island nitride layer；
The viewgraph of cross-section of the photovoltaic device of Fig. 5 depictions 4, wherein forming hole in the dielectric layer；
Fig. 6 A and 6B describe the vertical view of the different embodiments of mask, and the mask can be used to form in Figure 5
Hole in the dielectric layer shown；
The viewgraph of cross-section of the photovoltaic device of Fig. 7 depictions 5, wherein metal layer are deposited on the dielectric layer；
Fig. 8 is depicted in the cross of an embodiment of the photovoltaic cell that stripping technology is generated by the photovoltaic device of Fig. 7 later
Section view；
Fig. 9 describes the viewgraph of cross-section of another embodiment of the photovoltaic cell generated by the photovoltaic device of Fig. 3 A；
Figure 10 describes the viewgraph of cross-section of the photovoltaic cell of the veining layer scattering light on the back side that illustration passes through device；
Figure 11 describes photovoltaic device according to certain embodiments described herein, providing front lighting capture veining layer
Viewgraph of cross-section；
The viewgraph of cross-section of the photovoltaic device of Figure 12 depictions 11, wherein island nitride layer are deposited on the base layer；
And
The viewgraph of cross-section of the photovoltaic device of Figure 13 depictions 12, middle level have been deposited in island nitride layer.
Specific implementation mode
Embodiment of the present invention is usually directed to photoelectric device and technique, and relates more particularly to include one or more
It textures the optoelectronic semiconductor component of layer and is used to form the manufacturing process of such photoelectric device.
Herein, layer can be described as being deposited on other one or more layers.This term marker can be by
It is deposited directly to the top of other layers, or can indicate that one or more other layers can be deposited in certain embodiments
Between layer and other layers.In addition, other layers can be arranged in any order.
Term template layer herein is defined as instruction to be had significantly on thickness or in composition or in the two
The layer of inhomogeneities.This includes that thickness offset is so large that template layer is the possibility of multiple separate island.
When template layer and the layer under template layer are exposed to etchant or etch process, texturizing surfaces are generated or change.
Texturizing surfaces can cause light scattering, this can improve the capture of the light in photoelectric device.
Term island refers to material layer discontinuous in the plane, this allows etchant potentially to reach in lower section
Layer.Island nitride layer can form multiple apparent unconnected regions (Figure 1A), or can fully be connected but (be schemed with gap
1B), or the combination (Fig. 1 C) that both can be.Each of these figures show the template island nitride layer on first layer 112
152 top-down view.These layers are described in more detail herein.
Embodiment disclosed herein is related to capturing using the light of veining layer for larger device efficiency.
Fig. 2 illustrations are suitable for an embodiment party of the photovoltaic device 100 being used together with the embodiments described herein
The viewgraph of cross-section of case.Although the embodiments herein is related to photovoltaic device, the feature of description may be applied to other photoelectricity
Semiconductor devices such as LED, such as generated with scattering the light in device to provide increased or more efficiently light.
Device 100 includes being coupled with growth wafer 101 by being arranged in ELO releasing layers therebetween or sacrificial layer 104
Battery 120.Multiple epitaxial materials containing different constituents are deposited in photovoltaic device 100.Multiple epitaxial materials
It can be grown or otherwise be formed by the method appropriate for semiconductor growing.Battery 120 can for example be had
There is the battery based on GaAs of the layer made of group iii-v material.Group iii-v material is the film of epitaxially grown layer.
In certain embodiments, epitaxially grown layer can pass through the growth regulation III- during such as Seedling height rate gas-phase deposition
V races materials is formed.Seedling height rate depositing operation allows the growth rate more than 5 μm/hr, than such as from about 10 μm/hr or bigger,
Or up to about 100 μm/hr or bigger.Seedling height rate technique includes that wafer is heated in system of processing to about 550 DEG C or bigger
Depositing temperature, wafer is exposed to the deposition gases comprising precursor, for example gallium precursor gases and deposited for GaAs
The arsenic hydride of technique and the layer comprising GaAs is deposited on wafer.Deposition gases can include group V precursor, such as
Arsenic hydride, hydrogen phosphide or ammonia.
It as described herein, can be a plurality of types of heavy for depositing or being formed the depositing operation of group iii-v material
Product carries out in room.For example, can be used to grow, deposition or otherwise formed group iii-v material it is a kind of continuously into
Expect settling chamber in the commonly assigned U.S. Patent Application No. all submitted on May 29th, 2,009 12/475,131 and the 12/th
Described in 475, No. 169, they are hereby incorporated by reference in its entirety by reference.
Available layer and the certain examples for the method for being used to form such layer are on November 3rd, 2010 in device 100
It is disclosed in the Co-pending U.S. Patent Application the 12/939th, 077 of submission, and it is integrally incorporated this by quoting with it
Text.
In certain embodiments, one or more buffer layers 102 can be formed on growth wafer 101 to start shape
At photovoltaic device 100.Growth wafer 101 may include such as N-shaped or semi insulating material, and may include with it is one or more
The same or similar material of buffer layer then deposited.May include p-type material in other embodiments.
Sacrificial layer (ELO releasing layers) 104 can be deposited in growth wafer 101 or 102 (if present) of buffer layer.It is sacrificial
Domestic animal layer 104 can include material appropriate, such as aluminium arsenide (AlAs) or aluminium arsenide alloy, and be used to form in electricity
The lattice structure for the layer for including in pond 120, and be then etched and be removed during ELO techniques.
The layer of photovoltaic cell 120 can be deposited on sacrificial layer 104, be connect before may include in certain embodiments
Absorber layers 108 that contact layer 105, front window 106, neighbouring front window 106 are formed, emitter layer 110 and for veining
Basal layer 112.Preceding semiconductor contact layer 105 or boundary layer can be deposited on sacrificial layer 104.Preceding contact layer 105 is certain
Can be the layer of n doping in embodiment, including group iii-v material, such as GaAs.
Front window 106, also referred to as passivation layer can be formed on substrate 101 on sacrificial layer 104, or if it does,
It is formed on optional contact layer 105.Front window 106 can be it is transparent with allow incident photon pass through battery 120 just
Front window 106 on face is to the layer below other.In certain embodiments, front window 106 can include group iii-v material.
Absorber layers 108 can be formed in Window layer 106.Absorber layers 108 can include any Section III-V appropriate
Compound semiconductor, such as GaAs (GaAs).In certain embodiments, absorber layers 108 can be monocrystalline and can
To be that n is adulterated.Different embodiments can provide different doping concentrations, for example range is from about 1 × 1016cm-3To about 1
×1019cm-3。
In certain embodiments, emitter layer 110 can be formed in absorber layers 108.In certain embodiments,
Emitter layer 110 can be that p adulterates (such as p+Doping).Emitter layer 110 can include any group iii-v appropriate
Compound semiconductor and can be monocrystalline.For example, the doping concentration of the emitter layer 110 of severe p doping can from about 1 ×
1017cm-3To about 1 × 1020cm-3In the range of.In certain embodiments, emitter layer 110 can be with 108 shape of absorber layers
At hetero-junctions.
In certain embodiments, the contact with p-type emitter layer 110 of n-type absorber layer 108 is generated for absorbing photon
P-n junction.Other embodiments may include among the one or more between absorber layers 108 and emitter layer 110
Layer.Other embodiments can use the back of the body/emitter layer, and/or others of the substrate/absorber layers and n doping of p doping
The layer of p/n doping, to replace the layer of the n/p doping in description herein.
Basal layer 112 for veining can optionally be deposited over emitter layer 110.Basal layer 112 can carry
For first layer, and can be by contributing to island to be formed with the constituent component different from template layer, template layer is sunk
Product is used to texture purpose on the first layer.In certain embodiments, basal layer 112 can be that monocrystalline and p are adulterated
And with about 5 × 1017cm-3To about 2 × 1019cm-3Range in doping concentration.Basal layer 112 and template layer are below
In be described in more detail.In certain other embodiments, basal layer 112 is not included in device 100.For example, template
Layer (described below) can be deposited in emitter layer 110 or in absorber layers 108 (if on emitter layer).
Fig. 3 A are the cross sections according to the photovoltaic device 100 of an embodiment of the texturizing surfaces for being used as back reflector
Figure, the photovoltaic device 100 include the deposition template layer 140 on basal layer 112.Template layer 140 has inconsistent thickness, can
To cause the light reflection in device and light scattering, to increase light capture.
Used template layer in various embodiments can be different.In one embodiment, template layer has aobvious
The thickness inconsistency of work includes the possibility of multiple and different islands of mould material.In another embodiment, template
Layer has the inconsistency of composition, but may or may not have significant thickness inconsistency.
When the template layer in device is exposed to etchant or etching process with other layers, template layer can not be by significantly
Etching, or it can be etched (but with the slow rate of the rate being etched than the first layer that template layer is deposited thereon), or can
With with the rate being etched with the first layer that template layer is deposited thereon is suitable or is deposited thereon more than template layer first layer
The rate for the rate being etched is etched.As a result, template layer can (but not needing) formed or change texturizing surfaces mistake
It is now completely etched away in journey.Selectively, template layer still can be partially or entirely presented after etching process, but can be with
It is partially or entirely removed in the subsequent processing steps before the manufacture of photoelectric device is completed.
Template layer can have inconsistent composition.The different piece of template layer with different materials composition can be sudden and violent
It is etched with different rates when being exposed to etchant or etching process.In this way, template layer can be during the process of etching
It generates thickness inconsistency or increases its thickness inconsistency, even if thickness is consistent before etching.
The template layer with inconsistent thickness can be commonly known as island nitride layer before etching.Island growth can be down to
It is partially generated due to the strain between different materials, which is caused by the lattice mismatch between material.Selectively,
Island growth can be very thin due to island nitride layer and not form continuous layer and generate.Selectively, island growth can
To be generated due to dynamic etch during deposition process itself.
For example, in some embodiments, such as example embodiment shown in fig. 3a, Stranski-
Krastanov techniques can be used for forming template layer 140.The technique is related to depositing certain material, which is initially formed template
The wet layer 142 (it may include one or more individual layers) of layer material, then forms the island of identical material in wet layer 142
Shape object 144.In other embodiments, other kinds of island growth technique can be used.For example, Fig. 3 B show use
The formation of the island of Volmer-Weber techniques can not provide the wet of the template layer material of island growth on it
Layer, as described below.
Template layer 140 may include semi-conducting material, and can be the basal layer being deposited thereon with template layer 140
The different material of 112 material.In some embodiments, template layer 140 can be with the material bigger than basal layer 112
Band gap material.In some instances, template layer 140 may include phosphorus, gallium, aluminium, indium, arsenic, antimony, nitrogen, its derivative and/or
A combination thereof.For example, in some embodiments, basal layer 112 may include GaAs (GaAs) or aluminum gallium arsenide (AlGaAs), and
And template layer 140 may include indium gallium arsenic (InGaAs) or gallium arsenic antimony (GaAsSb).In other embodiments, basal layer 112
May include aluminum gallium arsenide (AlGaAs), and template layer 140 may include gallium phosphide (GaP).In other embodiments, substrate
Layer 112 may include indium arsenide (InAs), and template layer 140 may include indium arsenic antimony (InAsSb).In yet other reality
It applies in scheme, basal layer 112 may include gallium indium phosphorus (GaInP), and template layer 140 may include gallium phosphide (GaP) or phosphorus
Change aluminium (AlP).In yet other embodiments, basal layer 112 may include indium phosphide (InP), and template layer 140 can
To include indium phosphorus antimony (InPSb).In some embodiments, template layer may include gallium indium nitrogen arsenic (GaInNAs), gallium nitrogen arsenic
(GaNAs), gallium arsenic phosphide (GaAsP), aluminum gallium arsenide phosphorus (AlGaAsP) or gallium aluminium phosphorus (AlGaP).Any in these embodiments
It is a, derivative and/or the combination of these materials can be used.The material being doped can be used for template layer by some embodiments
140；It adulterates, and can have about 1 × 10 for example, material can be p17cm-3To about 2 × 1019cm-3Range in (ratio
Such as from about 1 × 1018cm-3) doping concentration.
In some embodiments, template layer 140 includes the folding with increase or the ability for maximizing scattering or reflected light
Penetrate the material of rate (n) and absorbability (k).For example, template layer 140 may include the transparent material for allowing light to pass through template layer.Such as
Term as used herein " transparent " refers to the negligible uptake in the wave-length coverage that photoelectric device operates.For example,
In some embodiments, template layer 140 can have the refractive index in the range of about 1 to about 3.5.In addition, in some realities
It applies in scheme, the material of template layer 140 can have about 0 to about 1 × 10-2Range in, than such as from about 1 × 10-3Or about 1 ×
10-4Absorbability (k).In some embodiments, template layer 140 may include multiple transparent layers.
In some embodiments, with used deposition parameter phase during previous the layer such as deposition of basal layer 112
Than the various parameters of depositing operation can be varied or adjusted, for the deposition of template layer 140.For example, the temperature of depositing operation
Degree, pressure, deposition gases and/or growth rate can be changed, as described in more detail below.
In figure 3 a, wet layer 142 and island 144 are deposited over substrate using Stranski-Krastanov techniques
On layer 112.Wet layer includes the complete film for the absorbate being accumulated in substrate, and wherein substrate is the base in described example
Bottom 112.Wet layer 142 can be grown using the material of deposition, further thereafter to deposit until realizing specific thicknesses
One or more islands 144 are caused to grow.Therefore, island 144 includes material identical with wet layer 142.Once wet layer 142
Critical thickness is had been carried out in Stranski-Krastanov techniques (such as by the chemical property of wet layer 144 and basal layer 112
Determined with physical property), then continued growth of the absorbate on basal layer 112 is tired in wet layer 142 by island 144
Product occurs, which is attributed to strain or stretching in wet layer material.
Island 144 provides the texturizing surfaces of island nitride layer 140.The growth of island 144 is controlled to increase or maximum
Change the angle random of light for being radiated on template layer 140 or being propagated across template layer 140.This angle randomization of light can be with
By adjusting or the different parameters (and thus cause growth be adjusted or customize) of growth conditions of customization island 144 make
Island obtains specific feature and increases or maximize.Some in different parameters include material of the deposition for template layer
Amount, depositing temperature, deposition pressure, the growth rate of template layer material, the V group element that is flowed in deposition gases and influence base
The composition of the mould material of lattice mismatch between bottom and template layer material.The amount of the template layer material deposited can influence
Island is grown.For example, the larger quantities of the material deposited is tended to encourage the growth of Stranski-Krastanov islands
(will be described in further detail below) is grown more than Volmer-Weber islands.
Another parameter that can be selected to the growth of control island 144 is included in the depositing operation of island nitride layer 140
The temperature that period provides.For example, temperature higher can be made to generate the island 144 with large-size.For depositing template
Some examples of the temperature range of layer 140 include about 600 DEG C to about 900 DEG C.
Another parameter of growth for controlling island 144 is the pressure provided during the deposition of template layer 140.Example
Such as, pressure bigger can be made to generate island 144 with a smaller size.It can be used for depositing the pressure model of template layer 140
Some examples enclosed include about 50 supports to about 600 supports.
Another parameter is the growth rate of template layer 140, can be controlled to influence the characteristic of veining layer.For example,
In some embodiments using Stranski-Krastanov techniques, the growth rate of template layer 140 can be controlled as
Than the growth rate using the standard before Stranski-Krastanov techniques faster.It in one example, can basis
Growth is controlled such as the Seedling height rate above with respect to other layers for depositing photoelectric device 100 described in epitaxially grown layer
Rate.In other embodiments, island 144 can grow slower, for example, if in some embodiments, to island
The better control of the special characteristic of shape object is desired, such as facet.In some embodiments, about 5 μ can be will be greater than
M/ hours growth rate ranges are used for template layer 140.
Another parameter that can be controlled is the V group element flowed in the deposition gases provided during deposition.For example, with
It can be with the Group V precursor and Group III precursor of certain ratio in the deposition gases for forming template layer 140.In some embodiments
In, V group element is hydrogen phosphide.The flow rate ratio can be controlled so that template growth is adjusted to desired characteristic.In general, for example,
The ratio of phosphatization hydrogen flowrate can be reduced relative to the flow rate ratio for previous sedimentary (for example, basal layer 112)
(that is, the ratio provided is low), to promote island to be formed.In some embodiments, deposition gases can have about 50:
1 to about 300:Hydrogen phosphide/Group III precursor in 1 range.
Another parameter that can be selected to the growth of control island 144 is the institute in basal layer 112 and template layer 140
The composition (type) of the material used.For example, the material of lattice parameter and template layer 140 that can be based on the material of contact layer 112
The lattice parameter of material selects material.In general, the growth part of island 144 depend on basal layer 112 and template layer 140 it
Between lattice mismatch.For example, in Stanski-Krastanov techniques, the larger mismatch between lattice parameter leads to wet layer 142
Smaller critical thickness, at critical thickness, island growth takes place.It can select the crystalline substance of the material of basal layer 112
The lattice parameter of the material of lattice parameter and template layer 140, to provide the desired growth pattern or feature of island 144, such as
The form of island, island start the point etc. of growth after wet layer deposition.In some example embodiments, basal layer
The lattice mismatch in the range of about 3% to about 20% can be used between 112 material and the material of template layer 140.One
In a little embodiments, template layer 140 can be the material of the band gap with the material bigger than basal layer 112.
Island 144 can be controlled to have specific or common physical characteristic, such as rule or irregular shape
Shape, size and/or interval.For example, can be by controlling the growth rate of wet layer and/or island, control critical thickness, using
Textured or figuratum basal layer 112 etc. controls the geometry and size of island.
In addition, some or all of the physical characteristic (for example, size, shape and/or interval) of island 144 can have
Variation or the scrambling for having specific degrees, with the island at interval that provide different, non-uniform shape and non-uniform
144.Compared with uniform texture, the texture usually enhancing of this variation and randomization dissipates the light received by template layer at random
The ability being mapped in absorbed layer 108.
Because the texturizing surfaces including template layer 140 are formed as the scattering layer of non-interactive, and utilize and use island
The shape of deposition process forming is grown, the scattering layer of the non-interactive has features not provided in absorbed layer or emission layer；And
And because largely variation, scrambling or randomness are preferred in the formation of island 144, in some implementations
In scheme, the semiconductor of high-quality is not required as the material of template layer 140.Such as with island growth technique
The previously used of Stranski-Krastanov techniques is compared, this can allow some reductions of the cost of material and/or processing,
In Stranski-Krastanov techniques, be arranged accurately size and the island that is accurately spaced device absorption
Growth (for example, for adjusting the transmitting of the wavelength in semiconductor laser) in layer.In addition, in some embodiments, quality compared with
The use of secondary semiconductor can allow the higher growth rate of template layer 140.
Fig. 3 B are the cross-sectional views of photovoltaic device 100', and photovoltaic device 100' includes being suitable for some implementations disclosed herein
The deposit of the template layer 150 of scheme, wherein island are formed using different island growth techniques.In figure 3b,
Volmer-Weber growth techniques have replaced the Stranski-Krastanov techniques in the example for Fig. 3 A to be used for island
Object is grown.
Template layer 150 includes island 152, by the way that template layer material is deposited on (or the institute as above of basal layer 112
Other layers in the embodiment without basal layer 112 for stating) on formed.It is different from the template layer 140 of Fig. 3 A, example
Template layer 150 is not included in the wet layer deposited before island is formed.Island 152 is due on the surface of basal layer 112
The atom of atom and island material has than it stronger interaction with the atom on the surface of basal layer and is formed.This causes
The cluster of material or island 152 is formed as island material deposits.Therefore, some or all islands 152 can be direct
It is formed on the surface of basal layer 112 and/or some or all islands 152 can have in 112 surface of basal layer and island
The layer of the island material formed between object 152.Compared with Stranski-Krastanov described above is grown, Volmer-
The growth of Weber islands is usually happened between template layer and basal layer at higher lattice mismatch and in the relatively low of template layer
On thickness.For example, in some embodiments, the growth of Volmer-Weber islands can be happened at about 5 angstroms of template layer with
Under thickness at.
Template layer 150 includes semi-conducting material, and is the material for the basal layer 112 being deposited thereon with template layer 150
Different materials.For example, in some embodiments, template layer 150 may include phosphorus, gallium, aluminium, indium, arsenic, antimony, nitrogen, its derivative
Object and/or a combination thereof.In some embodiments, basal layer 112 and template layer 150 can be described above for template layer
The combination of the material of 140 material or derivative.Some embodiments can use the material being doped to be used for template layer 150.
Similarly, as explained above with respect to the embodiment of Fig. 3 A, the growth of island 152 can be by adjusting heavy
The different parameters of one or more of product process control, including parameters described above.
In another embodiment, template layer has the inconsistency of composition, but may or may not have significantly
Thickness inconsistency.Fig. 3 C are the cross-sectional views for the exemplary photovoltaic device 100 " for showing this embodiment.Template layer 155
It is formed including two or more material, the first material is shown as unshadowed area 156 and 157, and second of material
Material is shown as shadow region 158.Fig. 3 C are intended to only show an example, and are not intended to be limited to the scope of the present invention.Particularly,
It is more than two kinds of chemical compositions it is possible that existing, 156 and 157 there is identical or different material to form, and 156 be connection
Layer rather than the island of disconnection as shown in the figure.
So, the embodiment with Fig. 3 C of the inconsistency of composition is easily affected by etching, which can be with not
Same rate etching layer 156 and 158.In one embodiment, when layer is exposed to etchant or etching process, layer 158 compares
Layer 156 is etched more quickly so that after the etching, the structure of reservation is similar to the structure of Fig. 3 B.Then, from Fig. 3 C's
Layer 156 becomes the island nitride layer 152 for being equal to Fig. 3 B.
In some example embodiments, template layer 155 may include two kinds of one or more semiconductors or be more than two
The different composition of kind, such as aluminum gallium arsenide (AlGaAs) (for example, there is different amounts of Al and Ga contents) or AlGaInP
(AlGaInP) (for example, there is different amounts of Al, Ga and/or In content) or other materials.
In order to further change island 152 and provide more coarse texture, etching can be after island growth
It is carried out as shown in the optional embodiment 100 " ' in Fig. 3 D.Island is grown and the parameter of etching the two can control
The form and size of texture, to maximize benefit of the texture to device performance.The variation of island 152 may include changing line
The physical size on physics and chemistry surface, wherein the physical size changed includes the change of one or more of texturizing surfaces island
Shape or texturizing surfaces in multiple islands between change distance.In various embodiments, etching can be
It is one or more in chemical etching, laser-induced thermal etching, plasma etching or ion(ic) etching or similar etching.
In another embodiment, after removing layer 158, layer 156 provides island template for further etching.
In another embodiment, layer 140 is partially etched, to generate island template (Fig. 3 E).After the etching,
The remainder of layer 140 is marked as 146.It is further etched in layer 112 and generates texture (Fig. 3 F).Fig. 3 F are shown in which pair
The etchant that layer 112 is etched has layer 146 a kind of embodiment of insignificant influence.In yet another embodiment,
The etchant that layer 112 is etched simultaneously effective etching layer 146 (Fig. 3 G).It is also possible that layer 112 etching it
Layer 146 no longer exists afterwards.
In another embodiment (Fig. 3 H), etching is not limited to layer 112 and the layer those of above layer 112, but also expands
Open up layer 110.No matter layer 146 or layer 152 or layer 156 are island nitride layer, this can be applicable in.
In Fig. 4, the photoelectric device 100 of Fig. 3 B by optional semiconductor contact layer 160 further by being deposited on template
It is deposited on contact layer (if present) or is deposited on template layer on layer 140,150 or 155, next by dielectric layer 162
140, it is formed on 150 or 155 (if if contact layer 160 is not present).Template is shown in the exemplifying drawings being described below
Layer 140 template layer 150 or 155 can wherein be used instead of template layer 140 as required.Those of ordinary skill in the art hold
It changes places, it is realized that the photoelectric device 100 ' of Fig. 3 B can further be formed in the same fashion and it will be the present invention's
In spirit and scope.In addition, the description below device 100 is equally applicable to the device 100 " -100 of Fig. 3 A-3H " " " '.Half
Conductor contact layer 160 can be deposited in some embodiments with for example on template layer provide calotte (cap) and with
Other layers are allowed to be more easily deposited on template layer, and/or to be provided preferably for the electric charge carrier movement in device 100
Ohmic contact.In some example embodiments, contact layer 160 may include semiconductor (such as GaAs (GaAs) (for example,
Due to it can be it is less opaque and have smaller thickness), aluminum gallium arsenide (AlGaAs) (for example, because it can be more
It is transparent and there is larger thickness)) or other materials, and can be p in some embodiments-Doping, have
Thickness in the range of about 5nm to about 500nm.
Dielectric layer 162 can be deposited over contact layer 160 and/or template layer 140,150 or 155 in some embodiments
On, and can promote to hit or travel across the reflection or scattering of the light of template layer 140,150 or 155.In some instances,
Dielectric layer 162 may include insulating materials (such as the titanium dioxide for example with the dielectric constant between template semi-conducting material and 1
Silicon (SiO2)).In some embodiments, dielectric layer 162 can be with the light being intended to by texturing layer scattering four/
The thickness of one wavelength (or multiple quarter-waves), and allow the reflection than metal layer (described below) bigger is used only
Ability.In some embodiments, dielectric layer can have the refractive index n lower than template layer 140,150 or 155.
Therefore, island 144 or 152 can be on being deposited on template layer layer in form recess portion so that back reflect
In device embodiment, the light that the material of template layer 140,150 or 155 is advanced is passed through to hit the surface of recess portion and the table from recess portion
Face is reflect off (for example, the surface scattering for passing through recess portion).Some examples are illustrated in greater detail about Figure 10.
In some other implementations, different materials can substitute dielectric layer 162 be deposited on semiconductor layer 160 or
On template layer 140,150 or 155 (if contact layer 160 is not present).For example, in some embodiments, electrically conducting transparent
Oxide (TCO) layer can be deposited to provide the albedo of raising similar with dielectric layer, and also for template layer and be set
The electric charge carrier set between the conductive metal layer on tco layer provides conductive path.In these embodiments, as figure
Hole may not necessarily be formed in tco layer described in dielectric layer 162 in 5.In some embodiments, high resistivity is saturating
Bright (HRT) layer can also be arranged in tco layer and semiconductor layer (such as template layer 140/150/155, emission layer 110 or absorbed layer
108) between.The HRT layers of shunting that can reduce pin hole (pin hole) of the electric charge carrier in semi-conducting material.
Fig. 5 is shown after hole has been formed in dielectric layer 162 to allow the device of the conductive contact across dielectric layer 162
Part 100.In the embodiment with semiconductor contact layer 160, such as example embodiment shown in Fig. 5, from dielectric layer
162 surface to semiconductor contact layer 160 passes through dielectric layer 162 to form hole 164.In its without semiconductor contact layer 160
In his embodiment, hole 164 can be formed from the surface of dielectric layer to template layer 140,150 or 155.
In some embodiments, it is etched by using etch process to form hole 164.Etch process can use
Any available suitable technology carries out.
In some example embodiments, the certain patterns in the hole 164 in dielectric layer 162 can pass through mask (such as light
Photoresist/etching mask) it provides.Fig. 6 A show the vertical view of the mask pattern 165 of the providing holes 164 in dielectric layer 162
One example, mesoporous are the circular holes 166 (being approximate circle in the vertical view of Fig. 6 A) for having near circular cross section.Figure
6B shows that another example of the vertical view of the mask pattern 167 of the providing holes 164 in dielectric layer 162, mesoporous are line styles
Groove.As shown, one or more grooves 168 can intersect with other one or more grooves 169.As shown,
Groove can be positioned to it is approximatively parallel to each other and/or vertical, or in other embodiments can with various other angles into
Row placement.Non-linearity or irregular groove can be used in other embodiments.
In the figure 7, photoelectric device 100 has been further advanced by is deposited on dielectric layer 162 by reflectivity back-metal layer 170
Upper, setting textures an example of layer 180 to be formed.Metal layer 170 includes the metal of effective reflected light.For example, at some
In embodiment, metal layer 170 may include gold, silver, copper or other reflective metals, they derivative, and/or they
Combination.The deposition of metal layer 170 provides the approximate flat surface opposite with template layer 140,150 or 155.In some embodiment party
In formula, layer 140,150 or 155 is etched before subsequent procedure of processing.In some embodiments, metal layer
170 can be with the average thickness in the range of about 70nm to about 10 μm.The material of metal layer 170 is also deposited in hole 164,
So that conductive contact is formed between metal layer 170 and semiconductor contact layer 160 or is formed in metal layer 170 and template layer
140, (there is no if contact layer 160) between 150 or 155.In some other implementations, metal layer 170 can be sunk
Product is on template layer 140,150 or 155, without making dielectric layer 162 and/or semiconductor contact layer 160 be deposited on metal layer and mould
Between plate layer.
In fig. 8, after some layers shown in the preceding step during stripping technology has eliminated Fig. 2-7, photovoltaic electric
Pond 120 is shown as being reversed direction.When epitaxial layer has been formed as PV devices 100 as shown in Figure 7, photovoltaic device
Some layers (such as front contact layer 105, Window layer 106, absorbed layer 108, emission layer 110 and veining layer 180) in part 100
It can be detached with substrate 101 and any buffer layer 102 during ELO techniques.
In one example, photovoltaic device 100 can be exposed to etching solution to etch sacrificial layer 104 and in extension
Battery 120 is set to be detached with growth wafer 101 during stripping (ELO) technique.Fig. 8 shows the battery in its obtained orientation
120, the front of wherein battery 120 is oriented at the top of battery, and at the top of battery, light hits and enters battery.Therefore, line
Physics and chemistry layer 180 is more anti-far from back is served as than the p-n junction by absorbed layer and emission layer formation in the front away from battery 120
Emitter.Once by detaching, then battery 120 can be processed further to form a variety of photovoltaic devices (including photovoltaic cell
And module).For example, hard contact 190 can be deposited on front contact layer 105.
Fig. 9 shows that the cross-sectional view of the selectable embodiment 120 ' of photovoltaic cell 120, mesoporous are not formed in Jie
In electric layer 162, and conductive contact is deposited over below dielectric layer 162.In this example, during layer deposits, some are conductive
Contact 194 can be deposited on semiconductor contact layer 160 ', or (if there is no connecing on template layer 140 '/150 '/155 '
If contact layer 160 ').In some embodiments, layer 140 ', 150 ' or 155 ' carries out before subsequent procedure of processing
Etching.Dielectric layer 162 ' is deposited on contact 194 and semiconductor contact layer 160 '.Metal contact layer 170 ' is deposited over dielectric
On layer 162 '.Then, device is flipped to direction shown in Fig. 9 after ELO or process similarity.
Conductive contact 194 is shown with cross section, and the plane that can be extended in the plane of Fig. 9 or from Fig. 9 extends
Out to one or more position (not shown) for passing through the arrival metal contact layer 170 ' of dielectric layer 162 ' by route.For example,
In some embodiments, contact 194 can be configured to the groove 168 and 169 phases with mask pattern 167 shown in Fig. 6 B
Seemingly, wherein contact 194 extends on the region of battery 120 ' and is connected to one or more connecting nodes (for example, phase
It is similar to node 196 shown in Fig. 6 B), one or more connecting node is extended through the covering part of dielectric layer 162 '
To metal contact layer 170 ', or extend to the external position of battery 120 '.There is provided each embodiment of hard contact 194 can keep away
Exempt to etch the hole in dielectric layer, procedure of processing is saved in forming battery 120 '.
Figure 10 shows the figure of the part 200 of the photovoltaic cell 120 of pictorial image 8, and wherein light is anti-by serving as back
The veining layer 180 of layer is penetrated to receive.Active layer or area 202 are arranged on texture reflecting layer 180.For example, active layer 202 can
To be solar cell active region, such as emission layer 110 and/or absorbed layer 108.Other one or more layers 204 are at some
It can also be placed in embodiment between active layer 202 and veining layer 180.
Light 206 has been marched in photovoltaic cell 120 and has been absorbed by upper layer.The light 206 from active layer 202 occur and
Hit the front surface 210 of veining layer 180.Light 206 passes through the transparent material of template layer 140,150 or 155.In some embodiment party
In formula, layer 140,150 or 155 is etched before subsequent procedure of processing.Some of photon 206 can hit dielectric
Layer 162 surface and reflected from the layer.Other photons 206 can pass through dielectric layer 162 and can hit back-metal
Layer 170 surface and reflected from the layer.Photon through reflection orient as indicated by arrow 212 pass back through template layer 140,
150 or 155 and subsequently into active layer 202, wherein they " can bounce " around and can pass through absorbed layer 108
It is captured with emission layer 110, and further generates electric current in the battery.
The island 144 (or island 156 of the island 152 of template layer 150 or template layer 155) of template layer 140 exists
Recess portion 172 is created in dielectric layer 162 and back-metal layer 170.This create the random of dielectric layer 162 and back-metal layer 170
Changing, roughening and angular front surface.The diffusion of veining layer 180 or the unabsorbed light for being scattered through active layer 202
Son.The texture of veining layer 180 can provide new angle for incident photon, some of these incident photons can redirect
Pass back through template layer 140,150 or 155 and towards the inside of photovoltaic cell.Although some light can be absorbed by template layer,
But because photon is scattered and redirected in inside, many light are re-directed to active layer 202.Therefore, texture
Therefore changing the different angles on the surface of layer 180 and its recess portion 172 effectively causes photon 206 to be reflected back work with random angles
To allow larger amount of photon by active layer recapture and be converted into electric energy in property layer 202, to enhance battery 120
Light acquisition performance and increase efficiency.
Figure 11 is suitable for providing another implementation of the photovoltaic device 300 of veining layer in the front side of photoelectric device 300
The cross-sectional view of mode.It is captured instead of above-mentioned back side light or in addition to this, veining layer can be arranged for photovoltaic cell
Light capture at front side.This allows the light for hitting the front side of photovoltaic device by the grain surface created by veining layer in device
It is middle to be scattered, increase the light capture in device.
Photovoltaic device 300 includes that ELO releasing layers by being disposed therein or sacrificial layer 304 are coupled with growth wafer 301
Battery 320.In some embodiments, one or more buffer layers 302 can be formed on growth wafer 301 to open
Beginning forms photovoltaic device 300.The layer of photovoltaic cell 320 can be deposited on sacrificial layer 304, and the sacrificial layer 304 is in some realities
Apply in mode may include back semiconductor contact layer 312, the emission layer 310 on back contact layer 312, on emission layer 310
It absorbed layer 308 (or emission layer 310 on absorbed layer 308), the front window layer on absorbed layer 308 or passivation layer 306 and is used for
Basal layer 305 texturing, being arranged in Window layer 306.
In some embodiments, back contact layer 312 may include nonmetallic group iii-v compound semiconductor,
Such as GaAs.
Basal layer 305 for veining is similar to the basal layer 112 described above with reference to Fig. 1.For example, basal layer 305
It provides thereon in order to texture the first layer that purpose deposits template layer, and for example by with the composition different from template layer
(for example, different lattice parameters), can contribute to island and is formed.
In other embodiments, device 300 is not grown in sacrificial layer structure as shown or ELO releasing layer structures.
For example, in other embodiments, device 300 is not removed program including ELO and is grown in no sacrificial layer 104 or buffer layer
On 302 substrate.
Figure 12 is the cross-sectional view of photovoltaic device 300, and photovoltaic device 300 includes according to the texture for being used as front side light trapping layer
Change the deposit of the template layer 340 on the basal layer 305 of the embodiment of layer.Template layer 340 can use island to grow work
Skill creates and provides the island 344 of one or more surface texturizings for making template layer to cause in the devices
Light reflection and scattering increase light capture.Some embodiments may include wetting layer 342, be similar to above-mentioned wetting layer.
In other embodiments, there is no islands to grow in layer 340, and on the contrary, the template layer has component inhomogeneities
And subsequent etch process removes certain materials than removing other materials faster.This is also similar to above for Fig. 3 C descriptions
Situation.In some embodiments, layer 340 is etched before subsequent procedure of processing.
In fig. 13, photoelectric device 300 has been further advanced by layer being deposited on and formed on template layer 340.At some
In embodiment, in example as shown in Figure 13, optional semiconductor contact layer 360 is deposited on template layer 340.
Anti-reflective coating (ARC) 362 can be deposited on semiconductor contact layer (if present) or in template layer
On 340 (if there is no if contact layer 360).ARC layer 362 includes dielectric material, and the dielectric material allows light to pass through, simultaneously
Prevent light from the surface reflection of ARC layer 362.In some embodiments, ARC layer 362 may include multiple layers.
In ELO embodiments, ELO techniques can be used battery 320 (including layer 340,360 and 362) from ELO layers
301, it 302 and 304 removes.After the removing, battery 320 keeps its direction shown in Figure 11-13 and about above-mentioned
It is not overturn on the direction of back side reflector embodiment.In other embodiments, it is used for battery 320 without ELO techniques.
Layer 340,360 and 362 provides front side light capture veining layer 380.The forward position of veining layer 380 allows it
It receives the light for hitting device 300 and at different angles by the lower layer of light scattering to device 300, this is attributed to template layer
The veining of island in 340, randomization surface.This has removed light capture, because photon bounces in lower layer, allows
More photons are absorbed to generate electric current.
In the other embodiment of device 100 and 300, other layer arrangements, doping arrangement, layer thickness etc. can be used.
For example, emission layer can be deposited on absorbed layer in some embodiments.
Each embodiment of photoelectric device and method for providing such devices described herein can provide texture
Change layer, veining layer includes the island for being created for that veining layer is made to allow to increase light capture.Disclosed each embodiment
The advantages of can also providing better than previous light trapping layer formation technology, including larger flexibility, the cost of attenuating and increase
Layer growth rate, save manufacture device in time and expense.
Although describing the present invention according to shown each embodiment, those of ordinary skill in the art will be easy
, it is realized that each embodiment may exist variation and these variations will within the spirit and scope of the present invention.Therefore, ability
Domain those of ordinary skill can make many modifications, without departing from spirit and scope of the appended claims.
Claims (22)
1. a kind of photoelectric device at least one texturizing surfaces, at least one texturizing surfaces include by executing
The method of following steps is made：
The semiconductor layer of photoelectric device described in epitaxial growth in growth substrates；
The semiconductor layer is exposed to etch process to form at least one texturizing surfaces on the semiconductor layer；
With
The photoelectric device is removed from the growth substrates.
2. photoelectric device according to claim 1, wherein it includes executing to remove the photoelectric device from the growth substrates
Extension removes (ELO) technique.
3. photoelectric device according to claim 1, wherein the etch process is lost by the chemistry based on liquid or solution
Agent is carved to complete.
4. photoelectric device according to claim 1, wherein etch process pass through gas etch, laser-induced thermal etching, plasma
One or more of etching or ion(ic) etching are completed.
5. photoelectric device according to claim 1, wherein at least one texturizing surfaces are configured as that light is caused to dissipate
It penetrates.
6. photoelectric device according to claim 5, wherein at least one texturizing surfaces be configured as making photon with
Random angles scatter.
7. photoelectric device according to claim 1, wherein the semiconductor layer includes in gallium, aluminium, indium, phosphorus, nitrogen or arsenic
It is at least one or more of.
8. photoelectric device according to claim 1 further includes in being deposited below at least one texturizing surfaces
One or more：
Dielectric layer,
Transparent conductive oxide (TCO) layer,
Anti-reflective coating, or
Reflective metallic.
9. photoelectric device according to claim 1, wherein at least one texturizing surfaces are than the photoelectric device
P-n junction further from the photoelectric device front side position back reflecting layer a part.
10. photoelectric device according to claim 1, wherein at least one texturizing surfaces are than the photoelectric device
P-n junction closer to the photoelectric device front side position front window layer a part.
11. photoelectric device according to claim 1, wherein the photoelectric device is a part for solar cell or shines
A part for diode.
12. a kind of method for providing at least one veining layer in the opto-electronic device, the method includes：
The semiconductor layer of photoelectric device described in epitaxial growth in growth substrates；
The semiconductor layer is exposed to etch process to form at least one texturizing surfaces on the semiconductor layer；
With
The photoelectric device is removed from the growth substrates.
13. according to the method for claim 12, wherein it includes that execution is outer to remove the photoelectric device from the growth substrates
Prolong stripping (ELO) technique.
14. according to the method for claim 12, wherein the etch process passes through the chemical etching based on liquid or solution
Agent is completed.
15. method as claimed in claim 12, wherein etch process pass through gas etch, laser-induced thermal etching, plasma etching
Or one or more of ion(ic) etching is completed.
16. according to the method for claim 12, wherein at least one texturizing surfaces are configured as causing light scattering.
17. according to the method for claim 16, wherein at least one texturizing surfaces be configured such that photon with
Random angles scatter.
18. according to the method for claim 12, wherein the semiconductor layer include in gallium, aluminium, indium, phosphorus, nitrogen or arsenic extremely
It is few one or more.
19. further including according to the method for claim 12, in being deposited below at least one texturizing surfaces
It is one or more：
Dielectric layer,
Transparent conductive oxide (TCO) layer,
Anti-reflective coating, or
Reflective metallic.
20. according to the method for claim 12, wherein at least one texturizing surfaces are than the photoelectric device
The part in the back reflecting layer that p-n junction is positioned further from the front side of the photoelectric device.
21. according to the method for claim 12, wherein at least one texturizing surfaces are than the photoelectric device
A part for the front window layer that p-n junction is positioned closer to the front side of the photoelectric device.
22. according to the method for claim 12, wherein the photoelectric device is a part or luminous two for solar cell
A part for pole pipe.
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| US14/452,393 | 2014-08-05 | ||
| CN201510475349.5A CN105336797B (en) | 2014-08-05 | 2015-08-05 | Thin film semiconductor's photoelectric device with veining front surface and/or back surface |
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