CN108565221A - A kind of ultralow interfacial state interfacial structure and preparation method thereof of matching (Al, In) GaN material - Google Patents
A kind of ultralow interfacial state interfacial structure and preparation method thereof of matching (Al, In) GaN material Download PDFInfo
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- 229910052782 aluminium Inorganic materials 0.000 title claims abstract description 45
- 229910052738 indium Inorganic materials 0.000 title claims abstract description 45
- 239000000463 material Substances 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910002790 Si2N2O Inorganic materials 0.000 claims abstract description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 48
- 229910052710 silicon Inorganic materials 0.000 claims description 48
- 239000010703 silicon Substances 0.000 claims description 48
- 229910052757 nitrogen Inorganic materials 0.000 claims description 28
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 25
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 23
- 229910052760 oxygen Inorganic materials 0.000 claims description 23
- 239000001301 oxygen Substances 0.000 claims description 23
- 238000000137 annealing Methods 0.000 claims description 19
- 239000012495 reaction gas Substances 0.000 claims description 18
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 claims description 12
- 229910021529 ammonia Inorganic materials 0.000 claims description 12
- 239000001257 hydrogen Substances 0.000 claims description 12
- 229910052739 hydrogen Inorganic materials 0.000 claims description 12
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 12
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 11
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 10
- 238000007740 vapor deposition Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 9
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 8
- 229910000077 silane Inorganic materials 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 238000011065 in-situ storage Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 6
- 239000000460 chlorine Substances 0.000 claims description 6
- 229910052801 chlorine Inorganic materials 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 4
- 238000010301 surface-oxidation reaction Methods 0.000 claims description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 3
- 239000000908 ammonium hydroxide Substances 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 230000000737 periodic effect Effects 0.000 claims description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 229910001882 dioxygen Inorganic materials 0.000 claims description 2
- 238000010129 solution processing Methods 0.000 claims description 2
- 238000009832 plasma treatment Methods 0.000 claims 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- 238000010276 construction Methods 0.000 abstract description 2
- 229910002601 GaN Inorganic materials 0.000 description 35
- GQPLMRYTRLFLPF-UHFFFAOYSA-N nitrous oxide Inorganic materials [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 13
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 238000003917 TEM image Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910020782 SixNyO Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 235000013842 nitrous oxide Nutrition 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000053 physical method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 229910017109 AlON Inorganic materials 0.000 description 1
- WYQGNUUOBJVAKM-UHFFFAOYSA-N N.Cl[SiH2]Cl Chemical compound N.Cl[SiH2]Cl WYQGNUUOBJVAKM-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 125000003963 dichloro group Chemical group Cl* 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910002059 quaternary alloy Inorganic materials 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/38—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- Computer Hardware Design (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Crystallography & Structural Chemistry (AREA)
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- Organic Chemistry (AREA)
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Abstract
A kind of ultralow interfacial state interfacial structure and preparation method thereof of matching (Al, In) GaN material, the ultralow interfacial state interfacial structure include:(Al, In) GaN substrate;And it is formed in the Si on described (Al, In) GaN base plate material2N2O layers, wherein the Si2N2O layers are monocrystalline or polycrystalline type.New construction proposed by the present invention and preparation method thereof can obtain and (Al; In) the interface of GaN material lattice constant matched; and realize ultralow interfacial state; the interfacial state that can effectively solve the problems, such as long-standing problem group III-nitride (III N) system, to push the scale and functionization of III N electronic devices.
Description
Technical field
The invention belongs to technical field of semiconductor device, and in particular to the passivation in the preparation of (Al, In) GaN base device and grid
Media technology more particularly to a kind of ultralow interfacial state interfacial structure and preparation method thereof of matching (Al, In) GaN material.
Background technology
Third generation semiconductor GaN material has been supplied in microwave and millimeter wave device, efficient electrical power electronic device etc. at present,
But reliability is always to restrict the bottleneck of its scale functionization, and one of key problem is that gallium nitride interfacial state problem does not solve thoroughly
Certainly.(Al, In) GaN material is the ternary developed based on GaN material or quaternary alloy system, is based on the half of (Al, In) GaN material
Conductor device generally use SiN, SiO2、SiON、Al2O3、AlON、AlN、HfO2Etc. media implementations passivation layer and gate insulation layer, but
Since the lattice mismatch of above-mentioned medium and (Al, In) GaN material is larger, it is difficult to obtain the very matched interface of lattice constant, lead
Cause medium and the interfacial state of (Al, In) GaN material high.Therefore, it finds and prepares normal with (Al, In) GaN material lattice
The medium of number matched becomes difficult point and the commanding elevation in group III-nitride field.
Invention content
(1) technical problems to be solved
In view of this, it is a primary object of the present invention to significantly reduce the crystalline substance between processing medium and (Al, In) GaN material
Lattice mismatch ratio effectively inhibits the interfacial state problem to remain high between the two.
(2) technical solution
In order to achieve the above objectives, the present invention propose it is a kind of matching (Al, In) GaN material ultralow interfacial state interfacial structure and
Preparation method.
On the one hand, the ultralow interfacial state interfacial structure of matching (Al, In) GaN material proposed by the present invention includes:
(Al, In) GaN substrate;And
The Si being formed in described (Al, In) GaN substrate2N2O layers,
Wherein, the Si2N2O layers are monocrystalline or polycrystalline type.
Preferably, described (Al, the In) GaN substrate is mono-crystalline type.
Preferably, the < 11-20 > crystal orientation of described (Al, the In) GaN substrate is parallel to the Si2N2O layers of 001 > of < are brilliant
To the < 1-100 > crystal orientation of (Al, the In) GaN substrate is parallel to the Si2N2O layers of 010 > crystal orientation of <.
On the other hand, the preparation method of the ultralow interfacial state interfacial structure of matching (Al, In) GaN material proposed by the present invention
Including:
(a) surface oxidation treatment is carried out to (Al, In) GaN substrate, forms oxide layer;
(b) (Al, In) GaN substrate by described in is put into vapor deposition apparatus, and silicon source and nitrogen source reaction gas are passed through in high temperature
Body forms Si2N2O layers;
(c) stop being passed through the reaction gas, anneal at high temperature.
Preferably, the oxidation processes in step (a) be the concentrated sulfuric acid and hydrogen peroxide mixed solution handle or oxygen etc. from
Daughter is handled.
Preferably, oxidated layer thickness described in step (a) is no more than 2nm.
Preferably, silicon source described in step (b) is in silane, three hydrogen silicon of a chlorine, dichlorosilane, one hydrogen silicon of trichlorine
One or more, nitrogen source is one or more in ammonia, hydrazine;The silicon source and the nitrogen source are passed through or alternately lead to simultaneously
Enter.
Preferably, high temperature described in step (b) is not less than 700 DEG C.
Preferably, annealing temperature is not less than 700 DEG C in step (c), and is not higher than 900 DEG C, and annealing time is not less than
20min。
Preferably, being annealed into step (c) anneals or anneals in high-temperature service in situ.
Another preparation method of the ultralow interfacial state interfacial structure proposed by the present invention includes:
(a) oxide layer of (Al, In) GaN base plate surface is removed;
(b) (Al, In) GaN substrate by described in is put into vapor deposition apparatus, and it is anti-to be passed through silicon source, nitrogen source and oxygen source in high temperature
Gas is answered, Si is formed2N2O layers;
(c) stop being passed through the reaction gas, anneal at high temperature.
Preferably, in step (a) oxide layer is removed using hydrochloric acid, ammonium hydroxide or potassium hydroxide.
Preferably, step (b), which is included under chemical vapor depsotition equipment high temperature, is passed through nitrogen source, silicon source and oxygen source reaction gas
Body, the silicon source, nitrogen source and oxygen source are passed through or are alternately passed through simultaneously, it is preferable that the high temperature is not less than 700 DEG C.
Preferably, step (b) is included in periodic sequence in atomic layer deposition apparatus and is passed through oxygen source, silicon source, nitrogen source and silicon
Source reaction gas, the high temperature are not less than 300 DEG C.
Preferably, silicon source described in step (b) is in silane, three hydrogen silicon of a chlorine, dichlorosilane, one hydrogen silicon of trichlorine
One or more, nitrogen source is one or more in ammonia, hydrazine, the one kind or more of oxygen source in oxygen or nitrogen oxides
Kind.
Preferably, annealing temperature is not less than 700 DEG C in step (c), and is not higher than 900 DEG C, and annealing time is not less than
20min。
Preferably, being annealed into step (c) anneals or anneals in high-temperature service in situ.
(3) advantageous effects
New construction proposed by the present invention and preparation method thereof can obtain and (Al, In) GaN material lattice constant height
The interface matched, and realize ultralow interfacial state, it can effectively solve the interfacial state of long-standing problem group III-nitride (III-N) system
Problem, to push the scale and functionization of III-N electronic devices.
Description of the drawings
Fig. 1 is the schematic diagram of ultralow interfacial state interfacial structure in the embodiment of the present invention;
Fig. 2 is the ultralow interfacial state interfacial structure preparation flow figure in one embodiment of the invention;
Fig. 3 is the ultralow interfacial state interfacial structure preparation flow figure in another embodiment of the present invention;
Fig. 4 is the ultralow interfacial state interfacial structure TEM image in the embodiment of the present invention;
Fig. 5 is the interfacial structure TEM image in a comparative example of the invention;
Fig. 6 is the interfacial structure TEM image in another comparative example of the present invention;
Fig. 7 is the threshold drift pair of ultralow the interfacial state interfacial structure and existing interfacial structure in the embodiment of the present invention
Than;
Fig. 8 is the interface state density pair of ultralow the interfacial state interfacial structure and existing interfacial structure in the embodiment of the present invention
Than.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in further detail.
Interfacial structure proposed by the present invention is the base combed comprehensively in the lattice constant to existing all kinds of medium systems
It is proposed on plinth, which has the lattice mismatch rate far below world level, and can successfully be realized by innovative technology ultralow
It is prepared by the interfacial structure of interfacial state.
As shown in Figure 1, the ultralow interfacial state interfacial structure in the present invention includes (Al, In) GaN substrate, and it is formed in
Si in (Al, In) GaN substrate2N2O layers.(Al, In) GaN substrate is mono-crystalline type, wherein ranging from the 0 of Ga elemental constituents x is arrived
1, corresponding Al and/or In elemental constituents are 1-x.Si2N2O layers can be monocrystalline or polycrystalline type.
Wherein, Si2N2001 > of < of O are oriented parallel to the directions < 11-20 > of (Al, In) GaN.Si2N2O is in < 001
The repetition interval in the directions > isAnd repetition intervals of (Al, the In) GaN in the directions < 11-20 > isThe mismatch ratio of (by taking GaN lattices as an example), the two is only 1.45%.
Si2N2010 > of < of O are oriented parallel to the directions < 1-100 > of (Al, In) GaN.Si2N2O is in 010 directions > <
Repetition interval beRepetition intervals of (Al, the In) GaN in < 1-100 > be(it is with GaN lattices
Example), mismatch ratio is only 0.45%.As it can be seen that Si2N2The lattice matched of O and (Al, In) GaN.
As shown in Fig. 2, the invention also provides a kind of ultralow interfacial state interfacial structures of matching (Al, In) GaN material
Preparation method, including:
(a) surface oxidation treatment is carried out to (Al, In) GaN substrate, forms oxide layer.
Oxidation processes in the step can be at the concentrated sulfuric acid and hydrogen peroxide mixed solution processing or oxygen plasma
Reason, can also be other oxidation processes modes, as long as a thin oxide layer can be formed.Here the thickness one of oxide layer
As must not exceed 2nm, such as can be 0.5nm, 1nm, 1.5nm etc..
(b) (Al, In) GaN substrate by described in is put into vapor deposition apparatus, and silicon source and nitrogen source reaction gas are passed through in high temperature
Body forms Si2N2O layers.
Here silicon source can be selected from one kind in silane, three hydrogen silicon of a chlorine, dichlorosilane, one hydrogen silicon of trichlorine or more
Kind, nitrogen source can be selected from one or more in ammonia, hydrazine.Above-mentioned silicon source and nitrogen source can in any combination, and this is not restricted,
And silicon source and nitrogen source can be passed through or alternately be passed through simultaneously.For example, in one embodiment, chemical vapor deposition can be passed through
Mode form Si2N2O layers.Silane and ammonia are passed through a chemical vapor depsotition equipment simultaneously, in another embodiment, logical first
Enter dichlorosilane gas, be then passed through ammonia again, or pass first into ammonia, is then passed through dichlorosilane gas.
Silicon source and nitrogen source can also be repeatedly alternately passed through in vapor deposition apparatus.
Here high temperature is generally not less than 700 DEG C, such as can be 750 DEG C, 800 DEG C, 850 DEG C etc..
(c) stop being passed through the reaction gas, anneal at high temperature.
In the step, annealing temperature generally be not less than 700 DEG C, also should not be higher than 900 DEG C, such as can be 750 DEG C, 800
DEG C, 850 DEG C etc., annealing time generally be not less than 20min, such as can be 25min, 30min, 35min, 40min, 50min,
60min etc..
When annealing can in vapor deposition apparatus in-situ annealing, can also will (Al, In) GaN substrate take out after it is high one
Annealing in warm equipment (such as high temperature oven, high temperature furnace).
As shown in figure 3, the ultralow interfacial state interfacial structure of the present invention can also be prepared by another preparation method, the system
Preparation Method includes:
(a) oxide layer of (Al, In) GaN base plate surface is removed.
Here oxide layer refers to the native oxide layer of substrate surface, and the method for removing removing oxide layer can be chemical method,
It may be physical method.For example, chemical method can remove substrate surface by, for example, hydrochloric acid, ammonium hydroxide or potassium hydroxide
Oxide layer, physical method can be plasma etching.
(b) (Al, In) GaN substrate by described in is put into vapor deposition apparatus, and it is anti-to be passed through silicon source, nitrogen source and oxygen source in high temperature
Gas is answered, Si is formed2N2O layers;
Here silicon source can be selected from one kind in silane, three hydrogen silicon of a chlorine, dichlorosilane, one hydrogen silicon of trichlorine or more
Kind, nitrogen source can be selected from one or more in ammonia, hydrazine, and oxygen source can be selected from one kind in oxygen or nitrogen oxides or more
Kind.Above-mentioned silicon source and nitrogen source can in any combination, and this is not restricted.
In one embodiment, Si can be formed by way of chemical vapor deposition2N2O layers.Silicon source, nitrogen source and oxygen source
It can be passed through or alternately be passed through in a chemical vapor depsotition equipment simultaneously.For example, in one embodiment, silane, ammonia and oxygen
Gas is passed through a chemical vapor depsotition equipment simultaneously, in another embodiment, is successively passed through dichlorosilane gas, ammonia in order
And oxygen, this is not restricted for the sequencing of silicon source, nitrogen source and oxygen source, and silicon source, nitrogen source and oxygen source can also be with multiple
Alternate mode is passed through in vapor deposition apparatus.
Here high temperature is generally not less than 700 DEG C, such as can be 750 DEG C, 800 DEG C, 850 DEG C etc..
In another embodiment, Si can be formed by way of atomic layer deposition2N2It O layers, at this time can be in an atom
Layer depositing device in periodic sequence be passed through oxygen source, silicon source, nitrogen source and silicon source reaction gas, here can by multiple periods with
Form Si2N2O layers.
Here high temperature is generally not less than 300 DEG C, such as can be 350 DEG C, 400 DEG C, 450 DEG C etc..
(c) stop being passed through the reaction gas, anneal at high temperature.
In the step, annealing temperature generally be not less than 700 DEG C, also should not be higher than 900 DEG C, such as can be 750 DEG C, 800
DEG C, 850 DEG C etc., annealing time generally be not less than 20min, such as can be 25min, 30min, 35min, 40min, 50min,
60min etc..
When annealing can in vapor deposition apparatus in-situ annealing, can also will (Al, In) GaN substrate take out after it is high one
Annealing in warm equipment (such as high temperature oven, high temperature furnace).
The present invention is explained in detail by taking GaN substrate as an example below, it should be understood that the following examples are not pair
The present invention's further limits, and the present invention is not limited in GaN substrate, utilizes AlGaN substrates, InGaN bases based on GaN material
Plate, AlInGaN substrates can reach identical technique effect.
Embodiment 1
Step a:GaN base plate material passes through the surface oxidation treatment of the concentrated sulfuric acid and hydrogen peroxide, and it is 1.5nm's to form a thickness
Oxide layer.
Step b:GaN substrate is put into CVD equipment, temperature is increased to 780 DEG C, while being passed through dichlorosilane and ammonia
Gas forms the Si that a thickness is 3nm2N2O layers (can be monocrystalline or polycrystalline either amorphous or the former mixed structure).
Step c:Turn off reaction gas, in-situ annealing 30 minutes under 800 DEG C of high temperature so that Si2N2O layers basic or complete
Holocrystalline.
Embodiment 2
Step a:GaN substrate material surface native oxide layer is removed using hydrochloric acid.
Step b:GaN substrate is put into CVD equipment, temperature is increased to 780 DEG C, while be passed through dichlorosilane, ammonia,
Laughing gas carries out chemical vapor deposition, forms the Si that a thickness is 10nm2N2O layers (can be monocrystalline or polycrystalline it is either amorphous or
The former mixed structure).
Step c:Turn off reaction gas, in-situ annealing 40 minutes under 800 DEG C of high temperature so that Si2N2O layers basic or complete
Holocrystalline.
Embodiment 3
Step a:GaN substrate material surface native oxide layer is removed using potassium hydroxide solution.
Step b:GaN substrate is put into ALD equipment, temperature is increased to 800 DEG C, and laughing gas, dichloro are passed through with alternating sequence
Dihydro silicon, ammonia dichlorosilane carry out atomic layer deposition, form the Si that a thickness is 20nm2N2O layers.
Step c:Reaction gas is turned off, GaN substrate is taken out, is placed in a high temperature furnace, is annealed 40 points under 820 DEG C of high temperature
Clock so that Si2N2O layers of substantially or completely crystallization.
Comparative example 1
Under the conditions of 600 DEG C, the silicon oxynitride layer of 10nm thickness is grown in GaN base plate surface by conventional method.
Comparative example 2
Under the conditions of 800 DEG C, the silicon oxynitride layer of 10nm thickness is grown in GaN base plate surface by conventional method.
Fig. 4 is the micro-structure diagram of the ultralow interfacial state interfacial structure in embodiment, it can be found that the Si generated2N2O layers
Basic crystallization, and the silicon oxynitride layer obtained in comparative example 1 is amorphous SixNyO (as shown in Figure 5), the silicon in comparative example 2
Oxynitride layer is to include partially-crystallized Si2N2The amorphous Si of OxNyO (as shown in Figure 6).
Amorphous SixNyO layers of mismatch ratio is maximum, and is currently known most advanced horizontal AlN/GaN mismatch ratios on 2.2% left side
It is right.Mismatch ratio of the ultralow interfacial state interfacial structure on the directions < 11-20 > in the embodiment of the present invention is only 1.5% or so,
Mismatch ratio on the directions < 1-100 > is only 0.45% or so, is far below the mismatch ratio of other existing amorphous dielectric layers, also low
In most matched single crystal AlN mismatch ratio at present.
Fig. 7 is the threshold drift pair of ultralow the interfacial state interfacial structure and existing interfacial structure in the embodiment of the present invention
Than wherein left side is SiN in the prior artxThe interfaces /GaN, right side are the Si of the present invention2N2The interfaces O/GaN, it is found that this
The threshold drift of ultralow interfacial state interfacial structure can drop to almost 0V from 0.5V in invention.
It is close to the deep energy level interfacial state of 5 prepared according to the methods of the invention ultralow interfacial state interfacial structures in the present invention
Degree is detected, as shown in Figure 8, it is found that the interface state density of ultralow interfacial state interfacial structure of the invention can be from
Existing 1012Level drops to 1010Magnitude is the best level being currently known.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect
Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the protection of the present invention
Within the scope of.
Claims (10)
1. a kind of ultralow interfacial state interfacial structure of matching (Al, In) GaN material, which is characterized in that including:
(Al, In) GaN substrate;And
The Si being formed in described (Al, In) GaN substrate2N2O layers,
The wherein described Si2N2O layers are monocrystalline or polycrystalline type.
2. ultralow interfacial state interfacial structure according to claim 1, wherein (Al, the In) GaN substrate is monocrystalline class
Type.
3. ultralow interfacial state interfacial structure according to claim 1, wherein (Al, the In) GaN substrate<11-20>
Crystal orientation is parallel to the Si2N2O layers<001>Crystal orientation, (Al, the In) GaN substrate<1-100>Crystal orientation is parallel to described
Si2N2O layers<010>Crystal orientation.
4. a kind of preparation method of the ultralow interfacial state interfacial structure of matching (Al, In) GaN material, which is characterized in that including:
(a) surface oxidation treatment is carried out to (Al, In) GaN substrate, forms oxide layer;
(b) (Al, In) GaN substrate by described in is put into vapor deposition apparatus, is passed through silicon source and nitrogen source reaction gas in high temperature, shape
At Si2N2O layers;
(c) stop being passed through the reaction gas, anneal at high temperature.
5. preparation method according to claim 4, wherein the oxidation processes in step (a) are the concentrated sulfuric acid and dioxygen
Water mixed solution processing or oxygen plasma treatment, it is preferable that the oxidated layer thickness is no more than 2nm.
6. preparation method according to claim 4, wherein silicon source described in step (b) be selected from silane, three hydrogen silicon of a chlorine,
One or more in dichlorosilane, one hydrogen silicon of trichlorine, nitrogen source is one or more in ammonia, hydrazine;The silicon source and
The nitrogen source is passed through or is alternately passed through simultaneously, it is preferable that high temperature described in step (b) is not less than 700 DEG C.
7. a kind of preparation method of the ultralow interfacial state interfacial structure of matching (Al, In) GaN material, which is characterized in that including:
(a) oxide layer of (Al, In) GaN base plate surface is removed;
(b) (Al, In) GaN substrate by described in is put into vapor deposition apparatus, and silicon source, nitrogen source and oxygen source reaction gas are passed through in high temperature
Body forms Si2N2O layers;
(c) stop being passed through the reaction gas, anneal at high temperature.
8. preparation method according to claim 7, wherein remove institute using hydrochloric acid, ammonium hydroxide or potassium hydroxide in step (a)
State oxide layer.
9. preparation method according to claim 7, wherein step (b) is included under chemical vapor depsotition equipment high temperature
It is passed through nitrogen source, silicon source and oxygen source reaction gas, the silicon source, nitrogen source and oxygen source are passed through or are alternately passed through simultaneously, it is preferable that institute
It states high temperature and is not less than 700 DEG C;
Alternatively, step (b), which is included in periodic sequence in atomic layer deposition apparatus, is passed through oxygen source, silicon source, nitrogen source and silicon source reaction
Gas, it is preferable that the high temperature is not less than 300 DEG C;
Preferably, one or more, nitrogen of the silicon source in silane, three hydrogen silicon of a chlorine, dichlorosilane, one hydrogen silicon of trichlorine
Source is one or more in ammonia, hydrazine, and oxygen source is one or more in oxygen or nitrogen oxides.
10. according to claim 4-9 any one of them preparation methods, wherein annealing temperature is not less than 700 DEG C in step (c),
And 900 DEG C are not higher than, annealing time is not less than 20min, it is preferable that is annealed into annealing in situ or in height in step (c)
It anneals in warm equipment.
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