TW503460B - Semiconductor structure including a magnetic tunnel junction and a process for fabricating same - Google Patents

Abstract

High quality epitaxial layers of ferromagnetic materials can be grown overlying large silicon wafers (22) by first growing an accommodating buffer layer (24) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. This technique permits the fabrication of devices (96) employing ferromagnetic materials on a monocrystalline semiconductor substrate. In particular, magnetic tunnel junction devices may be fabricated on silicon in accordance with this technique.

Description

503460 A7 B7 This patent application filed a U.S. patent application on July 24, 200 (). The patent application number is 09/624526. FIELD OF THE INVENTION The present invention is widely related to semiconductor structures and devices and methods of making the same.

The invention relates to a magnetic tunnel junction interface (MTJ) structure and device, and a method of manufacturing an MTJ device on a single crystal semiconductor substrate. ° W BACKGROUND OF THE INVENTION Magnetic tunnel junction (MTJ) devices have several applications in the microelectronics industry. For example, MTJ devices can be used to form magnetic non-volatile memory elements, magnetic field sensors, and the like. MTJ devices usually include two layers of strong magnetic fields separated by a thin insulating layer. The manufacturing method of the MTJ device is usually to form a ferromagnetic and a marginal layer on the gill titanate substrate. Such substrates are quite expensive and usually only obtain relatively small shapes (for example, substrates with a diameter of less than about two inches). The performance of MTJ devices usually increases with increasing crystallinity of the ferromagnetic film. For example, in the case of a single crystalline ferromagnetic material, the amount of change in impedance per total amount of magnetic field applied to the ferromagnetic layer is usually greater than the amount of change in impedance of polycrystalline or non-crystalline forms of the same material. In addition, the sharp interface between the insulating and ferromagnetic layers makes it easy to improve MTJ device performance by reducing device noise. Therefore, a method of forming a single crystal ferromagnetic and insulating material having a distinct interface on a substrate is desired. Compared with the high cost of manufacturing a hybrid device on a gill titanate substrate, if a large-area, high-quality single-crystal ferromagnetic material thin film is obtained at a low cost, it will help to manufacture various semiconductor devices on the thin film at a low cost. In addition, such as -4- this paper size applies Chinese National Standard (CNS) A4 specification (21 × 297 mm) A7 B7 V. Description of the invention (2) The result can achieve high quality on large-volume wafers such as silicon wafers The thin film of a single crystal ferromagnetic material can use the characteristics of dreams and ferromagnetic materials to = the current integrated device structure. Therefore, there is a need for a ferromagnetic structure that can provide a high-quality single crystal synthetic ferromagnetic film that is superior to another single crystal material (such as a semiconductor wafer), and a method for manufacturing such a structure. Specifically, there is a need for an MTJ device that can be epitaxially grown on a silicon substrate, in this way reducing the cost of the MTJ device and manufacturing the monolithic integrated dream-equipped S and circuits. The drawings briefly illustrate the present invention by way of examples and drawings, but the present invention is not limited to these examples and drawings, wherein similar references represent similar elements, and among which: FIGS. 1 to 3 show various examples according to the present invention. Schematic diagram of the device structure of the specific embodiment; a graph showing the relationship between the maximum film thickness available and the lattice mismatch between the main crystal and the growing crystal overlay; Figure 5 shows the fabrication of magnetic Schematic diagram of the cross-section of the junction surface; Figure 6 shows the schematic diagram of the cross-section of a magnetic tunnel junction junction stack on a single crystal semiconductor substrate; Figure 7 shows the schematic diagram of the device of the template layer shown in Figure 6 Figure 8 shows a schematic sectional view of the single-chip integrated device shown in Figure 6 between the magnetic ridge junction surface formed in the single crystal semiconductor substrate and the integrated logic element; and -5- the paper size Shicai S National Standard Flat (CNS) A4 Specifications (2 ^ · X 297 mm)

Other Device Structures of the Lean Grain Specific Embodiments Figs. 9 to I8 show schematic sectional views of various lean structures according to the present invention. Those skilled in the art should appreciate that the elements in the figures are simplified diagrams and do not need to be scaled. For example, if other components are expected, the size of some of the components may be excessively enlarged to facilitate understanding of the embodiment of the present invention. Detailed description of the drawings Fig. 1 shows a schematic sectional view of a part of a microelectronic structure 20 according to a specific embodiment of the present invention. The microelectronic structure 2G includes a single crystal substrate M, a storage buffer layer 24 containing a single crystal material, and a ferromagnetic material layer 26, which is preferably a single crystal. In this context, the term "single crystal" should have its usual meaning in the semiconductor industry. The term "single crystal" shall represent materials that are single crystals or generally single crystals, and shall include materials with a relatively small number of defects (such as dislocations commonly found in substrates of silicon or germanium silicide or mixtures, etc.), as well as the semiconductor industry The epitaxial layer of such materials often found in China. According to a specific embodiment of the present invention, the structure 20 further includes an amorphous intermediate layer 28 between the substrate 22 and the containing buffer layer 24. The structure 20 may further include a template layer 30 between the containing buffer layer 24 and the ferromagnetic material layer 26. As explained in detail below, the template layer helps to start growing a layer of ferromagnetic material on the containment buffer layer. The amorphous intermediate layer helps to slow down the containment buffer layer i 'and thereby assists the growth towards a crystalline quality containment buffer layer. According to a specific implementation of the present invention, the substrate 22 is a single crystal silicon wafer, preferably a large-size single crystal silicon wafer. The wafer may be a Group IV material of the periodic table 'and is preferably a Group IVA material. Properties of Group IV semiconductor materials -6- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Binding

503460 A7 _B7 ^ _._ 5. Description of the invention (4) Examples include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and so on. The substrate 22 may also belong to a synthetic semiconductor material. According to the requirements of specific semiconductor structures, from IIIA and VA elements (III-V semiconductor composite), mixed III-V compounds, II (A and B) and VIA elements (II-VI semiconductor composite) And mixed semiconductor materials selected from the substrate II 2 in the mixed II-VI composition. Examples include gallium arsenide (GaAs), indium gallium arsenide (GalnAs), gallium aluminum (GaAlAs), indium phosphide (InP), cadmium sulfide (CdS), mercury cadmium telluride (CdHgTe), zinc selenide ( ZnSe), zinc sulfur selenide (ZnSSe), and the like. The substrate 22 is preferably a wafer containing silicon or germanium, and is preferably a high-quality single crystal silicon wafer as used in the semiconductor industry. The accommodating buffer layer 24 is preferably a single crystal oxide or gaseous material grown on the base substrate. According to a specific embodiment of the present invention, the amorphous intermediate layer 28 is grown on the substrate 22 and is located between the substrate 22 and the growing accommodation buffer layer 24 by oxidizing the substrate 2 2 during the growth of the accommodation buffer layer 24. . The amorphous intermediate layer is used to reduce the strain that may occur in the buffer layer due to the difference in the lattice constant between the substrate and the buffer layer. In this context, the lattice constant represents the distance between cell atoms as measured on the surface plane. If the amorphous intermediate layer does not relieve such strain, the strain can cause defects in the crystalline structure in the containment buffer layer. Next, defects in the crystal structure in the containing buffer layer will make it difficult to achieve a high-quality crystal structure in the ferromagnetic material layer 26. The accommodating buffer layer 24 is preferably a single crystal oxide or nitride material compatible with the crystals of the base substrate and the crystals of the covering metal oxide material. For example, this type of material may be a ferromagnetic material that has a substrate that roughly matches the substrate and subsequent supplies of this paper are applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 503460 A7 B7 V. Description of the Invention (5) Lattice structure of oxides or nitrides. Materials suitable for containing the buffer layer include oxidized metals, such as soil test metal's acid salt, soil test metal sulphate, soil test metal salt, soil test Zhao salt, soil test ruthenate, alkaline earth metal niobium Acid salts, alkaline earth metal vanadates, perovskites such as alkaline earth metal tin-based perovskite, alkaline earth metal aluminates, lanthanum aluminates, lanthanum oxides, and oxide chaos. Alternatively, nitrides such as gallium nitride, aluminum nitride, and boron nitride can be used as the storage buffer layer. Most of these materials are insulators, although (for example) gills and ruthenium are conductors. In general, these materials are oxidized metals or nitrided metals', especially 'these oxidized metals or nitrided metals include at least two different metal elements' and have a bow-like lattice structure. In some specific applications, the metal oxide or metal nitride includes at least three or more different metal elements. The amorphous intermediate layer 28 is preferably composed of an oxide 'formed by oxidizing the surface of the substrate 2 2, especially by oxidation; The thickness of the amorphous intermediate layer 28 is sufficient to reduce the strain caused by the mismatch between the lattice constants of the substrate 22 and the storage buffer layer 24. Generally, the thickness of the amorphous intermediate layer 28 is about 0.5 to 5 nanometers (nm). The ferromagnetic material of layer 26 may be selected according to the requirements of a specific structure or application. For example, materials suitable for the ferromagnetic material layer 26 include the general chemical formula (AxB ^ jJCCb 'where X is in the range of 0 to 1 and where a is steel or neodymium, B is gill, barium, calcium or lead, and c Is Mn, (MnyC〇1-y) or (ΜηζΝυ, where y and z are greater than zero and less than one. A suitable template material is chemically bonded to the surface of the containing buffer layer 24-8-This paper size applies to Chinese national standards (CNS) A4 specification (210X297 public love) B7 V. The selected part of the invention description (6), and provided the subsequent ferromagnetic material layer 2 6 epitaxial growth nucleation site. When used, the thickness of the template layer 30 Between 1 to 10 monolayers. Figure 2 shows a cross-sectional view of a portion of a microelectronic structure 40 according to another embodiment of the present invention. Structure 40 is similar to structure 20 described previously. In addition to the additional insulating layer 32, which is located on the ferromagnetic material 26, and the second additional ferromagnetic material layer 33, which is formed on the insulating layer 32. The insulating material suitable for the insulating layer 32 may include a mating receiving buffer layer 2 4 Any of the listed insulation materials, while ferromagnetic materials 3 3 may include any of the ferromagnetic materials listed in the mating layer 26. The layer 33 is typically about 1 to 6 nm, and preferably less than about 2.5 nm. Figure 3 shows a microscale according to another exemplary embodiment of the present invention. A schematic sectional view of a part of the electronic structure 34. The structure 34 is similar to the structure 40, except that the structure 34 includes an amorphous layer 36 instead of the buffer layer 24 and the amorphous interface layer 28. As shown below Detailed description, similar methods as described above can be used to form the amorphous layer 36 by first forming a containing buffer layer and an amorphous interface layer. Then, the containing buffer layer is annealed to crystallize a single crystal. The containing buffer layer is converted into an amorphous layer. The amorphous layer 36 formed in this manner includes materials from the containing buffer layer and the interface layer, and the amorphous layer may or may not be an amalgamate. Therefore, the layer 36 may include one layer or Two non-crystalline layers. The non-crystalline layer 36 (formed from layer 32) formed between the substrate 22 and the additional buffer layer 32 reduces the stress between the layers 22 and 32, and is used to meet the standard substrate 'Eli Subsequent processing-for example, the formation of the ferromagnetic material layer 26. -9- i Paper size suitable for financial standards (CNS) A4 specifications (21GX 297 public) " " -------- 503460 A7 ___ _B7 V. Description of the Invention (7) The process described above with reference to Figs. 1 and 2 is suitable for growing a single-crystal ferromagnetic material layer on a single-crystal substrate. However, the description with Fig. 3 includes accommodating a single-crystal buffer layer The manufacture of the layer converted to an amorphous oxide is more suitable for growing a layer of a single crystalline ferromagnetic material because it allows any stress in the layer 32 to be relaxed before the layer 26 is formed. According to a specific embodiment of the present invention, the layer 30 is used as an annealing cap during the formation of the layer 36, and is used as a template during the subsequent formation of the ferromagnetic material layer 26. Therefore, the thickness of the layer 30 is preferably sufficient to provide a template (at least one monomolecular layer) suitable for the growth layer 26, and is thin enough to allow the formation of the layer 30 as a defect-free single crystal layer (typically less than about ten layers). Monolayer) The following non-limiting, exemplified examples illustrate various combinations of materials available in structures 20, 40 and 34 according to various alternative embodiments of the present invention. These are all used for illustration, and the present invention is not limited Take these examples for illustration. Example 1 According to a specific embodiment of the present invention, as shown in the figure! As shown, the single crystal substrate 22 is a silicon substrate having a (100) direction as a purpose. Silicon substrates can be, for example, shredded substrates commonly used in complementary metal-oxide-semiconductor (CMOS) integrated circuits with a diameter of approximately 200 to 300 mm. According to this specific embodiment of the present invention, the containing buffer layer 24 is a single crystal layer of SrgBaNgTi03, instead of the end of the day = the intermediate layer is SiOx formed on the interface between the silicon substrate and the containing buffer layer. Floor. The composition of layer 24 is selected to obtain a close match of the lattice constants of the subsequent subsequent formation of layer 26.

⑽460

number. For example, the thickness of the accommodating buffer layer is in a range of about 2 ηπ ^ 100 nm, and preferably a thickness of about 10 nm. In general, it is desirable that the thickness of the buffer layer is sufficient to isolate the ferromagnetic layer from the substrate to obtain the desired characteristics. Layers below 100 nm typically provide fewer additional advantages and add unnecessary costs; however, thicker layers can be made if needed. Oxidation = The thickness of the amorphous intermediate layer is in the range of about 0.5 nm to 5 nm, and preferably about 1.5 nm to 2.5 nm. According to this specific embodiment of the present invention, the ferromagnetic material layer 26 is a USi * MnO3 layer having a thickness of about 5 nm to about 500, and preferably a thickness of about 20 to 70 nm. The thickness usually depends on the application of the prepared layer. Example 2 According to another specific embodiment of the present invention, as shown in FIG. 3, a structure suitable for MTJ applications is provided. As mentioned above, the substrate is preferably a wafer. A suitable material for containing the buffer layer is SrgBai-gT103, where g is in the range of 0 to i, the thickness is in the range of about 2 nm to 100, and preferably the thickness is about 5 nm to 15 nm. The ferromagnetic material layer 26 may be, for example, LaSlMnOy and the thicknesses of the layers 26 and 33 are about 5 nm to about 50 nm, and preferably about 20 nm to 70 nm. The layer 3 2 between the ferromagnetic layers ⑽ 3 3 includes SrgBabgTiCh, where g is in the range of 0 to i, and the thickness is about 2.5 ηπ. Please refer to FIGS. 1 to 3 again. The substrate 2 * 2 is a single crystal substrate such as a single crystal dream or a broken substrate. The crystal structure of a single crystal substrate is characterized by a lattice constant and a lattice direction. In a similar method, the holding buffer layer M is also -11-this paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 public love) ---- 503460 A7 B7 V. Description of the invention (9) Single A crystalline material and a single crystalline material are characterized by a lattice constant and a crystal orientation. The accommodating buffer layer and the single crystal substrate must be closely matched, or one crystal direction must be rotated toward the other crystal direction to achieve a substantially lattice constant match. In this context, “substantially similar” and “substantially matched” indicate that there are sufficient similarities between the lattice constants, and a high-quality crystalline layer can be grown on the base layer. Figure 4 shows the achievable relationship between the thickness of the growing crystal layer of high crystal quality as a function of the mismatch between the lattice constants of the main crystal and the growing crystal. Curve 4 2 Limits of high crystalline quality materials. The area to the right of curve 4 2 represents a layer with a large number of defects. Due to the lattice matching, infinite thickness and high-quality epitaxial layers can be grown on the main crystal. As the lattice constant mismatch increases, the thickness of the high-quality crystal layer can be rapidly decreased. For example, as a reference point, if the lattice constant mismatch between the main crystal and the growth layer exceeds approximately 2%, a single crystal system crystal layer exceeding approximately 20 nm cannot be achieved. According to a specific embodiment of the present invention, the substrate 22 is a single crystal silicon wafer with a direction of (100) or (111), and the containing buffer layer 24 is a gill barium titanate layer. The way to achieve a substantial matching of the lattice constants of the two materials is to rotate the crystal orientation of the titanate material by 45 ° with respect to the crystal direction of the broken substrate wafer. In this example, if the thickness is thick enough, the silicon oxide layer included in the amorphous intermediate layer 28 structure is used to reduce the strain of the titanate single crystal layer, because the strain of the titanate single crystal layer will cause the main silicon crystal The lattice does not match the lattice constant of the growing titanate layer. As a result, according to a specific embodiment of the present invention, a high-quality, thicker single crystal layer titanate layer can be achieved. Please refer to Figures 1 to 3 again. Layers 26 and 33 are epitaxially grown ferromagnetic material layers. -12- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Device% 503460 A7 B7 V. Description of the invention (10), and the crystalline material is characterized by a lattice constant and a crystal orientation. According to a specific embodiment of the present invention, the lattice constant of the layer 26 is different from the lattice constant of the substrate 22. In order to achieve the south crystal quality, the crystalline growth early crystal layer 'accommodating buffer layer must have south crystal quality. In addition, in order to achieve a layer 2 6 of τ% crystal quality, it is desirable that the main crystal (in this case, the 'main crystal is an early-crystal-accommodating buffer layer) substantially match the lattice constant of the growing crystal. With the correct selection of the material, 'the crystal direction of the growing crystal will rotate relative to the main crystal', so the lattice constants can be roughly matched. In some cases, a crystalline buffer layer between the main crystalline oxide and the growing metal oxide layer can be used to reduce the strain of the growing single crystal ferromagnetic material layer because the strain causes a small difference in the lattice constant. This can achieve the best growth of the single crystal ferromagnetic material layer. Crystal quality 0 The insulating layer 3 2 is also characterized by the lattice constant and lattice direction. According to a specific embodiment of the present invention, the selected insulating layer 32 can be positioned so that the lattice constant of the layer 32 substantially matches the lattice constants of the layers 26 and 33. The following describes a method of manufacturing a microelectronic structure such as the structure shown in FIGS. 1 to 3 according to a specific embodiment of the present invention. The method begins by providing a single crystal semiconductor substrate including silicon. According to a preferred embodiment of the present invention, the semiconductor substrate is a silicon wafer having a (100) direction. The substrate is preferably oriented along the axis, and is offset from the axis by at most about 0.5. . At least a portion of a semiconductor substrate has a bare surface, but other portions of the substrate may surround other structures, as described below. In this context, the term "bare" means that the surface of the substrate has been removed to remove oxides, contaminants, or other foreign materials. As everyone knows, bare silicon is highly reactive and easily formed. -13- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Equipment% 503460 A7 B7 V. Description of the invention (11) Natural oxide. The term "naked" encompasses such natural oxides. It is also possible to intentionally grow thin silicon oxide on a semiconductor substrate, however such growth oxides are not necessary for the method according to the invention. In order to epitaxially grow a single crystal oxide layer to cover the single crystal substrate, the natural oxide layer must be removed first to expose the crystal structure of the base substrate. The following methods are best achieved by molecular beam epitaxy (MBE) method, although other epitaxial growth methods can be used according to the present invention. Natural oxides are removed by first thermally depositing a thin layer of gills, barium, a combination of gills and barium, or other alkaline earth metals or alkaline earth metals in an MBE device. In the case of gills, the substrate is then heated to approximately 750 ° C to chemically react the gills with the natural silicon oxide layer. The gill system is used to break down silica, leaving a silica-free surface. 1 * The surface produced by Daddy includes gills, oxygen, and silicon, and presents a neat 2 X 1 structure. The neat 2x1 structure forms a template for the orderly growth of a monocrystalline oxide overlay. The template provides the necessary chemical and physical properties to build up a crystal-grown overlay. According to an alternative embodiment of the present invention, a natural silicon oxide can be converted and a substrate surface can be prepared to grow a single crystal oxide layer by depositing, for example, gill oxide, gill oxide barium, or barium oxide on the surface of the substrate by MBE at a low temperature. Like alkaline earth metal oxides, the structure is then heated to about 750 ° C. At this temperature, the solid state reaction between the oxidized gills and natural silicon oxide results in the reduction of natural silicon oxide, leaving a neat 2x1 structure with gills, oxygen, and silicon on the substrate surface. Again, a template is formed in this manner to subsequently grow an ordered single crystal oxide layer. According to a specific embodiment of the present invention, the oxidation on the surface of the substrate is removed. -14- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm).

Pretend

After silicon, the substrate is cooled to a temperature in the range of about 200 to 80 (rc), and a gill titanate layer is grown on the template layer by molecular beam epitaxy. Pening shutte〇 began to expose gills, titanium, and oxygen sources. The ratio of gill to titanium is about 丨: 丨. The partial pressure of oxygen was initially set to a minimum of 値 to facilitate growth at a growth rate of about 〇. Gill titanate. After initial growth of gill titanate, increase the oxygen partial pressure to approximately the initial minimum 値. Oxygen overpressure will cause growth at the interface between the base substrate and the growing gill titanate layer Amorphous silicon oxide. The growth of the silicon oxide layer is due to the diffusion of oxygen through the growing gill titanate layer to the surface of the base substrate where oxygen reacts with silicon. The iron's salt grows into ordered single crystals, The crystalline orientation of the base substrate with respect to the neat 2 X 1 crystal structure is rotated by 4. 5. Otherwise, there may be strain in the total acid salt layer, because the lattice constant between the silicon substrate and the growing crystal is slightly different. This kind of strain can be mitigated in the intermediate layer of amorphous silica. After the gill titanate has grown to the desired thickness, the monocrystalline gill titanate is then covered by the template layer to promote subsequent growth. The desired material worm crystal layer. For example, the way to cover the single crystal layer of wei's salt of MBE is to cover 1 to 2 monomolecular layers, 1 to 2 monomolecular layers of oxo-oxygen, or 1 to 2 layers. A monolayer of strontium-oxygen is used to terminate the growth. After the template is formed (if a layer is formed), ferromagnetic materials are grown using MBE or other suitable techniques. By the method described above and adding an insulating layer deposition step, ie The structure shown in Fig. 2 can be formed. The method described above for the formation of the mating layer 24 can be used to epitaxially form an insulating material layer 32 on the layer 26, except for the layers 26 and -15. Standard (CNS) Α4 specification (210 × 297 mm) 503460

It is preferable not to form an amorphous interface layer between 3 and 2. Therefore, it is preferable to form the insulating layer using conditions that are conducive to the speculative growth layer 26. The structure 34 shown in FIG. 3 may be formed by growing a buffer layer and forming an amorphous oxide layer on the substrate 22, as described above. Then, the Gona buffer layer and the amorphous oxide layer are subjected to an annealing process, so that the crystal structure of the buffer layer is sufficient to change from a single crystal to an amorphous phase. By forming the amorphous layer, the amorphous oxide layer and the current amorphous phase are formed. The combination of the crystalline containing buffer layers forms a single amorphous oxide layer 36. A layer 26 is then grown on the layer 32. Alternatively, an annealing process may be performed to grow the layer 26. According to an aspect of this specific embodiment, the method of forming the layer 36 is to subject the substrate 2 2, the containing buffer layer, the amorphous oxide layer and the layer 30 or a suitable cover layer to a rapid thermal annealing process, and the highest temperature used About 70 ° C to about 1000 ° C. The process time is about 10 seconds to about 10 minutes. However, according to the present invention, other suitable annealing processes may be used to convert the containing buffer layer into an amorphous layer. For example, the Layer 36 is formed using laser annealing or "traditional" thermal annealing processes (in the appropriate environment). The ferromagnetic layer 5 2 (eg, (LakSn-OMnO3, where k is greater than zero and less than beans) is deposited using a low-temperature deposition method Worm crystals grow. Specifically, the target is (LakSri-k) Mn〇3, and the (LakSn-jJMnO3 layer) is grown by RF magnetron sputtering method (face-to-face configuration). The deposition is performed using oxygen as the execution Gas is sputtered and the substrate temperature is about 40 ° C. The method described above illustrates a method for forming a semiconductor structure by molecular beam epitaxial growth and RF sputtering. The semiconductor structure includes a stone substrate, Covering the oxide layer and a ferromagnetic material layer may also by

Binding% -16-

503460 A7 B7___ V. Description of the invention (Η) Chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy MEE), atomic lay epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (pulsed laser deposition; PLD) and so on. In addition, by a similar method, other single crystal containing buffer layers can be grown, such as soil test metal's acid salt, soil test metal zirconate, soil test metal salt, soil test salt, Earth metal vanadates, earth metal ruthenates, alkaline earth metal niobates, oxidation # 5 such as alkaline earth metal tin-based perovskite, lanthanum aluminates, Lanthanum thorium oxide and thorium oxide. In addition, by a similar method such as MBE, other metal oxide layers can be deposited to cover the single crystal oxide containing buffer layer and / or the ferromagnetic layer. Each variation of the ferromagnetic material and the single crystalline oxide layer uses an appropriate template layer to facilitate the growth of the individual layers. In this case, an appropriate template material can be grown according to the method described above in conjunction with the growth layer 26. FIG. 5 shows a schematic sectional view of a semiconductor structure 90 according to the present invention. The semiconductor structure 90 includes a single crystalline semiconductor substrate 92, a single crystalline insulating layer 94 covering the substrate 92, and a magnetic tunnel junction device 96 covering the insulating layer. According to a specific embodiment of the present invention, the insulating layer 94 is a single crystal oxide layer epitaxially grown on a substrate. Fig. 6 shows the semiconductor structure 9 8 which is broadly similar to the structure shown in Fig. 5-17-This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 503460 A7 B7 V. Description of the invention (15 ) Surface schematic. In FIG. 6, the magnetic tunneling interface 96 is depicted as a first layer 100 covering the insulating layer 94, a second layer 102 covering the first layer 100, and a third layer 104 covering the second layer 102. According to an aspect of the present invention, the first layer 100 and the third layer 104 can exhibit strong magnetic properties. In the illustrated specific embodiment, the first layer 100 and the second layer 102 can be grown in a tethered manner on the respective base layers. In addition, the second layer 102 is a single crystalline insulating layer. In addition, one or both of the first layer 100 and the third layer 104 may be a single crystal layer. In a particularly preferred embodiment, the substrate 92 is silicon. The insulating layer 94 preferably includes a single crystalline material selected from the group consisting of a metal oxide and a metal nitride. Specifically, the insulating layer 94 is preferably selected from the following materials: alkaline earth metal titanate, alkaline earth metal hammer salt, earth test metal salt, earth test metal Ie salt, earth test metal vanadate, alkaline earth metal ruthenium Acid salts, alkaline earth metal niobates, including perovskites which are tin-based perovskites, lanthanum aluminates, lanthanum oxide, hafnium oxide, gallium oxide, and aluminum nitride. In a particularly preferred embodiment, the first layer 100 is preferably a single crystalline oxide, for example, Borgan # 5 'ore (manganite perovskite), but any suitable material having a (A, B) C03 composition may be used Made of, where A is selected from the group consisting of lanthanum and neodymium, B is selected from the group consisting of gills, barium, calcium, and lead, and C is selected from Mn, (Mn, Co), and (Mn , Ni). In a specific preferred embodiment, the third layer 104 is preferably a single crystalline oxide, for example, # 成 短 矿 # 5 'ore (ma'nganite perovskite), but it can be described in conjunction with the first layer 100 Made of any material. The second insulating layer 102 is preferably a single crystalline oxide with a thickness ranging from 1 to 6 nm. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 5. Invention Note (16) within the 'and preferably the lattice matches the first layer. In a particularly preferred embodiment, the thickness of the second insulating layer 102 is less than 25 micrometers, and for the first layer ⑽, the lattice matching is in the range of about four percent. In addition, the second insulating layer 102 is constructed to provide an atomic interface with the first layer 100. The second insulating layer 102 can be made of a material selected from the group consisting of: alkaline earth metal's acid salt, soil test metal zirconate, soil test metal salt, soil test metal salt, alkaline earth metal vanadium Acid salts, alkaline-earth metal ruthenates, alkaline-earth metal salts, lye mines containing tin-based arsenite, lanthanum salts, lanthanum oxide, and oxidized milk. According to a further aspect of the invention, the first layer 100, the second layer 1.2, and the third layer 104 may be patterned according to widely known manufacturing techniques to form (at least to some extent) a magnetic tunnel junction device. By manufacturing a magnetic tunnel junction device on a single crystalline (eg, silicon) substrate 92 according to the present invention, cost reduction can be achieved in general because the single junction $ substrate 92 is sufficiently expandable. FIG. 7 shows a broad similarity The cross-sectional schematic diagram of the semiconductor structure 106 of the structure 98 shown in FIG. 6, but it also includes a template layer US covering the insulating layer. The template layer 118 facilitates the termination of the insulating layer 94 and can be made of oxygen and an element selected from gill, barium, calcium, or lead. The thickness of the template layer 118 ranges from 1 to 10 monomolecular layers. FIG. 8 also shows a schematic sectional view of a semiconductor structure that is broadly similar to the structure shown in FIGS. 5 to 7, and further shows an integrated logic element 13, such as a metal-oxide semiconductor (at least partially formed in the substrate 92) For example, CMOs) circuit. In a preferred embodiment, the logic element 130 may be electrically connected to the magnetic tunneling interface through an interconnect 108. In the illustrated specific embodiment, each other 503460 A7 — — _____B7__ 5. Description of the invention (17) The connection 108 connects the logic element 130 to the second layer 102. FIG. 9 shows a schematic cross-sectional view of a semiconductor structure 112 broadly similar to the structure shown in FIGS. 5 to 8. The semiconductor 112 includes a tension relaxation layer 114, for example, an amorphous oxide layer under the insulating layer 94. In this regard, the amorphous oxide layer 114 is generally similar to the intermediate layer 28 previously described in conjunction with FIGS. 1 and 2. FIG. 10 shows a schematic cross-sectional view of a semiconductor structure 116 that is broadly similar to the structure 98 shown in FIG. 6. . The semiconductor structure 116 includes a magnetic tunneling interface 96 located on a first electronic contact layer 120 (which is formed below and electrically contacts the first layer 100) and a second electronic contact layer 122 (which covers and electrically contacts the third layer 104) )between. One or both of the layers 120 and 122 preferably include a single crystalline electron-conducting oxide layer, and may be made of a material selected from the group consisting of (LakSivOCoOs, SrRu03, SrCi * 03, and SrV03, where k is greater than zero And less than one. Figure 11 shows a schematic cross-sectional view of a semiconductor structure 1 2 4 including a single crystal (eg, silicon) substrate 92 and a single crystal oxide layer 94 (preferably epitaxial growth to cover the substrate 92). And a magnetic tunneling inspection device 96. The magnetic tunneling junction device 96 preferably includes a first layer 100 made of a single crystal ferromagnetic material, and a second layer 102 made of a single crystal insulating material (Which covers and forms an atomic interface with the first layer 100) and a third layer 104 made of a ferromagnetic material. The second layer 102 is preferably thin enough to allow tunneling from there. The three layers 104 are advantageous for presenting an ordered-single crystal structure. In a preferred embodiment, the first layer 100, the second layer 102, and the third layer 104 are all epitaxially grown single crystal materials on their respective base layers. The second insulating layer 102 is preferably selected from -20-this paper size applies to China Standard (CNS) A4 size (210X297 mm) 503460 A7

The group of electrical insulating oxides consisting of: alkaline earth metal titanate, alkaline earth metal hammer salt, alkaline earth metal phosphonate, alkaline earth metal ㈣m gold salt, soil test metal ㈣ salt, soil test metal Salts, perovskites containing genus-based perovskites, lanthanum aluminates, lanthanum oxide mills, and hafnium oxide. Fig. 12 shows a schematic sectional view of a semiconductor structure 126, which includes a substrate 92 having a logic element 130 formed at least partially therein, an insulating layer 94, and a magnetic tunneling surface 96. The semiconductor structure 126 further includes an amorphous oxide layer 114 and an electrical interconnect 132 that is configured to electrically couple the logic element 130 to the layer 104. The insulating layer 94 is preferably a single crystalline oxide layer made of SrgBaggTiOs, where g 其中 is in the range of 0 to i. The single crystal layer 102 is preferably an oxide having a thickness in the range of 1 to 6 nmi, and the lattice matching of the layer 100 is in the range of about four percent. The various semiconductor structures illustrated and described herein can be fabricated using the processing techniques described above in conjunction with Figures 丨 3. By fabricating the magnetic tunneling junction device described herein on a single crystalline semiconductor substrate 92, monolithic integration between the magnetic tunneling junction structure and the microelectronic structure associated with the substrate 92 can be achieved. FIG. 13 shows a schematic sectional view of the integrated magnetic tunneling junction circuit ι40. The semiconductor structure 140 includes a template layer 142 covering the substrate 92 and an insulating layer 94. As explained in the foregoing with reference to Figs. 1 to 3, the amorphous oxide layer n4 is advantageous for manufacturing during the epitaxial growth of the insulating layer 94 on the substrate 92. After that, it is advantageous to manufacture the second template layer 144 on the insulating layer 94 layer. The second template layer 144 may promote the crystalline growth of the first ferromagnetic oxide layer 100. According to a preferred embodiment, it is best to epitaxially grow a second insulating oxide layer on the first ferromagnetic oxide layer 100. This paper size is applicable to China National Standard (CNS) A4 (210X 297 cm) (Centimeter)

Binding% 503460

102. The semiconductor structure 140 of FIG. 13 shows the photolithographic patterning process of the first layer 100, the second layer 102, and the third layer 104 to allow the logic element 130 whose magnetically-connected surface can be associated with the substrate 92. Monolithic integration. Specifically, the electrical interconnect 134 provides electrical contact between the logic element 13 and each of the first and third layers 100 and 104. Specifically, the interconnection 34 is constructed to contact the electrode 136 associated with the third layer and the electrode 13 8 associated with the first layer 100. In the context of the illustrated embodiment, any suitable method may be used to grow the single crystalline layer, including MBE, MOCVD, MEE, CVD, PVD, PLD, CSD, and ALE. Of course, if applicable, these techniques can be used to grow any of the layers illustrated herein. According to a further aspect of the present invention, the way to form the template layer may be to terminate the growth of a basic single crystal layer having 1 to 10 monomolecular layers of oxygen, and a material selected from the group consisting of thallium, barium, # 5 and lead . A preferred method of manufacturing the magnetic tunnel junction interface structure 46 will now be described with reference to FIG. First, a single crystal silicon substrate 92 is provided. Thereafter, any combination of the deposition methods described herein is used to successively deposit layers to form a semiconductor stack. In a preferred embodiment, an insulating layer 94 including a SrgBa ^ gTiO3 layer is preferably deposited on the substrate 92, where g 値 is in the range of zero to one. A ferromagnetic layer 100 is then deposited on the insulating layer 94. The ferromagnetic layer ιOO is preferably (A, B) C03 composite material, where A is selected from the group consisting of lanthanum and neodymium, and B Is selected from the group consisting of gill, barium, calcium and lead, and c is selected from the group consisting of Mn, (Mn, Co) and (Mn, Ni). An insulating tunneling oxide layer 102 is then deposited on layer 100. Then, deposit strong magnetism on layer 102. -22- This paper size is in accordance with China National Standard (CNS) A4 (210X 297 mm)

Load% 503460 A7 B7 layer 104, suitable material is similar to the material of layer 100. FIG. 15 shows a schematic sectional view of a semiconductor structure 156, which is broadly similar to the structure 146 shown in FIG. 14, and is used to further explain the amorphous layer 114 and the logic element 13 which are at least partially formed in the substrate 92. FIG. 16 shows a schematic cross-sectional view of a semiconductor structure 158 that is broadly similar to the structure 146 shown in FIG. 14 to further explain the steps above the patterned layer 100, 10 =, and 1044-layer or -layer, thereby Respective nodes 150 and 154 are generated, which may correspond to any desired combination of voltage or current nodes. Those skilled in the art will appreciate that one or more of the patterned layers 100, 102, and 104 can produce a magnetic tunnel junction device of any desired configuration. FIG. 17 shows a cross-sectional schematic diagram of a semiconductor structure, which is broadly similar to the structure 158 shown in FIG. 16, which further includes the following additional steps: depositing a conductive material layer 180 and patterning the layer 180 to produce individual Nodes i64, 166, and 168. In a particularly preferred embodiment, it is suitable to fabricate interconnects 170 in the semiconductor substrate 160 to connect one or more nodes (e.g., electrodes) of the nodes 164 to 168 to the logic element 13o. In particular, the methods and structures shown in Figs. 12 to 17 illustrate the advantages of manufacturing a magnetic splice device on a single crystalline semiconductor substrate, thereby allowing the magnetic tunnel junction device to be monolithically integrated with the logic elements associated with the substrate. Fig. 18 shows a schematic sectional view of a semiconductor structure 162, which includes the following additional steps: a conductive oxide layer 172 is deposited on the insulating layer 94, and the ferromagnetic layer 100 is electrically contacted. The best manufacturing step of the conductive oxide layer 172 is to deposit a material selected from the group consisting of (LakSrlk) Co03, Si * Ru〇3, Si * Cr03, and SrV〇3, where k is greater than zero and less than one. . -23- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 503460 A7 B7

V. Description of the invention (21 In the previous description, the invention has been described with reference to specific embodiments. However, those skilled in the art should understand the various modifications of the invention and easily modify them without departing from the patent application examples below. The scope and spirit of the present invention is provided. Therefore, the description and drawings should be regarded as illustrations, not as limitations, and all such modifications are within the scope of the present invention. Advantages, other advantages, and problem solutions. However, any advantage, advantage, and solution that can cause or become more significant, advantages, advantages, problem solutions, and any components should not be understood as the key and necessary of any or all patent application examples Item or basic function or element. As used herein, the term Γ includes "," includes "or any other variation thereof is used to encompass non-proprietary inclusions such that the method, method, article, or device includes a list of components Includes not only these elements, but also methods or methods, articles, or devices that are not explicitly listed or such Other elements. -24- This paper scales applicable Chinese National Standard (CNS) A4 size (210X 297 mm)

Claims (1)

• A magnetic tunnel junction structure includes: a single crystal semiconductor substrate; a single crystal insulating layer to cover the substrate; M — a first layer that is epitaxially grown to cover the single crystal insulating layer, the first layer The layer is said to exhibit strong magnetic properties;-a second single-crystal insulating layer, which is epitaxially grown to cover the first layer; and-a third layer, to cover the second single-crystal insulating layer, the third layer can present Strong magnetic properties. 2. The structure according to item 1 of the patent application scope, wherein the first layer is a single crystal. 3. The structure of item 2 of the patent application park, wherein the third layer is a single crystal. 4 · The structure according to item 1 of the patent application scope, wherein the substrate comprises silicon. 5. The structure according to item 4 of the scope of patent application, the structure further including at least a portion of the CMOS circuit formed in the substrate. 6. The structure according to item 1 of the scope of patent application, wherein the single crystalline insulating layer comprises a material selected from the group consisting of a metal oxide and a metal nitride. 7. The structure according to item 6 of the scope of patent application, wherein the single crystalline insulating layer comprises a material selected from the group consisting of: soil test metal's acid salt, soil test metal salt, soil test Metal salt, metal test salt, metal test salt, metal test ruthenate, metal test niobate, perovskite containing tin-based perovskite, lanthanum aluminate, Lanthanum hafnium oxide, hafnium oxide, gallium nitride and aluminum nitride. 8 · If the structure of the 6th scope of the patent application, where the first layer includes -25- this paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 刈 3460 ^^ # 5 ^. (Manganiteperovskite). 9. The structure according to item 6 of the scope of patent application, wherein the first layer includes a material having an (AxBhdCO3 composition, wherein a is selected from the group consisting of lanthanum and neodymium, and B is selected from the group consisting of gill and barium Of calcium, calcium, and lead, and χ is in the range of 0 to 1, and c is selected from) (y is greater than 0 and less than or equal to 1) * (MnzNii z) (z is greater than 0 and less than or equal to 1 ). 10. The structure of claim 9 in which the first layer includes a single crystalline oxide. 1 1 · If the structure of item 9 of the scope of patent application, the structure further includes a template layer covering the crystalline insulation layer. 1 2 · The structure according to item 丨 丨 in the patent application range, wherein the template layer terminates the single crystalline insulating layer and includes a layer containing oxygen and an element selected from the group consisting of gill, barium, calcium and lead . 1 3 · The structure according to item 12 of the scope of patent application, wherein the thickness of the template layer is 1 to 10 monomolecular layers. 1 4 · The structure of item 6 in the scope of patent application, wherein the third layer includes a hydroxyl shoe mine # 5 妖 矿 (manganite perovskite) 〇 15. The structure of item 6 in the scope of patent application, wherein the third layer includes A material having an (AxBNx) C03 composition, where a is selected from the group consisting of lanthanum and neodymium, B is selected from the group consisting of gill, barium, calcium, and lead, and X is between OSi Within the range, and c is selected from the group consisting of Mn, (MnyCoiy) (y is greater than 0 and less than or equal to 丨) and (MllzNii z) (z is greater than 0 and less than or equal to 1). -26- This paper size applies to Chinese National Standard (CMS) A4 specification (210 X 297 public attack) Patent application scope C8 D8 6. The structure according to item 15 of the scope of the patent application, wherein the third layer comprises-a crystalline oxide. 17. The structure of claim 6 in which the second single crystal insulating layer comprises an oxide having a thickness of 1 to 6 nm. 18 · The structure according to item 7 of the patent application scope, wherein the second single-crystal insulating layer includes a material having a lattice matching the first layer. 19. The structure as claimed in claim 6 wherein the second single-crystal insulating layer comprises a single-crystalline oxide having a thickness of less than 2.5 nm, and the oxide includes a lattice matching of about 4% to the first layer. Materials in the park. 2 0. The structure of item i in the scope of the patent application, wherein the second single crystalline insulating layer is constructed to provide an atomic interface with the first layer. 21. The structure according to item 6 of the scope of patent application, wherein the second single crystalline insulating layer comprises a material selected from the group consisting of: earth test metal titanate, alkaline earth metal zirconate, alkaline earth Metal salt, metal test salt, metal test salt, metal test ruthenate, metal test niobate, perovskite containing tin-based perovskite, lanthanum aluminate, Lanthanum oxide and thorium oxide. 22. The structure of claim 21, wherein the second single crystalline insulating layer comprises an alkaline earth metal titanate. 23. The structure according to item 1 of the scope of patent application, wherein the first layer, the second single crystalline insulating layer, and the third layer are patterned to form (to some extent) a magnetic tunnel junction device. 24. The structure according to item 23 of the scope of patent application, the structure further comprising at least a part of the integrated logic element formed in the semiconductor substrate. -27- This paper size applies to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 503460 ABCD 夂, patent application scope 25 · If the structure of the patent application scope item 24, the structure further includes a mutual connection 'It is formed on and electrically interconnects the integrated logic element and the magnetic tunnel junction interface device. 2 6. The structure according to item 1 of the scope of patent application, the structure further comprising an amorphous oxide tension relaxation layer formed under the single crystalline insulating layer. 2 7 · According to the structure of the scope of the patent application, the structure further includes a first electrical contact layer (which is formed below and electrically contacts the first layer) and a second electronic contact layer (which covers and electrically contacts the the third floor). 28. The structure of claim 27, wherein the first electrical contact layer includes a single crystalline electrically conductive oxide layer. 29. The structure of claim 28, wherein the first electrical contact layer comprises a material selected from the group consisting of (LakSri_k) Co03, SrRu〇3, SrCr〇3, and SrV〇3, where k is greater than Q is less than 1. A magnetic tunnel junction structure includes: a single crystal semiconductor substrate; a single crystal oxide layer that is grown by insect crystals to cover the substrate; a first single crystal ferromagnetic material layer to cover the single crystal An oxide layer; a second layer of early crystalline insulating material to cover the first layer and form a sharp atomic interface with the first layer, the second layer being thin enough to allow tunneling from there; and A third ferromagnetic material layer to cover the second layer. 3 1 · If the structure of the scope of patent application No. 30, where the third layer contains a -28 · This paper size applies to China National Standard (CNS) A4 specifications (210X 297 mm) State 460 A8 There is a layer of ordered monocrystalline material. 32. The structure of claim 30, wherein the first layer, the second layer, and the second layer all include an epitaxially grown single crystal material layer. 33. The structure of claim 30, wherein the first layer includes-a material having a (AxB ^ JCO3 composition, where A is selected from the group consisting of lanthanum and neodymium, and B is selected from the group consisting of rhenium and A group of lead, and X is in the range of 0 to 1, and c is selected from Mn, (MnyCoiy L (y is greater than 0 and less than or equal to 1) * (MnzNiiz) (z is greater than 0 and less than or y is equal to the group consisting of 1) 34. The structure according to item 33 of the patent application scope, wherein the second layer includes an electrically insulating oxide selected from the group consisting of: alkaline earth metal titanic acid Salt, alkaline earth metal zirconate, alkaline earth metal phosphonate, alkaline earth metal phosphonate, alkaline earth metal vanadate, alkaline earth metal ruthenate, alkaline earth metal niobate, perovskite containing tin-based perovskite, Lanthanum aluminate, lanthanum osmium oxide and praseodymium oxide. 35. The structure according to item 34 of the patent application, wherein the third layer includes a material having a (AJuJCO3 composition, of which eight series are selected from the group consisting of lanthanum and neodymium Group B is selected from the group consisting of gill, barium, calcium and lead, and X Is within the range, and c is selected from the group consisting of Mn, (MnyCoily) (y is greater than 0 and less than or equal to 1) * (MnzNik) (z is greater than 0 and less than or equal to 1). 36. — A kind of integrated magnetic tunneling junction circuit includes: a single crystal broken substrate; an integrated logic circuit formed at least partially in the silicon substrate; | -29- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 6. Scope of patent application-a first single crystalline oxide layer, which is epitaxially grown to cover the silicon substrate. A non-crystalline oxide, which is formed on the first single crystalline oxide Under the material layer; a second single crystalline oxide layer including a ferromagnetic material formed by epitaxy to cover the first single crystalline oxide layer; a third single crystalline oxide layer including a covering the An electrical insulating material for a second single crystal oxide layer, the third single crystal oxide layer is thin enough to allow tunneling therefrom; a fourth oxide layer includes a third oxide layer formed to cover the third single crystal A ferromagnetic material of an oxide layer; and an electrical interconnection, which Combine the integrated logic circuit and the fourth single crystal oxide layer. 37. The circuit of item 36 in the scope of patent application, wherein the integrated logic circuit includes a CMOS circuit. The circuit of item 6, wherein the first single crystalline oxide layer comprises a material selected from the group consisting of: alkaline earth metal titanate, alkaline earth metal zirconate, alkaline earth metal phosphonate, and soil test Metal boat salt, soil test metal vanadate, soil test metal ruthenate, alkaline earth metal niobate, perovskite containing tin-based perovskite, lanthanum aluminate, lanthanum hafnium oxide, and thorium oxide. 3 9. The circuit according to item 38 of the scope of application for a patent, wherein the first single crystalline oxide layer includes an earth metal salt. 40. If the circuit of item 38 of the scope of patent application is applied, wherein the first single crystal is oxidized -30- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 503460 The material layer includes SrgBa ^ gTiO3, where g 値 is in the range of 0 to 1. 4 1. The circuit of claim 38, wherein the second single crystalline oxide layer includes (AxB ^ JCO3, where A is selected from the group consisting of lanthanum and neodymium, and B is selected from the group consisting of gill, A group of barium, calcium, and lead, and X is in the range of 0 to 1, and C is selected from Mn, (MnyC〇iy) ㈠ greater than 0 and less than or equal to 1), and (MrizNih · ζ) (z A group of greater than 0 and less than or equal to 1). 42. The circuit of item 4 丨 in the scope of patent application, wherein the fourth oxide layer includes (ΑχΒι-χ) CO3 'where A is selected from the group consisting of lanthanum and neodymium, and B is selected from the group consisting of strontium, barium, A group of calcium and lead, and X is in the range of 0 to 1, and c is selected from Mn, (MnyCoi) (y is greater than or equal to 1), and (MnzNi! · Ζ) (z is greater than 0) And less than or equal to 丨). 43. The circuit of claim 38, wherein the third single crystalline oxide layer includes an insulating oxide material selected from the group consisting of alkaline earth metal titanate, alkaline earth metal hammer acid Salt, alkaline earth metal salt, alkaline earth metal button salt, alkaline earth metal vanadate, alkaline earth metal ruthenate, alkaline earth metal niobate, calcium 'ore containing tin-based perovskite, lanthanum aluminate, oxidation Lanthanum sharp and thorium oxide. 44. The circuit of claim 43 in the patent application scope, wherein the third single crystal insulating layer includes an oxide having a thickness between 1 and 6 nm. 45. The circuit of claim 43 in the patent application range, wherein the third single crystal oxide layer includes a pair of oxides in a lattice matching range of the second single crystal oxide layer in a range of about 4%. AB c D 503460 6. Application patent scope 46. A method for manufacturing an integrated magnetic tunnel junction interface circuit, the method includes the following steps: providing a single crystal semiconductor substrate; forming an integrated logic circuit, at least a part of which Parts are formed in the semiconductor substrate; a first template layer is formed to cover the semiconductor substrate; a single crystal insulating layer is grown on the system to cover the first template layer; during the growth of the single crystal insulation layer on the system, An amorphous oxide layer is formed under the single crystalline insulating layer; a second template layer is formed to cover the single crystalline insulating layer; a first ferromagnetic oxide layer is epitaxially grown to cover the second template layer; Growing a second single crystalline insulating oxide layer to cover the first ferromagnetic oxide layer; growing a second ferromagnetic oxide layer to cover the electrically conductive oxide layer; patterning the photolithographic method A first ferromagnetic oxide layer, the second single crystalline insulating oxide layer, and the second ferromagnetic oxide layer to expose a part of the integrated logic circuit; Electrode, to contact the first ferromagnetic oxide layer and the second ferromagnetic oxide layer; and forming an electrical connection to each other, extending from the integrated logic circuit portion to the electrode. 47. If the method of applying for the scope of the patent No. 46, which provides a single crystal half • 32- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 503460 The conductor substrate includes a step of providing on the surface of the single-crystal half-substrate substrate. The step of supplying-containing-having-oxygen-cutting of the substrate is performed, and the step of forming a first template layer includes the following steps. Deposition on the oxide dream layer-a material selected from the group consisting of a soil test metal and a soil test metal oxide; and heating the substrate to cause the material to react chemically with silicon oxide. 48. The method of claim 47, wherein the step of depositing-selecting the material of the group consisting of "free soil test metal and soil test metal oxide" includes: depositing-selected from the group consisting of barium, gills and barium gill mixtures, Material of the group consisting of barium oxide, gill oxide, and barium oxide gill. 49. According to the method of claim 48 in the scope of patent application, the step of growing a single crystal insulating layer in the crystal includes the following steps: heating the single crystal semiconductor substrate To a temperature between about 20 (rc and about 80 (Π: 2); and introducing a reactant containing gills, oxygen, and an element selected from the group consisting of barium, gills, and barium gadolinium. The method of item 49, wherein the inductive step includes controlling the total or barium to titanium ratio and controlling the partial pressure of oxygen. 5 1. The method of item 50 in the scope of the patent application, wherein a first amorphous oxide layer is formed The step includes adding oxygen partial pressure to more than the partial pressure required for epitaxial growth of the single crystal insulating layer. 52. The method according to item 49 of the patent application, wherein the step of forming a second template layer includes A material To cover the monolayer (capping) the single crystal oxide layer tramp, wherein the material is selected from -33-- This applies China National Standard Paper Scale (CNS) A4 size (210 X 297 mm) A8 B8 C8 A group consisting of drinking, oxygen, barium, lock oxygen, total iron and oxygen. 53. The method according to item 46 of the patent application, wherein the step of epitaxially growing a single crystalline insulating layer includes using a method selected from the group consisting of MBE, MocVD, CVD PVD, PLD, CSD, and ALE. The method performs the steps of epitaxial growth. 54. The method of claim 46, wherein the steps of epitaxial growth of a first-ferromagnetic oxide layer, epitaxial growth of a second single-crystal insulating oxide layer, and growth of a second ferromagnetic oxide layer are all The method includes the step of epitaxial growth by a method selected from the group consisting of MBE, MOCVD, MEE, CVD, PVD, PLD, CSD, and ALE. 5 5. The method according to item 46 of the patent application park, wherein the step of epitaxially growing a first ferromagnetic oxide layer includes the step of growing an (ΑχΒ ix) c03 composite oxide layer, wherein A is a selective The group consisting of free lanthanum and neodymium, B is selected from the group consisting of gill, barium, calcium, and lead, and X is in the range of 0 to 1, and C is selected from Mn, (MnyC〇1-y ) (y is greater than 0 and less than or equal to 1) and (MnzNii · ζ) (z is greater than 0 and less than or equal to 丨). 5 6 · The method according to item 46 of the patent application park, wherein the step of growing a second ferromagnetic oxide layer includes the step of growing an (ΑχΒ i · χ) c03 composite oxide layer, wherein A is selected The group consisting of free lanthanum and Syria, B is selected from the group consisting of gill, barium, calcium, and lead, and χ is in the range of 0 to 丨 ', and C is selected from Mn, (Mi ^ CobKy greater than 0) And less than or equal to 1) and (MnzNU (z greater than 0 and less than or equal to 1). 5 7 · The method according to item 46 of the patent application scope, wherein epitaxial growth of a second single -34- 503460 A8 B8 C8 _________D8 VI. The scope of patent application includes the step of growing a layer of crystalline insulating oxide layer, which includes a layer of insulating material selected from the group consisting of alkaline earth metal titanic acid Salt, alkaline earth metal hammer salt, alkaline earth metal phosphonate, alkaline earth metal mate, alkaline earth metal vanadate, alkaline earth metal ruthenate, soil test metal mirror salt, containing tin-based Ore, lanthanum acid salt, lanthanum oxide and thorium oxide. 5 8 · If the scope of patent application The method of item 46, wherein the step of epitaxially growing a single crystalline rural rim layer includes the step of growing a layer including an insulating material selected from the group consisting of alkaline earth metal citrate , Alkaline-earth metal hammer salt, alkaline-earth metal phosphonate, alkaline-earth metal button salt, alkaline-earth metal vanadate, alkaline-earth metal ruthenate, alkaline-earth metal niobium fe salt, containing about ore which belongs to tin group # 5 ', Lanthanum salt, osmium oxide and oxidized disorder. 59. The method according to item 58 of the patent application, wherein the step of epitaxially growing a first ferromagnetic oxide layer includes growing an (AxBi x) c03 composite. An oxide layer step, where A is selected from the group consisting of lanthanum and neodymium, B is selected from the group consisting of gill, barium, calcium, and lead, and χ is in the range of 0 to 1, and C is It is selected from the group consisting of Mη, (MnyCoiy) (y is greater than 0 and less than or equal to 1), and (MxizNUh is greater than 0 and less than or equal to υ.) 60. The method of claim 59, wherein A step of a first template layer includes terminating growth of the single crystal insulating layer Step, the single crystalline insulating layer has 丄 to 单 monomolecular layers of oxygen, and—a material selected from the group consisting of titanium, barium, calcium, and lead. • 35- Smart Scale Standards SS Home Standard (CNS ) Α4 € (297 replies) ----- Gutter 6 1 · The method according to item 46 of the patent application, wherein the step of growing a second ferromagnetic material includes the step of sputtering and depositing an oxide layer of (AxBix) c03 composite, wherein A is selected from the group consisting of lanthanum The group consisting of and convergence, B is selected from the group consisting of Wei, Suo, Wu and Cuo, and X is in the range of 0 to 丨, and C is selected from Mn, (MnyC〇1-y) (y is greater than 0 and less than or equal to 1) and (MnzNii.zKz is greater than 0 and less than or equal to i). A method for manufacturing a magnetic tunneling junction, the method comprising the following steps: providing a single crystal semiconductor substrate having a surface; epitaxially growing a single crystal insulating material layer on the surface; epitaxially growing a first ferromagnetic material Material layer to cover the single crystal insulating material layer; epitaxial growth of a second single crystal insulating oxide layer to cover the first layer; and forming a second ferromagnetic material layer to cover the second single crystal insulation Oxide layer. 63. The method according to item 62 of the scope of patent application, wherein the step of growing the first ferromagnetic material layer by vermicular crystals comprises a method selected from the group consisting of Mbe, MOC VD, MEE, CVD, PVD, PLD, CSD and ALE. The group method performs the step of growing a first ferromagnetic material layer of the worm crystal. 64. The method of claim 63, wherein the step of epitaxially growing a first ferromagnetic material layer includes the step of epitaxially growing a single-crystal ferromagnetic material layer. — 6 5 · The method according to item 62 of the patent application scope, wherein the step of forming a second ferromagnetic material layer includes the step of forming a second layer by PVD. -36 · This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 503460 A8 B8 C8 Patent application scope 66 'As in the method of patent application item 65, the method of forming a second layer includes A step of forming a layer having an ordered single crystal structure. 67. The method of claim 62, wherein the step of epitaxially growing a second single crystalline insulating oxide layer includes the step of growing an alkaline earth metal oxide layer having a thickness of 1 to 6 nm. 68. The method of claim 62, wherein epitaxial growth of a second single crystalline insulating oxide layer includes the step of growing an oxide layer that is thin enough to allow tunneling therefrom. 69. The method of claim 62, wherein the step of epitaxially growing a first and second single crystalline insulating oxide layer includes growing a pair of lattices of the first ferromagnetic material layer within a range of about 4%. Step of oxide layer. 70. The method of claim 69, wherein the step of epitaxially growing a second single crystalline insulating oxide layer includes the step of growing a layer having a thickness of less than 2.5 nm. 71 · —A method of manufacturing a magnetic tunnel junction interface circuit, the method includes the following steps: * providing a single crystalline silicon substrate, and by selecting from the group consisting of MBE, MOCVD, MEE, CVD, PVD, PLD, CSD and ALE The method of forming a group is to successively deposit the following single crystal crystalline layers: a SrgBa ^ gTiCh layer, which will be in the range of 0 to 1; a (ΑχΒ ^ χ) layer of ferromagnetic material of CO3 composition, where a It is selected from the group consisting of lanthanum and neodymium, and B is selected from the group consisting of gill, barium, dance, and wrong. -37- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 503460 ABCD Six, The group of patent application ranges, and X is in the range of 0 to 1, and C is selected from Mη, (MnyCow) (y is greater than 0 and less than or equal to i), and (MnzNii z) (ζ is greater than 0 and less than or A group consisting of 1); an insulating tunneling oxide layer; and a second (AxBi-x) C03 composite ferromagnetic material layer, where A is selected from the group consisting of lanthanum and neodymium, B is selected from the group consisting of strontium, barium, calcium, and lead, and x is in the range of 0 to 1, and C is selected from the group consisting of Mn, (Mnycoi-y) (y is greater than 0 and less than or equal to 1), and (MnzNii.zKz is greater than 0 and less than or equal to 1). 7 2 · The method according to item 7 i of the patent application scope, further comprising a step of forming at least one CMOS circuit in the silicon substrate. 7 3 · The method according to item 71 of the patent application scope, further comprising the step of forming a force relaxation layer under the SrgBa ^ gTiO3 layer (where g 値 is in the range of 0 to 1). 74. The method of claim 71 in the scope of patent application, the method further comprising patterning the ferromagnetic material layer, the insulating tunneling oxide layer, and the second ferromagnetic material layer to form a magnetic tunneling junction Device. 75. The method of claim 74, which further comprises the steps of: depositing a conductive material layer to cover the magnetic tunnel junction device and the CMOS circuit; and patterning the conductive material layer to form An electrical interconnection is constructed to electrically couple the CMOS circuit and the magnetic tunneling junction device. 76. Method according to item 71 of the scope of patent application, in which an insulating tunneling oxygen is deposited -38-The paper size is suitable for financial materials (CNS) A4 specification (2 dream 297 public love 1 ---- s A8 The step of the alkaline-earth metal oxide layer in nm includes the step of growing a layer having a thickness of 6 to 6 Å. 77. The method of claim 71, wherein the step of depositing an insulating warm-penetrating oxide layer includes growing an oxide layer that is thin enough to allow tunneling therefrom. 78. The method of claim 71, wherein the step of depositing an insulating through oxide layer includes the step of growing a pair of lattices of the first ferromagnetic material layer to match an oxide layer in a range of about 4 percent. 79. If the method of claim 71 is applied, the method further includes the step of depositing a single crystalline conductive oxide layer to cover the SrgBah Ti03 layer (where g 値 is in the range of 0 to 1). To guide electrical contact with the ferromagnetic material layer. 80. The method of claim 79, wherein the step of depositing a single crystalline conductive oxide layer includes the step of depositing a material selected from the group consisting of (LaieSrbOCoOs, SrRu03, SrCr03, and SrV03). A group of materials, where k is greater than 0 and less than i. 8 1 · A magnetic tunnel junction interface structure includes: a single crystalline broken substrate; a single crystalline oxide layer whose epitaxial growth grows to cover the substrate; and A magnetic tunnel junction device, which is epitaxially grown to cover the single crystalline oxide layer. -39-This paper size applies to China National Standard (CNS) A4 (210X 297 mm)